LECC 2001 WORKSHOP

CALL FOR PAPERS

Sorting Devices for the CSC Muon Trigger System at CMS
Matveev M., Padley P.
Rice University, Houston, TX, USA

Abstract

Key components of the CMS Cathode Strip Chamber (CSC) Endcap Muon trigger system are the Muon Port Cards and Muon Sorter, which perform data selection and sorting. They implement sorting "3 best objects out of 18" and "4 best objects out of 36" schemes respectively. We report on a common approach to design and construction of both boards. Board functionality and first results of logic simulation and latency estimate are presented.

Summary

The front end electronics of the Cathode Strip Chamber (CSC) Endcap Muon detector at the CMS experiment needs to calculate precise muon position and timing information and generate muon trigger primitives for the Level-1 trigger system. CSC trigger primitives (called Local Charged Tracks, LCT) are formed by anode (ALCT) and cathode (CLCT) cards. ALCT cards are mounted on chambers, while CLCT cards are combined with the Trigger Motherboards (TMB) that perform a time coincidence of ALCT and CLCT. Every CLCT/TMB card (one per chamber) transmits the two best combined anode and cathode muon tags to the Muon Port Card (MPC) which serves one CSC sector (8 or 9 chambers). The MPC selects the three best muons out of 18 possible and sends them over 100m of optical cable to the Track Finder (TF) crate residing in the underground counting room. In the current electronics layout the TF crate has 12 Sector Processors (SP), each of which receives the optical streams from several MPC. The SP measures the transverse momentum, pseudo-rapidity and azimuthal angle of each muon and sends its data (up to 3 muons each) to CSC Muon Sorter (MS) that resides in the middle of the TF crate. The MS selects the four best muons out of 36 possible and transmits them to Global Muon Trigger crate for further processing.

Two devices in the CSC trigger chain perform data sorting: the MPC ("3 best muons out of 18") and the MS ("4 best muons out of 36"). The total data reduction factor is 54. We propose a common approach to implementation of sorting logic and board construction for both the MPC and MS. They will be based on single chip programmable logic devices that receive data from the previous trigger level, sort it and transmit sorting result to the next trigger level. Programmable chips will incorporate input and output FIFO buffers that would represent all possible inputs and outputs for testing and debugging purposes. Finally we will use a common sorting scheme for both designs. The MPC and MS functionality as well as the first results of logic simulation and latency estimate are presented.

(20 March 2001)

Optical Link Evaluation for the CSC Muon Trigger at CMS
Matveev M., Nussbaum T., Padley P.
Rice University, Houston, TX, USA

Abstract

An optical link intended for trigger data transmission from the CMS Cathode Strip Chamber peripheral electronics to the counting room was evaluated. It is based on a Texas Instruments TLK2501 gigabit transceiver and a Finisar FTRJ-8519-1-2.5 optical module. Functionality of the evaluation board and results of tests are presented.

Summary

The CMS Cathode Strip Chamber electronic system consists of on-chamber mounted boards, the peripheral electronics in VME 9U crates, and a Track Finder in the counting room. Due to high operating frequency of 40.08MHz and the 100m cable run from the detector to the underground counting room an optical link is the only choice for data transmission between these systems. Our goal was to prototype an optical link intended for the communication between the Muon Port Card and Sector Processor modules using existing commercial components. Our initial design based on the Agilent HDMP-1022/1024 chipset and Methode MDX-19-4-1-T optical transceivers was reported at the 6th Workshop on Electronics for LHC Experiments a year ago. Data transmission of 120 bits representing three muons at 40 MHz would require as many as twelve HDMP chipsets and twelve optical transceivers on a single receiver card (the Sector Receiver). This solution has disadvantages such as a large power consumption and a significant area required for link components on both the transmitter and receiver boards. Studies of the later triggering stages show that a reduction in the number of bits representing three muons can be made without compromising the system performance. Another improvement is to utilize a data serialization and deserialization at 80Mhz using a low power chipset and small form factor optical modules for a more compact design. Now only three links rather than six in a previous design are needed for communication between the Muon Port Card and Sector Processor. Results of the evaluation of the Texas Instruments TLK2501 gigabit transceiver and Finisar FTRJ-8519-1-2.5 optical module are reported.

(20 March 2001)

Low Voltage Control for the Liquid Argon Hadronic End-Cap Calorimeter of ATLAS
H.Brettel^*, W.D.Cwienk, J.Fent, H.Oberlack, P.Schacht
MAX-PLANCK-INSTITUT FUER PHYSIK, Werner-Heisenberg-Institut, Foehringer Ring 6, D-80805 Muenchen

Abstract

The strategy of the ATLAS collaboration foresees a SCADA system for the slow control and survey of all sub-detectors. As software PVSS2 has been chosen and for the hardware links a CanBus system is proposed.
For the Hadronic Endcaps of the Liquid Argon Calorimeter the control system for the low voltage supplies is based on this concept. The 320 preamplifier and summing boards, containing the cold front-end chips, can be switched on and off individually or in groups. The voltages, currents and temperatures are measured and stored in a database. Error messages about over-current or wrong output voltages are delivered.

Summary

The slow control of sub-detectors and components of ATLAS is realized by a SCADA software installed in a computer net. At present it is PVSS2 from the Austrian company ETM.
Links between net nodes and hardware are realized in different ways. Between the last node and the detector electronics a CanBus is foreseen in some cases for the transfer of control signals and the survey of temperatures, supply voltages and currents.
An example are the Hadronic End Caps of the Liquid Argon Calorimeter. The application software in a PC, called PVSS2-project, has a connection to the CanBus via a driver software OPC and an interface board NICAN2 and acts as bus master. CanBus slaves are offered by the industry for several purposes. We use the ELMB from the CERN DCS group, which is tailored to our needs. It has 2 microprocessors inside and digital and analog I/O ports.
Each of the two HEC-wheels consists of 4 quadrants served by a feed-through with a front-end crate on top of it. The low voltages for 40 PSBs , the preamplifier and summing boards which contain the cold GaAs front-end chips, are delivered by a power box, installed between the fingers of the Tile Calorimeter, about half a meter away from the crates.
The input for a power box – a DC voltage in the range of 200 to 300V – is transformed into +8, +4 and -2V at the 3 output lines by DC/DC converters. At 2 control boards the lines are split into 40 channels, one for the supply of each PSB. Integrated low voltage regulators for each power line offer the possibility for individual adjustment and ON/OFF control. We use L4913 and L7913 from STm. The ELMBs and logic chips are mounted also on the control boards and establish the connection between the regulators and the CanBus.
An ELMB has 8-bit digital I/O ports. In order to make the system architecture as simple as possible and increase reliability, only 5 of the 8 bits are used. One ELMB controls 5 PSBs which belong to the same longitudinal end-cap segment. The consequence is: if an ELMB would fail, only one longitudinal segment is affectedd..
The low voltage regulators have a current limitation. The maximal current is adjusted to such a low value, that the wires in the feed-through cannot be damaged in case of a steady short circuit inside the cryostat. In addition, in case of an over-current error signal from one regulator, the logic on the control board will switch off immediately all 3 low voltage regulators related to this channel. Then the control program is informed (via the CanBus) about details of the problem.
Meanwhile tests of hard and software prototypes have been carried out successfully. The work on control boards is progressing and we are gaining more experience with the PVSS2 software.
We are considering also an emergency control system, independent of the CanBus, for the case that a computer or the bus itself would fail.

(21 March 2001)

Front-end/DAQ interfaces in CMS
G. Antchev, E. Cano, S. Cittolin, S. Erhan, W. Funk, D. Gigi, F. Glege, P. Gras, J. Gutleber, C. Jacobs, F. Meijers, E. Meschi, L. Orsini, L. Pollet, A. Racz, D. Samyn, W. Schleifer, P. Sphicas, C. Schwick

Abstract:

In the context of the CMS data acquisition system, simple and robust data links are required to transfer data from the underground counting rooms up to the surface buildings where complex processing of the data takes place. In the case of CMS, ~500 of these links, with an individual throughput of 400MB/sec over a distance of 200m, is required. The interface specification for these links as well as recent hardware developments are presented in this paper.

Summary:

After reviewing the architecture and design of the CMS data acquisition system, the requirements on the front-end data link and the different possible topologies for merging data from the front-ends are presented.  The front-end data link is a standard element for all CMS sub-detectors: its physical specification as well as the data format/protocol are elaborated within the Readout Unit Working Group where all sub-detectors are represented. The current state of the link definition is covered.
Finally, prototyping activities towards the final link as well as test/readout devices for Front-End designers and DAQ developers are described.

(4 April 2001)

Distributed Modular RT-System for Detector Control, DAQ and Trigger processing.

V.I.Vinogradov, INR RAS, Moscow, RF

Modular approach to development of Distributed Modular System Architecture for Detector Control, Data Acquisition and Trigger Data processing is proposed. Multilevel parallel-pipeline Model of Data Acquisition, Processing and Control is proposed and discussed. Multiprocessor Architecture with SCI-based Interconnections is proposed as good high-performance System for parallel-pipeline Data Processing. Tradition Network (Ethernet –100) can be used for Loading, Monitoring and Diagnostic purposes independent of basic Interconnections. The Modular cPCI –based Structures with High-speed Modular Interconnections are proposed for DAQ and Control Applications. Distributed Control RT-Systems. To construct the Effective (cost-performance) systems the same platform of Intel compatible processor board should be used.

Basic Computer Multiprocessor Nodes consist of high-power PC MB (Industrial Computer Systems), which interconnected by SCI modules and link to embedded microprocessor-based Sub-systems for Control Applications. Required number of Multiprocessor Nodes should be interconnected by SCI for Parallel-pipeline Data Processing in Real Time (according to the Multilevel Model) and link to RT-Systems for embedded Control/

(16 April 2001)

Thus, doping and intercalation of TlMC₂^VI leads to modification of their absorption spectra, change of exciton characteristics, i.e. allow optical properties to be controlled.

(20 April 2001)

The Embedded Local Monitor Board in the LHC Detector Front-end I/O Control System

Authors: B. Hallgren, H. Burckhart, H. Kvedalen
CERN, EP-ATI/CS

The ELMB is a plug-in board to be used in LHC detectors as a general-purpose system for the front-end control and monitoring. It is based on CANbus, is radiation tolerant and can be used in magnetic fields. Results of the radiation tests will be presented and examples of applications will be described.

SUMMARY

A versatile general-purpose system for the front-end detector control, the Local Monitor Box (LMB) was designed in 1998 and tested by the ATLAS sub-detector groups in test-beam and other applications. With this experience and to match better all the needs of the ATLAS sub-detector groups a modified version, the Embedded Local Monitor Board (ELMB) was designed. The main feature of the ELMB is that the ELMB now comes in the form of a general-purpose plug-in board of the size 50x67mm. The board can either be directly plugged onto the sub-detector front-end electronics, or onto a general-purpose motherboard which adapts the analog I/O signals. In order to make the ELMB available to ATLAS and other LHC experiments, which have also expressed interest, a small scale production of 300 boards for evaluation has been made by the CERN EP-ESS group in spring 2001.

The ELMB is based on the ATMEL low-power RISC microcontroller ATmega103. A second microcontroller AT90S2313 performs in system programming and monitoring functions including radiation Single Event Effects. A separate controller the Infineon SAE81C91 is used for the CANbus. The CANopen protocol has been chosen as high-level software. The ELMB can be powered remotely with the help of three low-drop power regulators. The power needed is 5V, 20 mA for the CANbus, 3.3V, 15 mA for the microcontrollers and 5V, 10mA for the ADC. The regulators function also as low-pass filters and provide current limitation and thermal protection for the ELMB. On the backside of the PCB are two high-density connectors of SMD type and optionally a 16+7 bit delta-sigma ADC with 64 differential inputs. There are up to 34 digital I/O lines available. The ATmega103 runs at a clock speed of 4 MHz. It has 128 kbytes of on-chip flash memory, 4 kbytes of SRAM and 4 kbytes of EEPROM. Also when the ELMB is installed in the detector it is possible to program the flash memory of the processors using the In-System Programming feature of the processors via the CAN bus.

A motherboard is available in order to evaluate the ELMB and for non-embedded applications. On the backside it contains two 100-pin SMD connectors for the ELMB and sockets for adapters for the 64 channel ADC. There are adapters available for different temperature sensors like NTC resistors, 2 wire Pt1000 and 4 wire Pt100 sensors. The motherboard may be mounted in DIN rail housing of the size 80 x 190 mm. On the front side there are connectors for the ADC inputs,
digital ports, a SPI interface, CAN interface and power connectors.
The environmental requirements are such that it can be used in the ATLAS cavern (USA15) outside of the calorimeter in the area of the muon detectors (MDTs) and further out. This implies tolerance to radiation up to about 5 Gy and 3E10 neutrons/cm2 for a period of 10 years and to a magnetic field up to 1.5 T. Several radiation tests of the ELMB have been made following the procedures as laid out by the ATLAS radiation policy. The results of TID tests made at Pagure, Saclay and GIF, CERN with different dose rates will be reported. Further neutron testing at Prospero and SEE tests at Cyclone/Louvain-la-Neuve are planned for spring and summer 2001. The ELMB was also tested for a week at 100 degrees for accelerated ageing corresponding to 40000h at 25 degree C.

DIALOG: an Integrated Circuit for front-end Logics, Diagnostics and Time Alignment in the LHCb muon system.

S. Cadeddu, A. Lai*
INFN Sezione di Cagliari, Cittadella Universitaria, 09042 Monserrato (Cagliari) - Italy
*Corresponding author, tel +39-070-6754913, email adriano.lai@ca.infn.it.

Abstract

We present a custom integrated circuit, developed in the IBM 0.25 micron technology. The chip is named DIALOG ((DIagnostics, time Adjuster and LOGics) and it is a fundamental ingredient of the LHCb muon front-end electronics. Each integrated circuit handles 16 front-end channels. The circuit generates the information used by the level 0 trigger starting from the front-end signals, by means of a suitable (programmable) logical combination. In addition, it integrates functionalities important for signal time-alignment and front-end channels diagnostics at run time.

Summary

The LHCb muon system supplies binary information, used by the fast L0 muon trigger. Nevertheless, the information used by the trigger does not coincide with the signals as output by the front-end Amplifier-Shaper-Discriminators (ASD). This is due to single channel maximum capacitance and sustainable rates. So, an important task of the electronics system is to generate trigger information, corresponding to 26,000 so called logical channels, starting from about 120,000 ASD signals, called physical channels. In order to minimize the number of links (and costs), such a function is performed on detector by DIALOG, our custom integrated circuit. The logical combinations necessary to generate the logical channels are different, according to the different detector regions. Consequently, DIALOG is configurable by writing suitable internal registers, which are accessible via an I2C interface. DIALOG is also important to time-align logical channels, in order to correctly synchronize the entire detector. This task is crucial for all the LHC experiments. DIALOG integrates 16 programmable delays, which allow shifting the signal phase by 32 steps of about 1.5 ns each. This covers two bunch-crossing periods. The programmable delays are used when setting up the detector before data taking, but can be re-programmed at any needed time by writing suitable internal registers. DIALOG contains also diagnostics features to distribute synchronous pulses to the ASD channels and to monitor the physical channels' activity. Moreover, it contains DAC’s to supply voltage thresholds to the front-end discriminators. All these functions are controlled via the I2C interface.
DIALOG is being developed in the IBM 0.25 micron radiation hard technology. We plan to submit a first version in the next August run. We present the circuit internal scheme and layout and some characterizing simulations.

A 10uV-offset DMILL opamp for ATLAS LAr calorimeter

C. de La Taille, J.P. Richer, N. Seguin-Moreau, L. Serin
LAL Orsay FRANCE

In order to calibrate the LAr calorimeter to 0.25% accuracy, precision pulsers have been designed to provide a fast and precise pulse that simulates the detector pulse over its full 16bit dynamic range. They are based on a precision DC current source (2uA-200mA) built with a low offset opamp and a 0.1% 5ohm external resistor. Several COTs having failed the irradiation tests, a custom chip has been designed and fabricated, first in AMS 0.8um BiCMOS and then in DMILL. It has been successfully tested and the electrical performance and irradiation results will be shown."

Design of ladder EndCap electronics for the ALICE ITS SSD.

(For the ALICE collaboration)

Abstract

The design of the control electronics of the front-end of the ALICE SSD is described. This front-end is build with the HAL25 (LEPSI) chip. The controls are placed in the ladder EndCap. The main EndCap functions are power regulation and latch-up protection for the front-end, control functions for the local JTAG bus, distribution of incoming control signals for the front-end and buffering of the outgoing analog detector data. The system uses AC-coupled signal transfer for double-sided detector readout electronics.

Due to radiation-, power-, and space requirements, two ASIC’s are under development, one for analog buffering and one with all other functions combined.

Summary

The ALICE ITS is build out of three layers, Pixel-, Silicon Drift- and Silicon Strip Detectors. For the SSD the development of the control-electronics inside the detector volume will be described.

The SSD is based on Double Sided Silicon Strip Detectors with 768 strips at each side. The detectors will be readout by the HAL25 (Hardened Alice128 in .25u CMOS) front-end chip developed by LEPSI Strasbourg.

The SSD consists of 2 layers of ladders, the inner with 34 and the outer with 38 ladders. The inner ladders contain 23 modules and the outer 26. The detector modules will be connected to the DAQ- & Control system via EndCap units mounted at the end of each side of the ladder. The available space is ~ 70x70x45 mm.

Since ALICE is a heavy-ion experiment the electronics must be susceptible for Single Event Effects (SEE). Total dose is not a big issue although levels up to ~50krad may not cause any degradation. Therefore the front-end chip and the electronics in the EndCap must be protected for latch-up and are now build in radiation tolerant technologies. The limited available space and the temperature constraints of the detectors (and environment) require a low power design.

Due to the use of double-sided detectors, the readout electronics on both sides operate at different potentials. To avoid ADC and control modules to operate at these bias potentials, all signals will be AC coupled to the corresponding voltage level. Also the analogue readout data will be AC coupled to a multiplexer/buffer, which is able to drive the differential signal to ADC modules (over 10m @ 10MHz). The front-end chips of the detector modules are readout in series, both the P- and N side of each detector module to one ADC channel.

The Low Voltage power for the front-end (2.5V) for the two bias levels is regulated inside the EndCap. This circuit not only provides the latch-up protection for the front-end but also for the control electronics and buffers in the EndCap itself.

The Front-end electronics is controlled via the JTAG bus and it is also used to monitor and control the EndCap functions. Errors like latch-up can be monitored and appropriate action can now be taken. Disabled front-end chips can be put in "by-pass" mode and this information is available for the DAQ system.

All previously mentioned functions of the EndCap will be integrated in two ASIC’s, one analog multiplexer/buffer (ALABUF) and one multipurpose control chip (ALCAPONE). This development is done using a commercial technology (0.25u CMOS) with radiation tolerant design techniques.

The multipurpose control chip houses a Bandgap reference (CERN), Regulator circuit with DAC (ALICE PIXEL or LEPSI), JTAG control, LVDS and CMOS buffers for AC coupling, ADC for monitoring and digital control functions for the front-end. Simulations of the analogue functions show good feasibility for use in the EndCap, tests after irradiation should clarify if this approach gives a satisfactory result for the EndCap design.

The regulator and the analog multiplexer/buffer circuits have been submitted to a MPW test run and test results will be compared with simulated data and discussed.

A Radiation Tolerant Gigabit Serializer for LHC Data Transmission
P. Moreira (1), T. Toifl (2), A. Kluge (1), G. Cervelli (1), F. Faccio (1), A. Marchioro (1) and J. Christiansen (1)

ABSTRACT
Gbit/s data transmission links will be used in several LHC detectors in trigger and data acquisition systems. In these experiments, the transmitters will be subject to high radiation doses over the experiment's lifetime. In this work, a radiation tolerant transmitter ASIC is presented. It supports two standard data transmission protocols, the G-Link and the Gbit-Ethernet, and sustains transmission of data at both 800 Mbit/s and 1.6 Gbit/s. The ASIC was implemented in a mainstream 0.25um CMOS technology employing radiation tolerant layout practices. A prototype was tested and its behavior under total dose irradiation as well as its susceptibility to single event upsets was studied. The experimental results are reported in the paper.

SUMMARY
Several LHC detectors require high-speed (~ Gbit/s) digital optical links for transmission of data between the sub-detectors and the data acquisition systems. Typically, high-speed data transmission is required for both the trigger systems data path and the data readout systems. In general, those links will be unidirectional with the transmitters located inside the detectors and the receivers situated in the counting rooms. Due to the proximity to the collision point, the transmitters will be subject to high levels of radiation doses over the lifetime of the experiments. Additionally, the large numbers of high-speed optical links planned (of the order of 100K total for the four LHC experiments) impose strict constraints on device cost. Moreover, in trigger links, data has to be transmitted with constant latency and synchronously with the LHC 40.08 MHz reference clock - this to facilitate data alignment at the receiving end before the data is fed to the trigger processors. Although commercial optical links and components can be found that meet the bandwidth requirements of all of the LHC planned systems, those components generally have not been designed to withstand high levels of total dose irradiation. The few radiation-hardened devices, which exist on the market, have prohibitively high prices when the large number (~ 100K) of links required is taken into account. It was thus considered necessary to develop a dedicated solution that would meet the very special requirements of the High-Energy Physics (HEP) environment. Since only the transmitters will be subject to irradiation, only they need to be developed and qualified for radiation tolerance.
In this paper, a radiation tolerant ASIC developed for data transmission at both 800 Mbit/s and 1.6 Gbit/s is reported. The data format and encoding were chosen so that the transmitter can be operated with either a Gigabit Ethernet or a G-Link "commercial of the shelf" receiver. The IC was fabricated in a mainstream 0.25um CMOS technology using radiation tolerant layout practices. The paper will describe in detail the circuit architecture and its functionality. Emphasis will be given to the presentation of experimental results reporting on the robustness of the design against total dose irradiation effects and on the behavior of the device under ionizing radiation that gives origin to single event upsets (SEU). To assess the techniques used to improve the robustness against SEU phenomena, a performance comparison will be established with a previously developed 1.2Gbit/s serializer prototype.

1. CERN-EP/MIC, Geneva, Switzerland
2. IBM Research, Zurich, Switzerland

Correspondin author:
Paulo Moreira
EP Division
CERN
Email: Paulo.Moreira@cern.ch

Performance of the Beetle Readout-Chip for LHCb


Authors list:
----------
Niels van Bakel, Jo van den Brand, Hans Verkooijen
(Free University of Amsterdam / NIKHEF Amsterdam)
Daniel Baumeister, Werner Hofmann, Karl-Tasso Knoepfle,
Sven Loechner, Michael Schmelling
(Max-Planck-Institute for Nuclear Physics, Heidelberg)
Martin Feuerstack-Raible
(University of Heidelberg)
Neville Harnew, Nigel Smale
(University of Oxford)
Edgar Sexauer
(now at Dialog Semiconductors, Kirchheim-Nabern, Germany)


Abstract:
--------
The Beetle front end chip for LHCb is a 128 channel pipeline chip developed in 0.25 um standard CMOS technology. After intensive testing of the first version (Beetle1.0), an improved design (Beetle1.1) has been submitted in March 2001. The key measurements on the Beetle1.0, which mainly drove the design changes for the Beetle1.1, are described together with first performance data of the new chip.

Summary:
-------
A 128 channel readout chip, the Beetle, has been developed for the LHCb experiment in 0.25 um standard CMOS technology. The latest design has been submitted in March 2001. The chip can be operated as analog or alternatively as binary pipelined readout chip and fulfills the requirements of the silicon vertex detector, the inner tracker, the pile-up veto trigger and the RICH in case of  multianode photomultiplier readout.

The chip integrates 128 channels with low-noise charge-sensitive preamplifiers and shapers. The risetime of the shaped pulse is 25 ns, the spill-over left 25 ns after the peak at most 30%. A comparator per channel with configurable polarity provides a   fast binary signal. Four adjacent comparator channels are being ORed and brought off chip via LVDS ports. Either the shaper- or the comparator output is sampled with the LHC-bunch-crossing frequency at 40 MHz into an analogue pipeline with a programmable latency of max. 160 sampling intervalls and an integrated derandomizing buffer of 16 stages. For analog readout the data are multiplexed with up to 40 MHz onto 1 or 4 ports. A binary readout mode operates with doubled output rate on two ports. Current drivers bring the serialized data off chip. The chip can accept trigger rates of up to 1 MHz, the readout time per event is within 900 ns. For testing and calibration purposes, a charge injector with adjustable pulse height is implemented. The bias  settings and various other parameters can be controlled via a standard I2C-interface.

The first chip version (Beetle1.0) submitted in April 2000 had to be patched with a focused ion beam to be functional. The reason was a layout bug in the control circuit. Beetle1.1 fixes this bug. In addition it solves a problem with the bias network of the pipeline readout amplifier, avoids charge injection in the switch of the
resetable amplifier and fixes an error inside the multiplexer. The measurements pointing out bugs and problems on Beetle1.0 are presented, the resulting design modification on the Beetle1.1 are described and first performance measurements with the new readout chip are shown.

TTCPR: A PMC RECEIVER FOR TTC

John W. Dawson, David J. Francis, William N. Haberichter,
and James L. Schlereth

Argonne National Laboratory and CERN

The TTCPR receiver is a mezzanine card intended for use in distributing TTC information to Data Acquisition and Trigger Crates in the Atlas Prototype Integration activities. An original prototype run of these cards was built for testbeam and integration studies, implemented in both the PMC and PCI form factors, using the TTCrx chips from the previous manufacture. When the new TTCrx chips became available, the TTCPR was redesigned to take advantage of the availability and enhanced features of the new TTCrx, and a run of 20 PMC cards was manufactured, and has since been used in integration studies and the testbeam. The TTCPR uses the AMCC 5933 to manage the PCI port, an Altera 10K30A to provide all the logic so that the functionality may be easily altered, and provides a 4K deep FIFO to retain TTC data for subsequent DMA through the PCI port. In addition to DMA's which are mastered by the Add On logic, communication through PCI is accomplished via mailboxes, interrupts, and the Pass-thru feature of the 5933. An interface to the I2C bus of the TTCrx is provided so that internal registers may be accessed, and the card supports reinitialization of the TTCrx from PCI. Software has been developed to suport operation of the TTCPR under both LynxOS and Linux.

Development of the Pixel Detector Module for the BTeV Experiment at Fermilab

S. Zimmermann, J. Andresen, J.A. Appel, G. Cardoso, D.C. Christian, B.K. Hall, J. Hoff, S.W. Kwan, A. Mekkaoui, R. Yarema.

Fermi National Accelerator Laboratory
P.O. Box 500
Batavia, IL 60510
USA

Abstract

At Fermilab, a pixel detector multichip module is being developed for the BTeV experiment. The module is composed of three layers. The lowest layer is formed by the readout ICs. The back of the ICs are in thermal contact with the supporting structure while the other side is bump-bonded to the pixel sensor. A low mass flex-circuit interconnect is glued on the top of this assembly, and the readout IC pads wire-bounded to the flex circuit. This paper will present recent results on the development of a module prototype and summarize its performance characteristics.

Summary

At Fermilab, the BTeV experiment has been approved for the CZero interaction region of the Tevatron. The innermost detector for this experiment will be a pixel detector composed of 64 pixel planes of approximately 100 mm by 100 mm each, assembled perpendicular to the colliding beams and installed a few millimeters from the beams. Each plane is formed by sets of hybridized modules, each composed of a single active-area sensor and of one row of readout integrated circuits (ICs).
The pixel detector will be employed for on-line track finding for the lowest level trigger system and, therefore, the pixel readout ICs will have to transfer data for all detected hits. This requirement imposes a severe constraint on the design of the readout IC, hybridized module, and data transmission. Several factors affect the amount of data that each IC needs to transfer:  readout array size, distance from the beam, number of bits of pulse height information, the data format, etc. Presently, the most likely dimension of the pixel chip array will be 128 rows by 22 columns.
The BTeV pixel detector module is based on a design relying on a hybrid approach. With this approach, the readout chip and the sensor array are developed separately and the detector is constructed by flip-chip mating the two together. This method offers maximum flexibility in the development process, choice of fabrication technologies, and the choice of sensor material.
The module is composed of three layers. The lowest layer is formed by the readout ICs. The back of the ICs are in thermal contact with the supporting structure while the other side is bump-bonded to the pixel sensor. The low mass flex-circuit interconnect is glued on the top of this assembly and the readout IC pads wired-bounded to the flex-circuit. The module is remotely controlled by the pixel Data Combiner Board, located approximately 10 meters away from the detector. All the controls, clocks and data are transmitted between the pixel module and the data acquisition system by differential signals employing the LVDS standard. Common clocks and control signals are sent to each module and then bussed to each readout IC. All data signals are point to point connected to the Data Combiner Boards.
A prototype module using the FPIX1 IC has been characterized. However, differently from the proposed "sandwich" module, the flex-circuit of this prototype is located on the side of the ICs. Typical results include threshold of 1500 electrons, threshold dispersion of 280 electrons and noise of 60 electrons. The comparison of these results with the characterization  results of a single FPIX1 IC board shows no observed degradation in performance. Furthermore, tests with dead-time-less mode, where the charge inject in the front end is time swept in relation to the readout clock also does not reveal any degradation in performance, suggesting no crosstalk problems between the digital and analog sections of the FPIX1 IC and the flex-circuit.

<Corresponding Author Information>
First Name: Kazumi
Last Name: Hasuko
E-mail hasuko@icepp.s.u-tokyo.ac.jp
Institute: University of Tokyo
Address: 7-3-1 Hongo
Bunkyo-ku, Tokyo 113-0033
Country: JAPAN

<Paper Category>
Experiment: ATLAS
Topic: Detector control and real time systems

A Remote Control System for On-Detector VME Modules of the ATLAS Endcap Muon Trigger

Author List:
K. Hasuko(1), C. Fukunaga(5), R. Ichimiya(3), M. Ikeno(2), Y. Ishida(5), H. Kano(5), Y. Katori(1), T. Kobayashi(1), H. Kurashige(3), K. Mizouchi(4), Y. Nakamura(1), H. Sakamoto(4), O. Sasaki(2) and K. Tanaka(5)

(1) International Center for Elementary Particle Physics (ICEPP), University of Tokyo
(2) High Energy Accelerator Research Organization (KEK)
(3) Department of Physics, Kobe University
(4) Department of Physics, Kyoto University
(5) Department of Physics, Tokyo Metropolitan University

Abstract :
We present the development of a remote control system for on-detector VME modules of the ATLAS endcap muon trigger. The system consists of a local controller in an on-detector VME crate and  a remote interface in a Readout Driver crate. The controller and interface are connected with dedicated optical links based on G-LINK. The control system can fully configure and control modules, especially FPGA-embedded ones using G-LINK words and VME bus from remote host. The system supports periodical readback and reconfiguration to assure correct configuration data against SEUs. The idea, prototype and initial performance tests of the system are discussed.

Summary :

We present the development of a remote control system for on-detector VME modules of the ATLAS endcap muon trigger. Such the VME modules are Star Switch (SSW) and High-pT board (HPT); the remote control system fully controls and configures them from outside of detector.

SSW is a relay module between on-detector modules and Readout Driver (ROD). SSW receives hit information from readout buffers in the modules, performs data reduction and formatting, and transfers the results to ROD. SSW is based on FPGAs which should be configured and controlled  by the remote control system. Since the configuration data are susceptible to  radiation-induced upsets (SEUs), dedicated control and configuration links are necessary, and every configuration should be assured to be correct via the links.

The other module, HPT, is a part of trigger system. HPT is based on ASIC configured with some registers inside and fully controlled via the same links from outside.
The remote control system consists of HPT/SSW Controller (HSC) and   Control/Configuration Interface (CCI). HSC is a local controller in a HPT/SSW VME crate. CCI is a remote interface in a ROD crate. HSC communicates with the ROD host via CCI. HSC and CCI are connected with optical links based on G-LINK. The links are dedicated for control and configuration. The host manages an instruction set; each instruction is encoded into 14-bit G-LINK control word and executed on HSC.  When downloading data, additional 16-bit data words are used. Following instructions, HSC can master the VME bus to access  the HPT/SSW modules through VME protocol encoders implemented in CPLDs on both HSC and HPT/SSW modules. All the control and configuration are performed via VME accesses.

FPGAs in SSWs are also configured via the VME bus using byte-based configuration scheme.   To resist SEUs, configuration data are periodically read back. Once a SEU is detected, the accessed FPGA is instantly reconfigured. The CPLDs as VME protocol encoders are configured with JTAG provided on the VME backplane. These JTAG signals are in a bus structure and mastered by an embedded JTAG controller on HSC with dedicated instructions. Most of the HSC functionalities are also built using CPLDs; they are configured with the same JTAG bus. Only the core part of instruction encoders on HSC manages the
JTAG-related instructions and built using an ASIC to resist SEUs. Therefore all the related CPLDs are configurable using the JTAG provided
via the ASIC encoder.

The detailed idea, prototype and initial performance tests of the HSC/CCI control system are discussed in this workshop. We will also discuss that the performance meets the requirements for controlling and configuration of HPT and SSW modules.

We report on the status of the evaporative cooling system, on the plans for the detector control system and upon the performance and irradiation tests of the interlock box.

Production and Radiation Tests of A TDC LSI for the ATLAS Muon Detector

Authors :
Yasuo Arai
KEK, National High Energy Accelerator Research Organization
Institute of Particle and Nuclear Studies
and
T. Emura
Tokyo University of Agriculture and Technology

Abstract :

ATLAS Muon TDC (AMT) LSI has been successfully developed and performance of a prototype chip (AMT-1) was reported in the LEB 2000. A new AMT chip (AMT-2) was developed aiming for mass production. The AMTs were processed in a 0.3 um CMOS Gate-Array technology, To proceed to a mass production of 400 k channels (~17,000 chips) scheduled in 2002, a systematic test methods must be established. Furthermore, the chip must be qualified to have adequate radiation tolerance in ATLAS environment.The test method and results of the radiation tests for gamma rays and charged particles will be presented.

Summary :

A TDC LSI for the ATLAS precision muon tracker (MDT) has been developed. The TDC chip, called AMT, was processed in a 0.3 um CMOS Gate-Array technology. It contains 24 input channels, 256 words level 1 buffer, 8 words trigger FIFO and 64 words readout FIFO. It also includes trigger-matching circuit, which selects data according to a trigger. The selected data are transferred through 40 Mbps serial line. By using a Phase Locked Loop (PLL) circuit, it achieved 300 ps timing resolution. The chip is packaged in a 144 pins plastic QFP with 0.5 mm pin pitch and about 110k gates are used.

A prototype chip, AMT-1 was successfully tested and reported in the last LEB workshop. The AMT-1 was mounted in a front-end PC board with ASD
(Amp/Shaper/Discri) chips, and system tests connected to a detector have been done (submitted in this workshop).

A mass-production prototype chip, AMT-2, has been recently developed. Although the AMT-1 was successfully operated, it consumed relatively large
power in inside LVDS receiver circuits. A low-power LVDS receiver was developed and included in the AMT-2. In addition, testability was enhanced
and several minor bugs are also fixed.

Mass production of 400 k channels (~17,000 chips) are scheduled in an early period of 2002. Most of the chip tests are done in manufacture, but a
systematic test system are still needed. Furthermore the chip must be qualified to have adequate radiation tolerance in ATLAS environment.
Gamma-ray irradiation to measure Total Ionization Damage (TID) and proton irradiation to measure Single Event Effects (SEE) are planned.

Test methods and results of the radiation tests will be presented.

ICEPP
University of Tokyo
7-3-1 Hongo,
Bunkyo-ku,
Tokyo 113-0033
Japan

Tel: +81 3 3815 8384
Fax: +81 3 3814 8806
E-mail: imori@icepp.s.u-tokyo.ac.jp

Abstract
The article describes a network of high voltage power supplies which can work efficiently under a magnetic field of 1.5 tesla. The high voltage power supply incorporates a piezoelectric ceramic transformer. The power supply includes feedback to stabilize the high voltage output, supplying from 2000V to 4000V with a load of more than 20 megohm at efficiency higher than 50 percent. The high voltage power supply includes a Neuron chip, a programming device processing a variety of input and output capabilities. The chip can also communicate with other Neuron chips over a twisted-pair cable, which allows establishing a high voltage control network consisting of a number of power supplies each of which incorporates the chip individually. The chip sets the output high voltage. The chip detects the
short circuit of the output high voltage and controls its recovery. The chip also monitors the output current. The functions of the power supply under the control of the chip are managed through the network. The high voltage power supplies are networked, being monitored and controlled through the network.


Summary

Network-Controlled High Voltage Power Supplies Operating in Magnetic Field High Voltage Power Supply

The article describes a network of high voltage power supplies. The high voltage power supply includes feedback to stabilize the high voltage output, supplying from 2000V to 4000V with a load of more than 20 megohm at efficiency higher than 50 percent. The power supply incorporates a ceramic transformer. So the power supply can be operated efficiently under a magnetic field of 1.5 tesla. The power supply could be utilized in LHC experiments. The power supply includes an error amplifier and a voltage-controlled oscillator (VCO). The output voltage is fed to the error amplifier to be compared with a reference voltage. The output of the error amplifier is supplied to the VCO which generates the frequency of a carrier where the carrier drives the ceramic transformer. Voltage amplification of the transformer depends on the frequency of the carrier. So the feedback adjusts magnitude of the amplification by controlling the frequency.

Breakdown of Feedback
While the load of the power supply falls within an allowable range, the driving frequency is maintained higher than the resonance frequency of the transformer such that the feedback is negative as designed. The allowable range of load cannot cover, for example, short-circuiting the output high voltage to ground. When the load deviates beyond the allowable range, the driving frequency may decrease below the resonance frequency; a condition that will not provide the required negative feedback, i.e., positive feedback locks the circuit such that it is independent of load.

Network
The high voltage power supply includes a "Neuron" chip possessing a variety of input and output processing capabilities. The Neuron chip can communicates with other Neuron chips over a twisted-pair cable; a feature that allows establishing a network consisting of a number of power supplies that respectively incorporate the chip. Since most functions of the power supply is brought under the control of the chip, the power supplies are managed via the network.

Output High Voltage
The reference voltage is generated by a digital-to-analog converter controlled by the chip so that the output high voltage can be controlled by the network.

Recovery from Feedback Breakdown
The VCO voltage, being the output of the error amplifier, controls the driving frequency of the carrier. The feedback breakdown is produced by deviation of the VCO voltage from its normal range. The deviation is detected by voltage comparators, interrupting the Neuron chip. Once awakened, the chip reports the feedback
breakdown and manages the power supply so as to recover from the breakdown.

Current Monitor
If both the output high voltage and the supply voltage are known before hand, the frequency at which the transformer is driven depends on the magnitude of the load. The output current can be estimated from the driving frequency. The chip gets the driving frequency by counting pulses, which allows calculating the output current.

References

M. Imori, T. Taniguchi and H. Matsumoto, "Performance of a Photomultiplier High Voltage Power Supply Incorporating a Piezoelectric Ceramic Transformer,"IEEE Trans. Nucl. Sci., vol. 47, no. 6, pp. 2045-2049, Dec. 2000.
Y. Shikaze, M. Imori, H. Fuke, H. Matsumoto and T. Taniguch, "Performance of a High Voltage Power Supply Incorporating a Ceramic Transformer, "Proceedings of the 6th Workshop on Electronics for LHC Experiments, pp.371-375, Sept. 2000, Krakov, Poland, To be published in IEEE Trans. Nucl. Sci.

On the developments of the Read Out Driver for the ATLAS Tile Calorimeter
Authors: Jose Castelo, Vicente Gonzalez, Enrique Sanchis
Afiliation: IFIC and Dpt of Electronic Engineering. University of Valencia

Abstract: "This works describes the present status and future evolution of the Read Out Driver for the ATLAS Tile Calorimeter. The developments currently under execution include the test of the adapted LAr ROD to Tile Cal needs and the design and implementation of the PMC board for algorithm testing at ATLAS rates. We will describe the test performed at University of Valencia with the LAr ROD motherboard and a new developped transition module with 4 SLINK inputs and one output which match the initial TileCal segmentation for RODs. We will also describe the work going on with the design of a DSP based PMC with SLINK input for real time data processing to be used as a test environment for optimal filtering."

(We would like to present this work as a poster)
DSDC - Grupo de Diseño de Sistemas Digitales y de
Comunicación
Dept. Ingenieria Electronica. Universitat de Valencia
<vicente.gonzalez@uv.es>
Avda . Dr. Moliner, 50
Burjassot
Valencia
46100
Spain
Fax: +34 96 316 0466
Work: +34 96 316 04

DEVELOPMENT OF AN OPTICAL DATA TRANSFER SYSTEM FOR THE LHCb RICH DETECTORS

N.Smale, M.Adinolfi, J.Bibby, G.Damerell, N.Harnew, S.Topp-Jorgensen
University of Oxford, UK

V.Gibson, S.Katvars, S.Wotton
University of Cambridge, UK

K.Wyllie
CERN, Switzerland

Abstract

Development of a front-end readout system for the LHCb Ring Imaging Cherenkov (RICH) detectors is in progress. The baseline solution for the RICH detector readout electronics is the HPD Binary Pixel chip. This paper describes a system to transmit data with addresses, error codes and synchronisation from a radiation harsh environment. The total data read out in 900ns is 32x36x440 bits per L0 trigger, with a sustained L0 trigger rate of 1MHz. Multimode fibres driven by VCSEL devices are used to transmit data to the off-detector Level-1 electronics located in a non-radiation environment. This data is stored in 64Kbit deep QDRbuffers.


Summary

There are six stages in processing the pixel data and delivering them to the Level-1 buffer. The Level-0 radiation-hard region has an interface to/from the pixel chip, parallel /serial conversion, fibre optics and drivers. The Level-1 non-radiation region has a fibre optic receiver, serial/parallel conversion, data checking and Level-1 buffer storage. Each are described in turn.


The pixel interface: 'PInt'

The pixel chip requires an interface chip (PInt) that generates chip biasing and calibration test levels, handles the ECS (Experiment Control System) and TTC (Timing and Trigger Control). The interface adds error codes, addresses, parity and Beam crossing ID to the data. The data are synchronised to a Gigabit Optical Link (GOL). The PInt is being developed using a Spartan II FPGA chip, and then later ported into a 0.25uM CMOS radiation-hard ASIC.


Parallel to serial conversion

The GOL chip is a multi-protocol high-speed transmitter ASIC which is able to withstand high doses of radiation. The chip is run in the G-Link mode at 800Mbits/s and therefore transmits 20 bits of data in 25nS. There are 16 bits of data and 4 overhead bits for encoding. The CIMT (Conditional Invert Master Transition) encoding scheme is employed. The 20-bit word is then serialised and transmitted via a VCSEL (Vertical Cavity Surface Emitting Laser) and multimode fibres. The threshold of the laser driver may be adjusted during the lifetime of the experiment with the GOL chip.


Fibre Optic Drivers

VCSELs emit light perpendicular to their p-n junctions, high output luminosity and focussing allows for easy coupling to multimode fibres. Wavelengths are generally in the 760-960nm range and output power is typically 5mW for a multimode fibre. VCSEL arrays can be easily incorporated into single ICs which allow for a much better multiple-fibre package. The VCSELs have been proven to be very robust in terms of radiation and magnetic fields. The proposal is to use 2 VCSELs per pixel chip and drive the data over 80 metres of multi-mode fibre to the counting room at 800Mb/s.


The fibre optic receiver and serial to parallel converter

The data are to be received by a pin diode and processed by either a Hewlett Packard HDMP1034 or the Texas Instruments TLK2501IRCP.


Data checking and Level-1 storage.

Data arriving from the serial/parallel converter are in a 16 bit wide 36 bit deep format, received at a rate of 640Mbits/s. The data contain header and error codes that require checking and stripping so as to leave 32x32 bits of raw data. The raw data, with event ID, are proposed to be time multiplexed and stored in the Level-1 buffer. The Level-1 buffer is a commercially available QDR SRAM (Quad Data Rate SRAM). The QDR SRAM is a memory bank of 9Mbits and can be segmented into multiple 64K bit deep Level-1 buffers. Data can be read in and read out on the same clock edge at a rate of 333Mbits/sec. For the QDR control and address generation a Spartan II FPGA is proposed. The Spartan II is chosen for it's high performance and I/O count at a low cost. The other functions of the Spartan II are to process the data from the serial/parallel converter, interface to the ECS and TTC.


Conclusion

The readout scheme will be presented with results for bit error rates and synchronisation checking. Full compatibility with TTC and ECS for the whole integrated system will be demonstrated.

Radiation Tests on Comercial Instrumentation Amplifiers, Analog Sw., DAC’s & ADC’s

3 Universidad Complutense (UCM), Electronics Dept., Madrid, Spain.

Abstract

A study of several comercial instrumentation amplifiers (INA110, INA111, INA114, INA116, INA118 & INA121) under neutron and very low gamma radiation was done. Some parameters (Gain, CMRR, input offset voltage, input bias currents) were measured on-line and bandwith, slew rate and supply current were determined before and after radiation. Different digital-to-analog and analog-to-digital converters were tested under radiation . Finally, the results of the testing of some voltage reference and analog switchs will be shown.

Summary

Commercial instrumentation amplifiers have been tested: INA110 (fast settling time FET-Input amplifier), INA111 (High speed FET-input amplifier), INA114 & INA118 (bipolar instrumentation amplifier), INA116 (DiFET instrumentation amplifier) and INA121 (low power FET-Input instrumentation amplifier). Input offset voltage, input bias currents, differential gain and CMRR were measured under the irradiation once every 20 minutes during 5 days. After the irradiation, other parameters as slew rate, supply currents and bandwidth were measured.

It was observed that JFET-input, designed to have an excellent frecuency response, exhibit the best behaviour. On the other hand, the worst is a DiFET amplifier because its destruction happened quickly. This is a great surprise because, in early papers, it was found that the best operational amplifiers under neutron radiation were built in this technology. Most of other amplifiers were destroyed during the irradiation.

It was observed a growth of the input offset voltage and the bias currents. Differential gain remains constant upto a value of radiation wich depends on the different amplifiers. CMRR behaves in a similar way. In all the amplifiers that survived, the supply currents decrease and the frecuency response is degradated. The value of slew rate and bandwidth is lower and output signal is very distorted in the more irradiated amplifiers.

In MX7541 digital-to-analog converter a great increase of output current offset and integral non-linearity error were observed but gain error keeps constant until a total dose (3-5·10¹² cm^-2, 150 Gy) which destroy the converter. In this moment, a reduction of the number of output voltage levels was observed. Before the destruction, this number was reduced to 16, 8, 4 and none. The converter did not come back to work after the annealing. It is possible that the converter destruction was due to the vestigial gamma dose because an alike converter, AD7541 from Analog Devices, is reported to be destroyed at similar levels of gamma dose.

The study of the parameters of ADS1210 analog-to-digital converter has been carried out.

The resistance and the leakage current of DG412 analog switches were also measured. It was observed a high increase of the switch resistances. The initial value was 20-30 ohms but the last values obtained before the destruction was 80-100 ohms. It was observed an increase of the leakage current (absent in the beginning, it can reach 1 mA). The aparition of this current is due to the action of gamma rays that form charges inside the oxide of the MOSFET transistors and the oxide that covers the semiconductor. However, the growth of resistance value is due to the neutron radiation.

With respect to REF102 voltage reference, it was observed an increase of line regulation and, also, the lowest voltage needed to obtain the nominal output voltage moved from 12 volts to 16-20 volts.

Development of Radiation Hardened DC-DC converters for the  ATLAS Liquid Argon Calorimeter

Helio Takai and James Kierstead
Brookhaven National Laboratory

The power supplies for the ATLAS liquid argon calorimeter using 300V input DC-DC converters will be located in a high radiation environment. Over the life of the experiment (i.e. 10 years) the total ionizing dose is expected to reach 25 krad. Along with the total dose is a projected total fluence of 2x10^12 particles/cm^2 of 1 MeV equivalent neutrons of which a fraction of the total neutron fluence, 1x10^11 neutrons/cm^2, has energies above 20 MeV. These values include the standard ATLAS recommended safety factors. The anticipated effects in order of potential seriousness are: (a) single event burnout (SEB) of the input power MOSFET, (b) total dose effects on active CMOS and bipolar components and (c) neutron induced lattice displacements causing conductivity and other changes in active components. The power supply will also be subjected to a magnetic field at a strength of 50 Gauss.

Tests performed on commercially available modules manufactured by Vicor found that none satisfy the requirements. Therefore we are seeking a solution that involves a semi-custom design. This typically introduces questions of reliability and cost. The approach for the development of a prototype is to select a vendor with experience in designing power supplies for radiation environments, e.g. space environments. This provides some assurance that the power supply will be hardened to ionizing and neutron radiation. Then to reduce cost, the radiation hardened power MOSFET will be replaced with a less expensive commercial power MOSFET. It is known that by operating a commercial MOSFET at a lower (derated) voltage it is possible to use them safely in an environment with high-energy particles. For instance a 600 volt MOSFET operated at 500 volts might show a large SEB cross section but has a negligible SEB cross section at 300 volts.

We will report on the progress of the design and comment on the different practical issues of the process such as purchasing of components in lots and specifying parts. Results of power MOSFET qualification will also be presented as well as preliminary test results. Packaging and operational issues will also be discussed as time allows.

Title: PRINTED CIRCUIT BOARD SIGNAL INTEGRITY ANALYSIS AT CERN

Jean-Michel Sainson SI Engineering & Support
CERN - IT Division CE Group Phone:(41) 22 767 75 61
CH - 1211 Genève 23 Fax:(41) 22 767 71 55
SUISSE / SWITZERLAND mailto:J-M.Sainson@cern.ch
Intranet: http://cern.ch/support-specctraquest/

Abstract:
Because of increasing clock frequencies, faster rise times and wider busses, printed circuit board (PCB) design layout becomes an issue.  The Cadence® SPECCTRAQuest™ SI (signal integrity) package allows the pre- and post-layout signal integrity analysis of a PCB designed in  the Cadence flow under Allegro. Case studies of work done for some LHC detectors will be presented. These will show how the tools can   help Engineers in design choice, optimizing electrical performance of board layout, to reduce prototype iterations and to improve production robustness. Examples will include work done on PCI 66MHz and GTL busses.

The ALICE Pixel Detector Readout Chip Test System

Antinori, F. (1,2), Ban, J. (3), BURNS, M. (1), Campbell, M. (1), CHOCHULA, P. (1, 4), Formenti, F. (1), Kluge, A. (1), Meddi, F. (1, 7), Morel, M. (1), Petra,
Roberto, Snoeys, W. (1), Stefanini, G. (1), Wyllie K. (1).
(For the ALICE Collaboration)

ABSTRACT
Described is a system that has been developed for testing the ALICE Silicon Pixel Detector Readout Chip. It is capable of  covering all aspects of testing, from the selection of know good dies on a wafer, characterisation, and as a DAQ when  performing beam tests
Considerable effort has been invested in the software to provide a comprehensive suit of facilities and test routines to enable the complete testing and characterisation of the device.
In this paper we would like to present the objectives and requirements of the test system, a description of the hardware, software and database and present some of the results obtained.

SUMMARY
The previous test system for the pre prototype ALICE1LHC Pixel detector Readout Chip was built using both CAMAC and VME components employing a standard processor that was sited in the VME crate. The system evolved continuously to increase the system functionality and automate the measurement process. This resulted in a bulky test system which was difficult to transport and almost impossible to reproduce. The results of the measurements were stored on the VME system local disk for treatment at a later date by another computer system.

The new system has taken the analogue functionality of the CAMAC modules and integrated them into the circuitry contained on the Adapter Board. The VME crate had been kept and houses the modules required in the DAQ chain. A PC running LabView software has been selected as the system controller. The PC is interfaced to the VME system using the MXI bus connection from National Instruments The Adapter Board is controlled using a 4-wire JTAG connection from an interface which may be installed in either the PC or the VME crate. All test parameters may be varied interactively to enable detailed verification of the various subsections of the Pixel Chip or routines can be executed to automatically perform detailed measurements of the devices. Acquired data is treated and displayed via a graphical user interface exploiting the capabilities of LabView to rapidly present the results. The results may then archived for further reference when either assembling the Pixel Detector or by the ALICE online database.

The system requires approximately xx minutes to characterise a device and yy minutes to test a whole wafer automatically

Anode Front-End Electronics for the Cathode Strip Chambers of the CMS Endcap Muon Detector

N. Bondar*, T. Ferguson**, A. Golyash*, V. Sedov*, N. Terentiev**.

*) Petersburg Nuclear Physics Institute, Gatchina, 188350, Russia
**) Carnegie Mellon University, Pittsburgh, PA, 15213, USA

Abstract

The very front-end electronics system for the anode signals of the CMS Endcap Muon cathode strip chambers has been designed. Each electronics channel consists of an input protection network, amplifier, shaper, constant-fraction discriminator, and a programmable delay with an output pulse width shaper. The essential part of the electronics is an ASIC consisting of a 16-channel amplifier-shaper-discriminator (CMP16). The ASIC was optimized for the large cathode chamber size (up to 3 m x 2.5 m) and for the large input capacitance (up to 300 pf). The ASIC combines low power consumption (30 mW/channel) with excellent time resolution (~2 ns). A second ASIC provides a programmable time delay which allows the alignment of signals with an accuracy of 2.5 ns.

Summary
The very front-end electronics system for the anode signals of the CMS Endcap Muon cathode strips chambers has been designed. The main tasks of the anode side of the detector are to provide a good time resolution and a high efficiency. To meet this requirement, the following measures were implemented:

-each channel was split into two parts: an analog section (amplifier-shaper-discriminator), followed by a digital delay and pulse width shaper.
-the analog part was placed as close to the anode outputs as possible, and the digital part was located on the input of the anode local charged track board (ALCT). -the amplifier input circuits were very carefully arranged and shielded.

Two ASICs were designed. The first is a 16-channel amplifier-shaper-discriminator (CMP16). The ASIC was optimized for the large chamber size (up to 3 m x 2.5 m) and for the large input capacitance (up to 300 pf). The ASIC combines low power consumption (30 mW/channel) with excellent time resolution (~2 ns). The chip is made by AMI, using a BiCMOS 1.5 micron technology. To achieve a low input resistance and relatively low noise, a BJT was used as an amplifier first stage. A two-exponent tail cancellation system, with a semi-Gaussian shaper is also employed in the chip. A two-thresholds constant-fraction discriminator is used to obtain the required time resolution. Output signal levels are LVDS standard.

The second ASIC is a 16-channel LVDS/TTL converter, with a programmable delay and output pulse width shaper. This chip was also made by AMI, using a CMOS 0.5 micron technology. The chip is a logical extension of the CMP16 chip in that it matches the amplifier outputs to the ALCT logic inputs and aligns the signals in phase at the input of the anode logic.

To support the CMP16 chip, a 16-channel anode front-end board (AD16) was also designed. The board was made in the simplest and cheapest way possible. The threshold control network and the board  test facility were delegated to the ALCT board. Each AD16 board is  connected to the ALCT board with a 40-wire cable. This cable supplies the board with power, a threshold voltage setting and test pulses, as well as transmits the output signals to the ALCT. A special setup and accompanying procedures were designed to test and certify the AD16 boards and the two ASICs.

The anode front-end electronics system has met the required specifications, and the mass production has begun.

CMOS front-end for the MDT sub-detector in the ATLAS Muon Spectrometer, development and performance.

C. Posch*, E. Hazen, J. Oliver:

Abstract

Development and performance of the final 8-channel front-end for the MDT segment of the ATLAS Muon Spectrometer is presented. This last iteration of the read-out ASIC contains all the required functionality and meets the envisaged design specifications. In addition to the basic "amplifier-shaper-discriminator"-architecture, MDT-ASD uses a Wilkinson ADC on each channel for precision charge measurements on the leading fraction of the muon signal. The data will be used for discriminator time-walk correction, thus enhancing spatial resolution of the tracker, and for chamber performance monitoring (gas gain, ageing etc.). The feasibility of the MDT system to perform particle identification through dE/dX measurement using the Wilkinson ADC is evaluated. Results of performance and functionality tests in the lab and on-chamber along with an outlook to volume-production and production testing are presented.

Summary

This article reviews the development of the final 8-channel front-end for the MDT segment of the ATLAS Muon Spectrometer and presents results of performance and functionality tests on the last pre-production prototype. The MDT-ASD is an octal CMOS Amplifier/Shaper/Discriminator which has been designed specifically for the ATLAS MDT chambers. Implementation as an ASIC using a high quality analog 0.5um CMOS process has been chosen for this device. The analog signal chain of the MDT-ASD has already been presented for a previous prototype version of the chip and has not been changed significantly since then. It will therefore be addressed only briefly in this article. New developments include the implementation of a Wilkinson type charge-to-time converter and on-chip programmability of certain functional and analog parameters along with a serial control data interface. Bipolar shaping was chosen to prevent baseline shift at the anticipated level of background hits. The shaper output is fed into a discriminator for the timing measurement and the Wilkinson ADC section for performing the leading edge charge measurement. The information contained in the Wilkinson output pulse, namely the leading edge timing and the pulse width encoded signal charge, will be read and converted to digital data by a TDC. The Wilkinson cell operates under the control of a Gate Generator which consists of all differential logic cells. It is thus highly immune to substrate coupling and can operate in real time without disturbing the analog signals. The final output is then sent to the LVDS cell and converted to external low level differential signals. The main purpose of the Wilkinson ADC is to provide data which can be used for the correction of time-slew effects due to pulse amplitude variations. Time slewing correction improves the spatial resolution of the tracking detector. In addition, this type of charge measurement provides a useful tool for chamber performance diagnostics and monitoring (gas gain, ageing etc.). Further applications such as dE/dx measurements of slow moving heavy particles like heavy muon SUSY partners etc are conceivable. Test results on the conversion characteristics as well as measurements of noise performance respectively non-systematic charge measurement errors of the Wilkinson ADC are shown. The feasibility of the MDT system to perform particle identification through dE/dX measurement using the Wilkinson ADC is evaluated and results of a simulation study on energy separation probability is presented. It was found advantageous to be able to control or tune certain analog and functional parameters of the MDT-ASD, both at power-up/reset and during run time. A serial I/O data interface using a JTAG type protocol plus a number of associated DACs were implemented in the chip. In order to facilitate prototype testing during the design phase as well as to perform system calibration and test runs with the final assembly, a calibration/test pulse injection system was integrated in the chip. It consists of a bank of 8 parallel switched capacitors per channel and an associated channel mask register. The mask register allows for each channel to be selected separately whether or not it will receive test pulses. The capacitors are charged with external standard LVDS voltage pulses, yielding an input signal charge range similar to the expected range of the tube signals. This pulse injection system allows for automated timing and charge conversion calibration of the system. Hence, in principle all systematic errors of the readout electronics can be calibrated out for each individual channel. As a final point, an outlook to volume-production and production testing of the chip is given.

The authors also expect to present evaluations of the circuit which was submitted to foundry at the end of March.

DeltaStream : A 36 channel low noise, large dynamic range silicon detector readout ASIC optimised for large detector capacitance.

P.Aspell, D.Barney, P.Bloch, A.Go, C.Palomares

Abstract

DeltaStream is a 36 channel preamplifier and shaper ASIC that provides low noise, charge to voltage readout for capacitive sensors over a large dynamic range. The chip has been designed in the DMILL BiCMOS radiation hard technology for the CMS Preshower project. Two gain settings are possible. High gain (HG), has gain 30mV/MIP (7.5mV/fC) for a dynamic range of 0.1 to 50 MIPS (0.4fC – 200fC) and low gain (LG), has gain 4mV/MIP (1mV/fC) for a dynamic range of 1 to 400 MIPS (4fC – 1600fC). The peaking time is ~25ns and the noise has been measured at ~ENC = 680e + 28e/pF. Each channel contains a track & hold circuit to sample the peak voltage followed by an analog multiplexer operating up to 20MHz. The response of the signal is linear throughout the system. The design and measured results for input capacitance < 55pF are presented.

Summary

DeltaStream has an architecture that follows in the Amplex family of silicon sensor readout ASICs. It contains 36 channels, each of which contains a low noise preamplifier, shaper and a track & hold circuit to sample the peak voltage. An analog multiplexer then serializes the analog values into a single analog data stream.

DeltaStream has been developed to provide a readout ASIC suitable for the production testing of the CMS Preshower silicon sensors. It also serves as a multi-channel prototype chip for the preamplifier and shaper (Delta) and a 20MHz analog multiplexer intended for use within the Preshower front-end electronics analog memory ASIC called PACE.

DeltaStream is designed to be dc coupled to silicon sensor strips and is insensitive to dc leakage currents < 50mA per strip. Charge to voltage readout over a large dynamic range (< 400 MIPs) for total input capacitance up to 55pF with 25ns peaking times are the main design goals. Two gain settings are possible. High gain (HG), has gain ~30mV/MIP (7.5mV/fC) for a dynamic range of 0.1 to 50 MIPS (0.4fC – 200fC) and low gain (LG), has gain ~4mV/MIP (1mV/fC) for a dynamic range of 1 to 400 MIPS (4fC – 1600fC).

Measurements of gain, rise time and noise have been made in both HG and LG for two different levels of total input capacitance (13pF, 52 pF). The mean gain is as follows : HG (13 pF) = 33.1 mV/MIP, HG (52 pF) = 24.6mV/MIP, LG (13 pF) = 4.6 mV/MIP, LG (52 pF) = 3.4 mV/MIP. The rise time measured from 10-90% of the peak voltage is HG (13pF) = 18.9ns, HG (52pF) = 21.8ns, LG (13pF) = 14.5ns, LG (52pF) = 17.5ns, The standard deviation across all channels is ~3% for gain and ~1% for the rise time.

Noise has been measured for all the channels in high gain resulting in a mean value of ENC = 680e + 28e/pF.

The multiplexer operates at frequencies up to 20MHz with a linear response. It can also be used to individually select a channel allowing the full pulse shape to be readout.

1.Corresponding author
Name: Franco Gonella
Institution: Istituto Nazionale di Fisica Nucleare - Sez. Padova (Italy)
Email address: fgonella@pd.infn.it
Postal address: Via Marzolo, 8 - 35131 Padova (Italy)

2.Paper category
LHC Experiment: CMS
LHC Experiment Subsystem: MU
LEB2001 Workshop topic: Electronics for muon detectors

3.Paper information
Title:
"The MAD", a Full Custom ASIC for the CMS Barrel Muon Chambers Front End Electronics

Authors list with Institutions: Franco Gonella and Matteo Pegoraro from INFN - Sez. Padova (Italy)

Summary:

The analog frontend electronics for the muon chambers of CMS barrel has been integrated in a full custom ASIC, named "The MAD", developed by INFN Padova using 0.8 µm BiCMOS technology from Austria Mikro Systeme. Each chip provides the signal processing for 4 drift tubes in a 2.5x2.5mm2 die housed in a TQFP44 package. The 4 identical analog chains contained in the ASIC are made of a charge preamplifier followed by a simple shaper with baseline restorer, whose output is compared against an external threshold by a latched discriminator; the output pulses are then stretched by a programmable one shot and sent to an output stage able to drive long twisted pair cables with LVDS compatible levels. The working conditions of the detector set requirements for high sensitivity and speed combined with low noise and little power consumption. Moreover, as the basic requirement for the frontend is the ability to work at very low threshold to improve efficiency and time resolution, a good uniformity between channels of different chips is needed for sensitivity and threshold. Gain value is 3.3 mV/fC in average, constant up to 500 fC input with less than 1% integral nonlinearity; saturation occurs at about 800 fC. Threshold uniformity is very good, the r.m.s. is below 0.6 mV and the propagation delay is about 4 ns for signals above 30fC. Key characteristics for low threshold operation are noise and crosstalk: bare chips exhibit ENC ??1400 e- (slope of 60 e-/pF) and a value below 0.1% for the latter. Once mounted on the PCB these two figures increase to 1900 e- and 0.2% mainly because of the input protection network necessary to prevent HV discharge events. The power dissipation of the chip is very low, about 25 mW/channel so reducing the need for heat removal. Control and monitoring features have been included in the chip: to mask noisy wires each channel can be disabled at the shaper input resulting in little crosstalk to neighbors. It's also possible to check trigger functionality using a fast disable/enable feature, controlled via LVDS levels, acting on the output driver of left and right channel pairs. An absolute temperature probe with a sensitivity of 7.5 mV/(K has been integrated in order to detect electronics failures and monitor environmental changes. Two separate power supplies (5V and 2.5V) are used in order to reduce power drain and minimize interference between input and output sections. The routing has been particularly cured for power, digital ground and analog ground and many pins have been reserved for this purpose. Reliability is a critical point in a hardly accessible environment as CMS detector: tests performed (accelerated ageing and irradiation with neutrons, heavy ions and gamma rays) show good MTBF characteristics, low SEU rate and immunity to latch-up events in spite of using a standard and not too expensive technology.


Abstract:

To meet frontend electronics needs of CMS barrel muon chambers a full custom ASIC, named "The MAD", has been first developed by INFN of Padova and then produced in over 50.000 pieces to equip the 180.000 drift tubes. The chip provides 4 identical chains of amplification, discrimination and cable driving circuitry; also it integrates a flexible channel enabling/disabling capability and a temperature probe for monitoring purposes. The ASIC has been deeply tested resulting in good performances; particularly, big effort was put in radiation (neutron, gamma rays and ions) and ageing tests to check behavior and reliability in LHC environment.

IONIZATION RADIATION TOLERANCE OF THE ATLAS TRACKER ELECTRONICS

M. Ullan*, D. Dorfan*, T. Dubbs*, A. A. Grillo*, E. Spencer*, A. Seiden*, H. Spieler**, M. Gilchriese**, M. Lozano***

* Santa Cruz Institute for Particle Physics (SCIPP)
University of California at Santa Cruz
Santa Cruz, CA 95064
USA
Phone: 1 831 459 3567
Fax: 1 831 459 5777
E-mail: ullan@scipp.ucsc.edu

** Lawrence Berkeley National Laboratory (LBNL)
University of California at Berkeley
Berkeley, California, USA

*** Centro Nacional de Microelectrónica (CNM-CSIC)
Barcelona, Spain


Abstract

Ionization damage has been investigated in the IC designed for the readout of the detectors in the Semiconductor Tracker (SCT) of the ATLAS experiment  at the LHC, the ABCD chip. The technology used in the fabrication has been found to be free from Low Dose Rate Effects which facilitates the studies of the radiation hardness of the chips. Other experiments have been done on the individual transistors in order to study the effects of temperature and the annealing, and to get a better understanding and a quantitative information about these mechanisms. With all this information, the suitable irradiation experiments have been designed for the chips to obtain a better answer about the survivability of these chips in the real conditions.

Summary

The ABCD chip is the IC that has been designed for the readout of the silicon detectors of the ATLAS Semiconductor Tracker (SCT) at the LHC. It is fabricated on the DMILL technology, which is a BiCMOS process on an SOI substrate. This chip will have to be placed very close to the detectors and, therefore, inside the active area of the SCT. That means that it will have to endure the same level of radiation that the detectors themselves.

Different experiments have been carried out to study the radiation hardness of this technology and the ABCD chip itself to that high level of radiation. The physical mechanisms that intervene in the damage produced on the analog part of these chips from ionization or non-ionization radiation are different and it is better to study them separately to have a good understanding of the problem. This study is presented here where the effects of ionization radiation have been analyzed for the DMILL technology and the ABCD chip, taking into account the total dose effects.

A first study has been to check if the bipolar transistors of the DMILL technology suffer from Low Dose Rate Effects (LDRE) which would largely complicate the rest of radiation hardness studies. Different radiation experiments have been carried out up to a high enough total dose and at a very wide range of dose rates using individual transistors of the technology. The result has demonstrated that the DMILL technology does not suffer from total dose effects which facilitates the realization of other radiation hardness studies. This result has been confirmed by other irradiations up to the total dose of interest. Together with this study, the annealing of the damage produced on the transistors has been investigated in order to separate this effect from the LDRE.

Other experiments have been carried out at different temperatures in order to obtain the sensitivity of the radiation damage of these chips to temperature. The tests structures have been irradiated up to the total dose of interest and at a wide range of temperatures from 10 to 110 ºC. The results demonstrate the presence of two opposite effects. One is the increase in the damage at higher temperatures, and the other is the increase in the annealing of that damage also for higher temperatures. This two effects result in a worst case temperature at which the transistors suffer the largest damage, being the damage smaller at higher or lower temperatures.

Finally the ABCD chip has been irradiated up to the total dose and at a high dose rate in order to obtain the total ionization damage that will be produced to the chip in the real experiment. Given that it has been demonstrated that there are not LDRE on this technology this experiment can be done at a high dose rate and in a short period of time. The results demonstrate that the ABCD chip remain within specifications after the expected ionization damage has been produced.

Results of Radiation Tests on the Anode Front-end Electronics for the CMS Endcap Muon Cathode Strip Chambers

T.Ferguson, N.Terentiev
(Carnegie Mellon University, Pittsburgh, PA, 15213, USA)

N.Bondar, A.Golyash, V.Sedov
(Petersburg Nuclear Physics Institute, Gatchina, 188350, Russia)

Abstract

We report the results of several radiation tests on pre-production samples of the anode front-end electronics boards for the CMS endcap muon system. The crucial component tested was the 16-channel preamplifier ASIC (BiCMOS). The boards were exposed to doses up to 80 krad in a 63 MeV proton beam, and to a neutron fluence up to 2*10**12 n/cm**2 from a nuclear reactor. The static (current and voltage) and dynamic (noise,threshold, gain and timing) characteristics were measured versus the radiation dose.

2. Summary

The peak luminosity of LHC, 10**34 cm**-2*sec**-1, combined  with the 7 TeV beam energy, will create a very hostile radiation environment in the detector experimental halls. Radiation tolerance and reliability are important issues for the CMS electronics, including the endcap muon CSC front-end electronics. The most severe conditions in the muon endcap region are in the vicinity of the ME1/1 CSC chambers. Here, the neutron fluence and the total ionizing dose (TID) accumulated during 10 years of LHC operation are expected to be about 6-7*10**11n/cm**2 (at En>100 keV) and 1.8-2 krad, respectively (Ref.1). The goal of our measurements was to test the performance of the anode front-end boards, with specially designed preamplifier chips (AMI 1.5 micron BiCMOS technology) on them, up to a level of 3 times these doses, and to observe the presence of single-event effects such as latch-up, at higher doses (Ref.2).
The boards were irradiated in a 63 MeV proton beam and received a TID up to 14 and 80 krad. No latch-ups or spikes or any changes in the static parameters (amplifier, discriminator and regulator voltages) were observed. However, the dynamic parameters such as threshold, gain and slewing time were sensitive to the radiation, showing a maximum deviation of 40% (for slewing time) at a TID of 60 krad. The noise and the resolution time were not affected at all. At the required 3 times level of TID (5-6 krad), all changes were practically negligible. The corresponding graphs will be presented. Some boards were exposed to a reactor neutron fluence up to 2*10**12 n/cm**2, at a neutron energy of 100 keV < En < 10 MeV.  They also received a TID of about 50-60 krad from gammas which accompanied the reactor neutrons. About 50% of the boards survived, showing moderate changes (20-30%) in dynamic characteristics in a test taken one month after the irradiation. The rest of the boards recovered after one week of heating at 110 degrees C. Further heating returned all the parameters for all boards to the norm. From our results we can roughly estimate that, for the test doses given above, the annealing time is about a few months at room temperatures. Since the LHC rate of real radiation exposure is much slower than this, we conclude that the anode front end boards should not show any radiation damage during normal LHC operation.

We are thankful to M. Tripathi and B. Holbrook of the University of California, Davis, and to T.Y. Ling and B. Bylsma of the Ohio State University for their valuable help.

References:

1. "A global radiation test plan for CMS electronics in HCAL,Muons and Experimental Hall". http://cmsdoc.cern.ch/~faccio/
2. T.Y.Ling. "Radiation tests for EMU electronics". http://www.physics.ohio-state.edu/~ling/elec/rad_emu_proc.pdf

Use of antifuse-FPGAs in the Track-Sorter-Master of the CMS Drift Tube Chambers

G.M.Dallavalle, A.Montanari, F.Odorici, G.Torromeo, R.Travaglini, M.Zuffa
INFN and University, Bologna, Italy

Abstract
The Track-Sorter-Master (TSM) is an element of the on-chamber trigger electronics of a Muon Barrel Drift Tube Chamber in the CMS detector. The TSM  provides the chamber trigger output and access to the trigger electronic devices for monitoring and configuration. The specific robustness requirements on the TSM are met with a partitioned architecture based on antifuse-FPGAs. These have been successfully tested with a 60 MeV proton beam: SEE and TID measurements are reported.

Summary
Drift Tubes Chambers (DTCs) are used to detect muons in the barrel of the Compact Muon Solenoid (CMS), which will collect data at the future Large Hadron Collider (LHC) of CERN. In LHC, two proton beams of 7 TeV will collide at a bunch crossing frequency of 40 MHz. Electronic devices installed on the DTCs analyse every bunch crossing, with no deadtime, and search for possible muon track segments. In  particular, the Trigger Server system (TS) examines the search results from smaller sections of a DTC, rejects fakes and duplicates, and selects the best two segments overall, thus reducing the chamber output by a factor of 25.

Because of the limited accessibility of front-end electronics and the high neutron flux expected in the CMS cavern, priority in the TS design is given to partitioning and to remote control and testability. The TS architecture is a compromise between optimal partitioning, for minimising the impact of failures, and minimal trigger latency, in order to limit event data buffering. In the TS, muon track segment selection is performed in two steps: Track Sorter Slave (TSS) units (each serving 1/7 of a DTC) in the first layer feed Track Sorter Master (TSM) units (one each DTC) in the second layer. For the TSS, we designed a 0.5 micron CMOS ASIC implementing an ad-hoc fast sorting algorithm. Overall, in the CMS muon barrel about 1300 TSS ASICs will perform as a single synchronous system. The TSM does the final selection and provides access to the TSSs for monitoring and configuring.

The TSM is partitioned in several distinct blocks with partial redundant functionality, and automatic failure detection and re-configuring. For manufacturing the TSM blocks, antifuse-FPGAs, which have permanent configuration once programmed, are chosen, after their radiation tolerance has been successfully tested for use in LHC. Single Event Effect and Total Irradiation Dose measurements for the Actel A54SX antifuse-FPGAs were performed using a 60 MeV proton beam. The chips show good tolerance to high radiation doses of 10 to 70 Krads. For Single-Event-Upsets, we set an upper-limit cross-section of 2.9/10^12 cm2 (90% c.l.) per chip.

Evolution, Revolution, and Convolution
Recent Progress in Field-Programmable Logic


by Peter Alfke
Xilinx, Inc.

Evolution:
Bigger, faster, cheaper chips, better software.

Revolution:
Versatile I/O for 5 V, 3.3 V, 2.5 V and 1.8 V interfaces
Controlled-impedance I/O drives transmission lines, simplifies pc-boards
Versatile clock management eliminates delay, adjusts phase
Dedicated fast multipliers (>100 per chip)
PowerPC cores, up to 4 per chip
3.125 Bbps ( 2.5 Gbps data ) serial interface, clock recovery, 8B/10B, 20-bit FIFOs ( 10 Mbps in the future )

Convolution:
Using BlockRAM as state machines
Using multipliers as logic or arithmetic shifters
Using input flip-flops to count at 1 GHz
Using FPGAs with asynchronous clocks
Using triple redundancy to correct single-event upsets

The front-end prototypes for the electronic readout of the ALICE experiment Silicon Drift Detector have been designed and succesfully tested. Nevertheless, a number of system requirements as minimize dead time, avoid external biasing and develop the Detector Control System have to be addressed. At this purpose, new building blocks have been developed. These blocks include a 10 bit A/D converter, an 8 bit D/A converter based on the current mirror scheme, a voltage regulator and biasing schemes. The A/D converter is based on the successive approximation principle. In order to reduce the input capacitance, the internal DAC has been splitted into a 5 bit main DAC and a 5 bit sub DAC. This arrangement makes possible to reduce the input capacitance of a factor of 8 compared to the previous version. The D/A converter is based on a matrix of 256 current mirrors. This technique relaxes the matching requirements and therefore improves DNL and INL. A transimpedance amplifier has been designed in order to convert the output current into a voltage. The voltage regulator and bias circuits will be integrated in the final front-end ASIC ( named PASCAL ) in order to have no external analog signals in the front-end board. Those components will be also the building blocks for the Detector Control System ASIC which will be located on both ends of the SDD ladder. The circuits have been developed in a commercial CMOS 0.25 um technology using radiation tolerant layout techniques.

Influence of Temperature on Pulsed Focused Laser Beam Testing

P.K.Skorobogatov, A.Y.Nikiforov

Specialized Electronic Systems, Kashirskoe shosse, 31, 115409, Moscow,

Russia pkskor@spels.ru

Abstract

Temperature dependence of p-n junction radiation-induced charge collection under 1.06 and 0.53 micrometer focused laser beams was investigated in the temperature range from 22 to 110 C using experiments and numerical simulation. It was shown that in the case of 0.53 micrometer laser irradiation the temperature practically does not affect the collected charge. In the case of 1.06 micrometer laser irradiation the theory and experiments have shown the essential growth (from 2 to 3 times) of collected charge with temperature. The result obtained must be taken into account in device SEE selection for LHC electronic.

Summary

The high radiation environment of the LHC experiments requires the electronics to withstand single event effects (SEE). The procedure for estimating of integrated circuits SEE vulnerability based on particle accelerators testing is very expensive.

The focused laser sources may be used for SEE investigation and estimation [1,2]. Laser simulation of SEE is based on the focused laser beam capability to induce local ionization of IC structures. A wide range of particle linear energy transfer (LET) and penetration depths may be simulated varying the laser beam spot diameter and wavelength. The temperature dependence of the laser absorption coefficient in semiconductor affects the equivalent LET and must be accounted for when devices are tested at temperature range [3].

In order to estimate the influence of temperature on SEE laser testing parameters we have analyzed the temperature dependence of charge collected by test structure p-n junction. The experiments were performed using the original "PICO-2E" pulsed solid-state laser simulator in basic (1.06 micrometer) and frequency-double (0.53 micrometer) modes with laser spot diameter of 5 micrometers. The numerical simulations were performed using the original "DIODE-2D" 2D software simulator.

The investigated test structure was manufactured in a conventional 2 micrometer bulk CMOS process and includes well-substrate p-n junction. The measurements of p-n junction collected charge were performed in the temperature range from 22 to 110 ?C for two laser beam spot positions: within the n-well and out of junction area. It was shown that in the case of 0.53 micrometer laser irradiation the temperature practically does not affect the collected charge because of slight laser absorption coefficient temperature dependence in this range. The theoretically predicted variations of collected charge do not exceed 10% and may be explained by carrier lifetime and mobility temperature dependences. In the case of 1.06 micrometer laser irradiation the theory and experiment have shown the essential growth of collected charge with temperature. It is corresponds with strong laser absorption coefficient temperature dependence for photon energy near the bandgap. The theoretical prediction gives the approximately doubling of collected charge in the range from 22 to 110 C. The experimental results show that SEE sensitivity increases at least three times in this temperature range. The difference between measured and simulated results may be explained by uncertainties of laser absorption coefficient temperature dependence near the edge of silicon fundamental band-to-band absorption zone.

The results obtained prove that the temperature dependence of the laser absorption coefficient in semiconductor affects the equivalent LET and must be taken into account in device SEE selection for LHC electronic.

References

[1] C.F.Gosset, B.W. Hughlock, A.H.Johnston, "Laser simulation of single particle effects", IEEE Trans. Nucl. Sci., vol. 37, no.6, pp.1825-1831, Dec. 1990.

[2] J.S. Melinger, S. Buchner, D. McMorrow, W.J. Stapor, T.R Wetherford, A.B. Campbell and H. Eisen, "Critical evaluation of the pulsed laser method for single-event effects testing and fundamental studies", IEEE Trans. Nucl. Sci., vol. 41, no.6, pp. 2574-2584, Dec.1994.

[3] A.H. Johnston, "Charge generation and collection in p-n junctions excited with pulsed infrared lasers", IEEE Trans. Nucl.Sci., vol. 40, no. 6, pp. 1694 - 1702, Dec. 1993.

The Behavior of P-I-N Diode under High Intense Laser Irradiation

P.K.Skorobogatov, A.S.Artamonov, B.A.Ahabaev

Specialized Electronic Systems, Kashirskoe shosse, 31, 115409, Moscow,

Abstract

The dependence of p-i-n diode ionizing current amplitude vs 1.06 micrometer pulsed laser irradiation intensity is investigated. It is shown that analyzed dependence becomes nonlinear beginning with relatively low laser intensities near 10 W/cm2. This effect is connected with the modulation of pi-n diode intrinsic region by laser irradiation. As a result the distribution of electric field becomes non-uniform that leads to decrease of excess carriers collection. The ionizing current pulse form becomes more prolonged and does not repeat the laser pulse waveform. It is necessary to take into account when p-i-n diode is used as a laser intensity dosimeter.

Summary

Pulsed laser sources are widely used for dose rate effects simulation in IC's. The Nd:YAG laser with 1.06 micrometer wavelength is near ideal for silicon devices, with a penetration depth near 700 micrometers. The measurements of pulsed laser irradiation intensity and waveform monitoring may be provided with p-i-n diode. High electric field in its intrinsic region provides the full and fast excess carriers collection. As a result the ionizing current pulse waveform repeats the laser pulse within the accuracy of several nanoseconds.

Possible nonlinear ionization effects may disturb the behavior of p-i-n diode at high laser intensities. To investigate the p-i-n diode possibilities at high laser intensities the original software simulator "DIODE-2D" and the pulsed laser simulator with 1.06 micrometer wavelength were used. The typical p-i-n diode with 380 micrometers intrinsic region width under 300 V reverse bias was investigated. The simulation of p-i-n diode structure have shown that linear dependence between laser intensity and ionizing current is valid only at relatively low intensities up to 10 W/cm2 under 11 ns laser pulse irradiation. The ionization distribution nonuniformity connected with laser radiation attenuation does not affect the dependence because of relatively low excess carrier density to sufficiently change the absorption coefficient. In the field of high laser intensities this dependence becomes non-linear and ionizing current increases more slowly than laser intensity. The numerical results were confirmed by experimental measurement of pi-n diode ionizing reaction in a wide range of laser intensities. The pulsed laser simulator "RADON-5E" with 1.06 micrometer wavelength and 11 ns pulse width was used in the experiments as a radiation source [1]. The laser pulse maximum intensity was varied from 0.3 up to 2ú103 W/cm2 with laser spot size covering the entire chip. It provides in silicon the equivalent dose rates up to 109 rad(Si)/s

As in the case of gamma irradiation [2], the reason of non-linearity is connected with the modulation of p-i-n diode intrinsic region by excess carriers. Because of low level of initial carriers concentration the modulation takes place at relatively low laser intensities. As a result of modulation the distribution of electric field in the intrinsic region becomes non-uniform that leads to decrease of excess carriers collection. The behavior of p-i-n diode becomes similar to that of ordinary p-n junction with prompt and delayed components of ionizing current. The prompt component repeats the dose rate waveform. The delayed component is connected with the excess carriers collection from regions with low electric fields. As a result the ionizing current pulse form becomes more prolonged and dose not repeat the laser pulse waveform.

The non-linear character of behavior and prolonged reaction must be taken into account when p-i-n diode is used as a laser intensity dosimeter in LHC experiment.

References

[1]. "RADON-5E" Portable Pulsed Laser Simulator: Description, Qualification Technique and Results, Dosimetry Procedure/A.Y. Nikiforov, O.B. Mavritsky, P.K. Skorobogatov et all//1996 IEEE Radiation Effects Data Workshop. P. 49-54.

[2]. P.K.Skorobogatov, A.S.Artamonov, B.A.Ahabaev The Nonlinear Behavior of P-I-N Diode in High Intense Radiation Fields// Proceedings of the Sixth Workshop on Electronics for LHC Experiments. Krakow, September 22-26, 2000. P. 499 - 501.

Neutron radiation tolerance tests of optical and opto-electronic components for the CMS Muon Barrel Alignment

L. Baksay, P. Raics, Zs. Szabó, L. Molnár, G. Pszota
Institute of Experimental Physics, Debrecen University, Debrecen, Hungary

A. Fenyvesi, J. Molnár,
Institute of Nuclear Research (ATOMKI), Debrecen, Hungary

Gy. L. Bencze
Institute of Particle and Nuclear Physics, Budapest, Hungary
CERN, Geneva, Switzerland

L. Brunel
CERN, Geneva, Switzerland
Institute of Experimental Physics, Debrecen University, Debrecen, Hungary

Abstract

Components (LED light sources, LED driver and controller electronics, lens and video-sensor) of the barrel muon position monitoring system of the LHC CMS experiment have been irradiated with p(17.5 MeV)+Be neutrons. The tests were performed at the MGC-20E cyclotron of ATOMKI (Debrecen, Hungary). The neutron fluences delivered to the components were 2.6E+12 n/cm2 and 8.0E+13 n/cm2 (the expected values for the Barrel Muon and ME1/1 chambers, respectively). Changes of the electrical and optical characteristics were investigated.

This work was supported by the Hungarian National Research Fund (OTKA). Contract Nos.: T026184 and T026178.

Summary

Performance of the muon detecting system of the CMS detector of the Large Hadron Collider (LHC) is affected by the position and orientation of the individual chambers. In the case of the barrel muon detectors, their alignment will be controlled on the basis of the information that is provided by the position monitoring system. This system will consist of LED light sources, LED driver and controller electronics, optical lenses and video-sensors. They will have to work in a radiation environment, where the highest expected flux of the neutron component is about 1.0E+03 n/cm2/sec, and the estimated time of operation is 5.0E+10 sec. The total expected neutron flux is 2.6E+12 n/cm2 and 8.0E+13 n/cm2 for the Barrel Muon and ME1/1 chambers, respectively. Radiation damage induced by neutrons can alter electrical and optical characteristics of the components and thus the accuracy of the whole barrel muon position monitoring system.

Neutron radiation hardness tests of the components to be used in the Barrel Muon Alignment System were carried out using the broad-spectrum p(17.5 MeV)+Be neutron source ( 0 < En < 18 MeV, < En> = 3.7 MeV) of ATOMKI (Debrecen, Hungary).

Low current high intensity point-like LED light sources emitting at 660 nm (Type: FH1011, Stanley Electric Co. Ltd.) were irradiated up to 2.6E+12 n/cm2. Three modes of operation were studied: a) voltage on permanently, b) voltage off permanently and c) voltage on for 1 sec and off for 19 sec. For all of these modes of operation, the light yield decreased almost linearly as a function of the neutron fluency and approximately 50 % decrease was observed at the end of the irradiations. No other change in the electrical and spectral characteristics was measurable.

LED current driver and controller electronics with Microchip PIC16F84 processors were irradiated up to 8.0E+13 n/cm2. Some 20 % loss of the output currents of the LED controllers was observed at the end of the irradiation. The degradation of the current drivers was negligible below 1.0E+11 n/cm2 (the expected fluency at the position of operation of the device). Two processors were studied. Both damaged only after delivering ~ 2.0E+13 n/cm2 neutron fluency to them as the dramatically increased current consumption of the electronics indicated.

Plano-convex single lenses were irradiated up to 8.0E+13 n/cm2. They were made of BK7 glass without coating and their diameter was 10 mm. No measurable change of the spectral transmission and the refraction (focal length) was observed.

VM5402 video cameras with VV5402 CMOS sensor device (VLSI Vision Ltd.) were irradiated up to 2.8E+12 n/cm2. The radiation damage of the sensor resulted in the altered nearly Gaussian distribution of the light sensitivity of the individual pixels in all modes of operation. The mean values decreased while the sigma values increased in all three modes ( a) voltage on permanently, b) voltage off permanently and c) voltage on for 1 sec and off for 19 sec). Apart from the general sensitivity loss, the spectral sensitivity of the sensor did not change.

A PROTOTYPE FAST MULIPLICITY DISCRIMINATOR FOR ALICE L0 TRIGGER

Leonid Efimov, Vito Lenti and Orlando Villalobos-Baillie

Abstract

The design details and test results of a prototype Mutiplicity Discriminator (MD) for the ALICE L0 Trigger electronics are presented. The MD design is aimed at the earliest trigger decision founded on a fast multiplicity signal cut, in both options for the ALICE centrality detector: Micro Channel Plates or Cherenkov counters. The MD accepts detector signals with an amplitude range of plus-minus 2.5 V, base duration of 1.8 ns and rise time of 300-400 ps. The digitally controlled threshold settings give an accuracy better than 0.4% at the maximum amplitude of the accepted pulses. The MD internal latency of 15 ns allows for a decision every LHC bunch crossing period, even for the 40 MHz of p-p collisions.

Summary

A functional scheme and other considerations for the Prototype Multiplicity Discriminator (MD), as an element of ALICE L0 Trigger Front-End Electronics (FEE), are given for the proposed MCP-based detector option. The MD has to produce a Pre-Trigger on Multiplicity by cut of a fast linear sum of 8 signals from pads belonging to an MCP disc sector. This is foreseen within every FEE card according to programmable threshold codes delivered by a Source Interface Unit through the ALICE Detector Data Link. The prototype MD schematics and implementation are described in details around a functional scheme and a schematic view of the input analog section. The approach used in the design was to implement a leading edge discriminator by a proper combination of an ultra-fast voltage comparators and a digital-to-analog converter (DAC) from Analog Devices. The shaper, built on components of Motorola MECL 10KH logic series, provides the output signal with a correct form, duration and 16 mA for 50 Ohm load. The prototype MD board is mounted in a double-width NIM module to support conventional test facilities. The correlation between MD preset and real (effective) thresholds has been studied in order to evaluate the MD sensitivity to very fast and low-amplitude detector signals. Some results of such measurements, using a fast programmable pulse generator, are shown as the effective voltage threshold versus the DAC threshold values. Next calculation of the equivalent electric charge, carried by these pulses, gave the rough estimates of the MD sensitivity as a minimum of over DAC threshold pulse charge needed to trigger the scheme. An estimate of a Prototype MD input capacity was obtained also. The first experimental test of the prototype MD was performed at CERN PS/T10 area with muon beams of 7.5 GeV/c.
The aim of this experiment was two fold:
a) to test the timing properties of the prototype MD;
b) to simulate a study of multiplicity/centrality versus the MD threshold.
Results from the MD, used instead of a specialized fast timing discriminator for time-of-flight measurements, are presented with a distribution of events versus the time-to-digital converter channels. A resolution of about 120 ps should be taken as a good one because the MD is not optimized for timing applications.
In conclusions the main achievement is defined as a prototype amplitude discriminator, for the ALICE L0 multiplicity Trigger, has been designed, elaborated and tested to stand short nanosecond signals coming from the ALICE T0/Centrality detector on Micro Channel Plates base. Commercially available, inexpensive and fast components have been used to implement the prototype MD. It features an input signal range from 0 to plus-minus 2.5 V, a programmable threshold control with 8 bit resolution, and an output signal latency of 15 ns. The minimum input signal charge, needed to trigger the scheme over the DAC threshold, has been found in about 0.26 pC. While applying the MD for timing in MIPs time-of-flight measurements, a resolution of about 120 ps has been obtained. The MD was also tested by studying the response to real MCP signals as a function of the MD threshold.

The IC modularity is 3-channels per chip. Each individual channel converts a differential input voltage into a single-ended output current superimposed to a pre-settable DC current (0-60mA). The latter allows to bias the laser diode above threshold and to track the amount of threshold-drift expected during LHC operation. Input signals are transmitted to the laser driver using 100W cable up to 30 cm long. The driver is optimised for analogue operation (good linearity, low noise), but the input voltage levels are also compatible with the digital LVDS standard (±400mV, on 100W). The channels can be individually addressed via a serial I2C interface, allowing individual power down, gain control, and pre-bias control. Robustness to Single Event Upsets is achieved by tripling the digital logic and by using a majority voting decision scheme. About 20.000 such devices will be packaged in a 5x5 mm LPCC case for ease of testing and installation in the Tracker readout and control hybrids.

The ASIC qualification will be completed before the conference, except for SEU testing which is foreseen for Autumn 2001. A prototype version of the device (using the same analogue blocks and redundant functionality) has been included in the CMS Tracker System Test currently under preparation. The final device performance and functionality will be presented at the conference. The production test program and equipment is being optimized for fast execution (pass/fail) with highest possible fault coverage.

Irradiation Tests and Tracking Capabilities of the Alice1LHCb Pixel Chip

J.J. van Hunen (For the ALICE collaboration)

The Alice1LHCb front-end chip has been designed in a 0.25um CMOS commercial technology, with special design rules to obtain radiation tolerance, for the ALICE pixel and the LHCb RICH detectors. The chip has been irradiated with low energy protons and heavy ions, to determine the cross-section for Single Event Upsets, and with X-rays to evaluate the sensitivity to the Total Ionizing Dose. We report the results of those measurements. We also report preliminary results of measurements done with minimum ionising particles in a test beam at the CERN SPS.

Activation studies for an ATLAS SCT module.

C.Buttar, I.Dawson, A.Moraes (University of Sheffield, UK)

One of the consequences of the harsh radiation environments at LHC experiments will be induced-activation of detector systems. This has implications for operation and maintenance scenarios. We have simulated the radiation environment of the ATLAS SCT system and made first estimates on the levels of induced activation of an SCT module. This has included studying both neutron-induced and spallation-induced activation. Dose rates are also obtained and
compared to other parts of the ATLAS detector where estimates have also been made.
(FOR POSTER PRESENTATION)

Design and performance of a circuit for the analogue optical transmission in the CMS inner tracker

G. M. Bilei, M. T. Brunetti (corresponding author), F. Ceccotti, B.Checcucci,  V. Postolache, A. Santocchia

A new circuit for the conversion of analogue electrical signals into the corresponding optical ones has been built and tested by the CMS group of Perugia. This opto-hybrid circuit will be used in the read out electronics of the inner barrel part of the CMS tracker. The opto-hybrid is a vetronite circuit equipped with one programmable laser driver chip and up to 3 laser diodes, all being radiation tolerant. The description of the circuit and its performances are reported and discussed.

Summary: The opto-hybrid circuit is employed in the analogue optical link of the CMS inner barrel and converts the analogue electrical signal coming from silicon detectors and sampled by the APV chips into the analogue optical signal to be transmitted via optical fibres. The opto-hybrid is an FR4 (vetronite) circuit with dimensions of 30 x 22 mm2. The active devices are a programmable laser driver chip and up to 3 laser diodes (output channels). The laser driver through an I2C interface biases each laser diode in its linear response region. Analogue input signals up to +/- 300 mV from the MUX connected to the APV chips modulate the bias currents. The optical fibres escaping from each laser diode carry the analogue signal, which will be converted again, out of the beam area, into an electrical signal and is finally digitised for acquisition and analysis. For test purposes the opto-hybrid has been temporarily connected to ancillary circuits for power supply and signal injection. The test set-up includes an  optical receiver, which converts the optical signal into the electrical output  to be read by the scope or by the spectrum analyser. A set of routines, written  in Labview 5.1, allows the remote control of the instruments and the automatic execution of the electrical tests. For a preliminary validation of the opto-hybrid circuits, the measurements to be performed are gain, integral-non-linearity, signal-to-noise ratio, crosstalk and bandwidth. The gain of the optical link is defined as the ratio between the output electrical signal and the corresponding pulse injected at the opto-hybrid input and is pre-settable through the programmable laser driver up to a value of 2.5. The gain test has shown a good agreement between the measurements and the values set via the laser driver. The integral-non-linearity (INL) test gives the deviation from a linear fit of the measured output values versus an increasing input voltage. The tested opto-hybrid chips have shown an INL estimated to be less than 3%, according to the request asked for its performances. The crosstalk is the noise measured on adjacent channels when one laser chip is pulsed. This test was affected by an impedance mismatch, which will be removed in further measurements, but the low noise values found were, nevertheless, encouraging. In order to completely characterise the opto-hybrid behaviour, thermal cycles and  irradiation with particles are foreseen. All these tests will guarantee the correct operation of the opto-hybrid once in the hostile environment of the LHC tunnel.

Progress in Development of the Analogue Readout Chip for Si Strip Detector Modules for LHC Experiments

E. Chesi, A. Clark, W. Dabrowski, D. Ferrere, J. Kaplon, C. Lacasta, J. Lozano, S. Roe, R. Szczygiel, P. Weilhammer, A. Zsenei.

We present a new version of 128-channel analogue front-end chip SCT128A for readout of silicon strip detectors. Following the early prototype developed  in the DMILL technology we have elaborated a design with the main goal to improve its robustness and radiation hardness. The improvements implemented in the new design are based on experience gained on the DMILL technology while developing the binary readout chip for the ATLAS Semiconductor Tracker. The architecture of the chip and critical design issues will be discussed. The performance of modules built of ATLAS baseline detectors read out by 6 SCT128A chips will be presented and discussed.

Summary: In parallel to development of the binary readout chip for the ATLAS Semiconductor Tracker we have been developing a chip with analogue readout   architecture - SCT128A. Both chips have been developed in the DMILL technology and employed the same concept of a fast front-end circuit based on bipolar transistors. Analogue architecture has a number of potential advantages compared to the binary one. A feature, which is particularly important for large installations like trackers for LHC experiments, is immunity of this architecture to common noise effects. First prototype of the SCT128A chip was designed and manufactured in an early stage of stabilisation of the DMILL process. In the meantime the DMILL process has been improved and stabilised. The development of the ABCD binary readout chip helped us to understand better and quantify various aspects of the process like matching, parasitic couplings through the substrate and radiation effects. The conclusions from the work on the ABCD chip have been implemented in the new design of the SCT128A chip with a main goal to improve robustness   and radiation hardness of the new chip. The SCT128A is designed to meet all basic requirements of a silicon strip tracker for LHC experiments. It comprises five basic blocks: front-end amplifiers, analogue pipeline (ADB), control logic including derandomizing FIFO, command decoder and output multiplexer. The front-end circuit is a fast transimpedance amplifier followed by an integrator, providing a semi-gaussian shaping with a peaking time of 20-25ns, and an output buffer. The peak values are sampled at 40 MHz rate and stored in the 128-cell deep analogue pipeline. Upon arrival of the trigger the analogue data from the corresponding time slot in the ADB are sampled in the buffer and sent out through the analogue multiplexer. The gain of the front-end amplifier is of about 50mV/fC. The designed peaking time for the nominal values of resistors and capacitors is 20ns. The front-end circuit is designed in such a way that it can be used with either polarity of the input signal, however the full read-out chain (NMOS switches in the analogue pipeline, output multiplexer) is optimised for the p-side strips. The dynamic range of the amplifier is designed for 12fC input which together with the gain of 50mV/fC gives the full swing at the output of the front-end in the range of 600mV. The current in the input transistor is controlled by an internal DAC and can be set within the range from 0 to 320 microA. This allows one to optimise the noise according the actual detector capacitance. The design  and the performance of the chip will be presented. The basic chip performance has been evaluated in the test bench. Analogue prototype module consisting of two 6.4 cm x 6.3 cm ATLAS baseline detectors read out by SCT128A chips has been built. The chips are mounted on a ceramic hybrid connected to the sensors in the end-tap configuration. The performance of the module will be presented and discussed.

Quality Assurance Programme for the Environmental Testing of CMS Tracker Optical Links

K. Gill, R. Grabit, M. Hedberg, J. Troska, F. Vasey and A. Zanet
CERN EP Division.

The QA programme for the environmental tests of the COTS components for the CMS Tracker Optical link system is presented. These tests will take place in the pre-production and final production phases of the project and will measure radiation resistance, component lifetime, and sensitivity to magnetic fields. The results are summarized from the extensive series of earlier prototype sample testing and the evolution of these small-scale tests to the pre-production final manufacturing tests is outlined.

Summary: Final production of the CMS Tracker optical links will begin in 2001 and continue until 2004. Approximately 40000 uni-directional analogue optical links, and ~1000 bi-directional digital optical links will be produced during this time. Full details of the two types of optical link system, including the quantities of components and their specifications, can be found on the web[1].

Both analogue and digital optical links for the CMS Tracker share the same basic components, namely 1310nm InGaAsP/InP multi-quantum-well edge-emitting lasers and InGaAs p-i-n photodiodes coupled to single-mode optical fibre. The optical fibre is in the form of buffered single-way fibre, ruggedized 12-way ribbon fibre cable, and dense 96-way multi-way ribbon cable, with MU-type single way and MT-type multi-way optical connectors used at the various optical patch panels. All of the devices listed here are commercial off-the-shelf (COTS) components.

Quality Assurance (QA) procedures have been developed in order to guarantee that the final links meet their specified performance and are produced on schedule. A full QA manual has been written and in this paper we focus on the part of the QA programme concerning environmental testing of components.

The CMS Tracker environment is characterized by the high levels of radiation, up to ~2x10^14/cm^2 fluence and 100kGy ionizing dose for the optical link components over the first 10 years of operation[2]. The particle fluence at the innermost detector modules of the Tracker is dominated by pions and photons, with energies ~100MeV, and by ~1MeV neutrons at the outermost modules. In addition the components must operate in a 4T magnetic field and at temperatures close to -10§C.

The extensive use of COTS components in the optical links means that all prototype devices have had to be thoroughly tested. The resistance to radiation and magnetic fields are not product characteristics that are normally specified or guaranteed by telecommunications manufacturers. In extensive prototype sample tests we have measured the radiation effects in all of the optical link components, for fluences and doses typical of CMS Tracker worst-case conditions[3]. The set of results will be summarized in the full paper.

Despite having restricted the final choice of candidate components to those that have passed earlier sample tests, the use of COTS means that environmental QA testing must continue into the production phase of the project. This is simply because the factors that can affect the radiation hardness of given components are not well understood in terms of their sensitivity to any changes, however slight, in the component production method. These tests are separated into 'Advance Validation' and 'Pre-production Qualification'. In the case of the lasers, p-i-n photodiodes and the optical fibres, given the large quantities required and their observed sensitivity to radiation damage, it is desirable to do the radiation tests before the final lots have been produced and delivered to CMS. These tests are therefore carried out as Advance Validation tests which means that we will carefully screen every wafer, in the case of lasers and p-i-n photodiodes, and every glass preform, in the case of optical fibres, using a number of representative samples. It is understood that this is an unusual method of component validation, necessitating a very good working relationship with the component manufacturers.

For the other components, namely the hybrids and the terminated optical cables where there are fewer devices required, or where the radiation damage is expected to be less significant, the environmental tests will be carried out as part of the more general Pre-production Qualification.

[1] CMS Tracker Optical Links www pages, http://cms-tk-opto.web.cern.ch
[2] CMS Tracker Technical Design Report.
[3] Papers in previous LEB Workshop, RADECS and SPIE Proceedings. (1996-2001). All available at [1].

TIM ( TTC Interface Module ) for ATLAS SCT & PIXEL Read Out Electronics

Jonathan Butterworth, Dominic Hayes(*), John Lane,
Martin Postranecky, Matthew Warren
University College London, Department of Physics and Astronomy
( * now at Radiocommunications Agency, London )

Summary: The TIM ( TTC Interface Module ) has been designed to provide the interface between the ATLAS Level-1 Trigger and the SCT and PIXEL off-detector electronics.

There will be one TIM module in each of the 9U-sized off-detector ROD ( Read Out Driver ) crates, distributing the timing, trigger and control signals to all the ROD modules in each crate via a custom-designed J3 backplane and BOC ( Back Of Crate ) modules.

Each TIM receives the TTC ( Timing, Trigger and Control ) information in optical form from the LHC-standard TTC distribution system, using the standard TTCrx receiver and decoder chip to provide electrical outputs.

Each TIM receives in turn the ROD BUSY signals from each ROD in the crate and transmits a masked-OR Busy signal to the Level-1 Trigger via a ROD Busy Module.

Two prototype TIM modules have been manufactured last year and have been extensively tested since that time at UCL. One module has been in use in the ROD System Tests at Cambridge from May 2001. Following these tests, further TIM modules are being built to allow for further ROD System and Front End Module testing at various sites around the world.

The TIM has been designed as a 9U multilayer PCB with a standard VME slave interface, with all registers and configuration, control and monitoring accessible to the local crate processor. All the major logic elements of the TIM module are contained on ten large scale PLDs (Programmable Logic Devices ), allowing for possible future design changes by firmware modification.

Each TIM is also capable of fully stand-alone operation, generating all the TTC-type signals under the control of the local processor. Each TIM can also act as a 'master' to synchronise a number of 'slave' TIM modules to allow for a stand-alone operation of a system consisting of more than
one ROD crate.

As well as being the 'standard' TTC Interface Module for the SCT off-detector electronics, TIMs will also be provided to the PIXEL detector
community, and possibly other detectors, to provide them with the TTC interface.



ABSTRACT :
----------

The design, functionality, description of hardware and firmware and
preliminary results of the ROD ( Read Out Driver ) System Tests of the
the TIM ( TTC Interface Module ) are described.

The TIM is the standard SCT and PIXEL detector interface module to the
ATLAS Level-1 Trigger, using the LHC-standard TTC ( Timing, Trigger and
Control ) system.

TIM has been designed and built during the year 2000 and two prototypes
have been used since. More modules are being built this year to allow for
more tests of the ROD system at different sites around the world.

Design and Test of a DMILL Module Controller Chip for the Atlas Pixel Detector

Abstract:
The main building block of the Atlas Pixel Detector is a "module" made by a Silicon Detector bump-bonded to 16 Analog Front-End chips. All FE's are
connected by a star topology to the MCC. MCC does system configuration, event
building, control and timing distribution. The electronics has to tolerate
radiation fluences up to 10^15 cm^-2 1Mev in equivalent neutrons during the first three years of operation.
The talk describes the first implementation of the MCC in DMILL (a .8um
Rad-Hard technology). Results on tested dices and irradiation results of this
devices at the CERN PS, up to 30 MRad, will be presented.
The chip was operating during irradiation and allowed to measure SEU effects.

Summary:
The Module Controller Chip (MCC) is an ASIC which provides complete control of
the Atlas Pixel Detector module. Besides the MCC the module hosts 16 FE chips
bump-bonded to a Silicon Detector.

The talk is divided in three sections.

In the first section we describe the requirements that the MCC has to fulfil.
Main features of this device are the ability to perform event building which
provides some data compression on data coming from 16 Front-End chips read out
in parallel. The system clock frequency is 40MHz. Inside the MCC 16 Full
Custom FIFO's temporary store data received by the FE chips. Event Building is

performed by extraction of hits from those FIFO's and formatting the event in
one or two serial streams that allow a data transfer up to 160 Mbit/s.
All the operations on the module (configuration of MCC and FE's, trigger and
resets) are performed by means of a serial protocol which is decoded inside
the MCC. The Trigger command decoding is done allowing for a single bit flip
on the data line without loss of timing information.

First a prototype and then a full version of the chip where designed and
tested. This is described in the second section of the talk. The prototype
chip, called MCC-D0 is made of a Full Custom FIFO, the whole Command Decoder
and an array of configuration registers.
The second chip is a full scale MCC (MCC-D2) designed to be integrated in a
Rad-Hard version of the module.

The third part describes in detail the tests made on both chips focusing on
the irradiation tests done at PS at CERN where 8 MCC-D0's were successfully
irradiated up to 30 MRad. The chips were irradiated while operating them. This
allowed us to perform a detailed measurement of both static and dynamic Single
Event Upset (SEU) effects. We also describe our test system, developed in
Genova, which allows a comparison between the actual hardware, hosted on a VME
board, and a C++ simulation of the MCC.