Trigger Throttling System for CMS DAQ

A. Racz / CERN-EP

Abstract:

This document is a first attempt to define the basic functionnalities of the TTS in the CMS DAQ. Its role is to adapt the trigger pace to the DAQ capacity in order to avoid congestions and overflows at any stage of the readout chain. The different possibilities for the TTS to measure the load on parts of the chain are examined. It clearly appears that one part of the chain needs fast reaction time (few tens of useconds) whereas the rest of the chain can afford longer reaction time, available to nowadays processors.

Summary:

The role of the CMS Trigger Throttling System has been described in global terms. The situation regarding the different stages of the data acquisition chain is quite different. Intrinsically, the most problematic parts are the front-end systems where full custom solutions must be developed. For the rest of the chain, standard and well known solutions can be used.

After this first analysis, it has been shown that the TTS can be split logically and physically into two parts:

- a first one featuring quick reaction time, custom hardware, located in the global trigger logic

- a second one with slower reaction time, running on the BM processors

Finally, depending on the overflow recovery procedure, the DAQ availability time can be reduced by an inacceptable factor.

First evaluation of neutron induced Single Event Effects on the CMS barrel muon electronics

S. Agosteo(1), L. Castellani(2), A. Favalli(1), I. Lippi(2), R. Martinelli(2) and P. Zotto(3)
1) Dip. di Ingegneria Nucleare (CESNEF) del Politecnico di Milano, Italy
2) Dip. di Fisica dell'Universit and sez. INFN, Padova, Italy
3) Dip. di Fisica del Politecnico di Milano and sez. INFN di Padova, Italy

Abstract:

Neutron irradiation tests of the currently available electronics for the CMS barrel muon detector were performed using thermal neutrons and fast neutrons at E < 11MeV. The Single Events Upset on the Static RAM was measured, while upper limits are derived for devices having experienced no failure. The results are used to guess the upper limits on the mean time between failures in the whole barrel muon detector.

SEU tests of an 80Mbit/s optical receiver

F. Faccio, K. Gill, M. Huhtinen, A. Marchioro, P. Moreira, F. Vasey
CERN, CH-1211 Geneva 23, Switzerland

G. Berger
Cyclotron Research Center, UCL, B-1348 Louvain-la-Neuve, Belgium

Abstract:

The sensitivity to SEU is presented for a rad-hard 80Mbit/s receiver developed for the CMS Tracker digital optical link. Bit Error Rate (BER) measurements were made while irradiating with 59MeV protons and 62MeV neutrons, for different angles to the beam and for a wide range of optical power in the link. The photodiode is the most sensitive element to SEU. Direct ionisation can explain the SEU rate for protons incident at high angles of incidence and nuclear interactions explain the SEU rate for incident neutrons, as well as for protons for the low angles of incidence and higher optical power.

Summary:

The LHC experiments will use thousands of digital optical link channels for the transmission of timing, trigger and control signals. A large number of optical receivers will seat inside the detector, operating in a radiation environment. Radiation will threaten the correct operation of the optical receivers by degrading the performance of the photodiode, the receiver circuit, or by inducing errors (Single Event Upsets) in the data transmission. To study the sensitivity to radiation-induced errors of the rad-hard 80Mbit/s receiver developed for the CMS Tracker digital optical link, we have exposed the receiver to beams of 59 MeV protons and 62 MeV neutrons.

We performed BER measurements at CERN and at the irradiation facility (CRC, in Louvain-la-Neuve) to verify the reliability of our measurement system in the absence of irradiation. Then, we repeated the measurement in presence of proton and neutron beams. The measurements confirm that the most sensitive element to SEU is the PIN photodiode and not the receiver chip. This was expected on the basis of previous works and of the much greater sensitive volume for charge collection of the photodiode (80 µm in diameter and 2 µm in thickness). Errors induced by ionization in the photodiode occur only during the transmission of a '0' symbol.

By changing the angle of the photodiode to the beam, and by comparing proton and neutron irradiation results, we were able to distinguish between errors induced by direct ionization (from the protons) and by nuclear interactions in the diode (from both protons and neutrons). Protons incident at high angle, that is almost parallel to the diameter of the photodiode, have a sufficiently long trajectory in the sensitive volume to induce an error via direct ionization. Instead, when the angle is low (45o or less), the path-length of the protons in the sensitive volume is only a few microns at most, and the energy deposited via direct ionization is not sufficient to cause SEU. In this case, errors are dominated by ionization from heavy recoils originated from nuclear inelastic interaction of the incident protons in the photodiode. This is confirmed by the neutron irradiation measurements, for which the error cross-section (the number of errors divided by the particle fluence) is equivalent to the one measured for protons at low angles of incidence. Moreover, as expected for processes dominated by inelastic scattering, no angle dependency was observed for the neutron irradiation.

An increase of the optical power raises the threshold for errors and we observe, in all cases, a decrease of the error cross-section at high optical power. We can estimate that, for the optical receiver tested, an optical power of about -12dBm (corresponding to 63 µW) is necessary to achieve a BER below 10-12 in the presence of a particle flux of about 106 cm^-2 s^-1. A similar flux of hadrons above 5 MeV is expected in the silicon tracker of CMS, at a radial distance of about 40cm.

Status of the 80Mbit/s Receiver for the CMS digital optical link

F. Faccio, C. Azevedo, K. Gill, P. Moreira, A. Marchioro, F. Vasey
CERN, CH-1211 Geneva 23, Switzerland

Abstract:

The first prototype of the 80Mbit/s optical receiver for the CMS digital optical link has been manufactured in a 0.25µm commercial CMOS process. Its performance satisfies the low power, wide dynamic range, and speed specifications. The required sensitivity (BER of 10^-12 for an optical power of -20dBm) is easily achieved, since this BER is obtained already at -27dBm. The radiation hardness has been verified irradiating the diode with 6 MeV neutrons (up to 6.5·10^14n/cm2) and the receiver circuit with 10KeV X-rays (up to 20 Mrad). Neither type of irradiation did sensibly modify the BER performance of the receiver.

Summary:

The CMS tracker will use approximately 1000 digital optical links for the transmission of timing, trigger and control signals. An optical receiver, made up of a PIN photodiode and a receiver circuit, will convert the digital optical signals into electric signals in a LVDS logic signal. Since the communication channel end sitting inside the CMS detector will work in a harsh radiation environment, radiation hardness is a must for both the photodiode and the receiver circuit. For this reason, and also to decrease the power budget of the receiver, the circuit has been developed as an ASIC in a 0.25µm commercial CMOS technology. The design has been made using enclosed NMOS transistors and guardrings, techniques that have been proven to achieve multi-Mrad TID hardness and to protect the circuit from Single Event Latchup (SEL).

The ASIC has been fabricated and completely characterised before and after irradiation. The power consumption is limited to about 30mW per channel, a factor of ten smaller than for a commercial radiation-soft component with similar performance. To precisely evaluate the sensitivity of the receiver, we have performed Bit Error Rate (BER) measurements at a bit rate of 80Mbit/s using a dedicated setup. The measurements have been made in a configuration similar to the one foreseen for the CMS tracker optical link. Two Fermionics FB80S-7F InGaAs/InP photodiodes have been bonded to two of the receiver channels of the ASIC, one link being dedicated to the clock and the other to the data transmission. In this condition, and with an optical power in the link of -20dBm (which corresponds to 10µW, the minimum specified level), we did not detect any transmission error in more than 15 days, from which we infer a BER below 9.3·10^-15. The CMS digital link requires a BER of 10^-12, which is reached in our configuration for an optical power of about -27dBm (2 µW).

The radiation hardness of the optical receiver has been verified in two ways. First, several photodiodes were irradiated with 6 MeV neutrons up to a fluence of 6.5·10^14 n/cm2. Two irradiated photodiodes were bonded to the receiver circuit, and the BER of the resulting optical receiver channels was measured, revealing no difference from channels where non-irradiated photodiodes were mounted. Second, the radiation hardness of the ASIC was verified with X-ray irradiations up to a TID of 20 Mrad(SiO2). We did not observe any radiation-induced degradation in the BER of the circuit, and the power consumption increase was limited to about 7%.

LHC machine timing distribution for the experiments

B.G. Taylor, CERN for the RD12 Collaboration

Abstract:

At the LHC the 40.079 MHz bunch crossing clock and 11.246 kHz machine orbit signal must be distributed from the Prevessin Control Room (PCR) to the TTC systems of the 4 LHC experiments, to the test beam facilities in the West and North areas and to beam instrumentation around the ring.

To achieve this, a single high-power laser transmitter with optical fanout to all the destinations has been installed at the PCR. A standard TTC machine interface (TTCmi) has been developed which receives the signals and can deliver very low jitter timing signals to LHC experiment TTC distribution systems with multiple trigger partitions.

Summary:

At the LHC the 40.079 MHz bunch clock and 11.246 kHz machine orbit signal must be distributed from the Prevessin Control Room (PCR) to the TTC systems of the 4 LHC experiments and to beam instrumentation located at 24 points around the ring. Also, during LHC-structured SPS beam tests, the bunch clock and 43.375 kHz SPS orbit signal must be broadcast to the test beam facilities in the West and North areas.

To achieve this, a single high-power 1310 nm laser transmitter has been installed at the PCR. The bunch clock and the LHC and SPS orbit signals are received from the BA3 Faraday Cage by coaxial cables with galvanic isolation. A VCXO-PLL in the laser transmitter reduces the clock jitter and a synchronizer prevents metastability of the SPS orbit signal, whose frequency swings 29 Hz during acceleration. The 40.079 MHz clock has a constant frequency and before each slow extraction the SPS is rephased to it, just as it will be before each transfer to the LHC when it is used as injector.

The encoded laser transmitter signal is fanned out by a passive optical tree coupler and distributed to all the destinations by singlemode fibres. These distribution fibres are largely underground and preliminary tests over a 13 km link have shown that the diurnal variation in the phase of the received 40.079 MHz clock is very small.

A standard TTC machine interface (TTCmi) has been developed which receives the optical signals at the LHC experiments, decodes the composite signal and reduces the bunch clock jitter to less than 10 ps rms (about 6% of the rms bunch collision length). To compensate for the phase differences in the orbit signal received at different locations around the LHC ring, the TTCmi provides for the phase of the signal to be adjusted throughout the 88.924 µs period in 3564 steps of the bunch-crossing interval of about 25 ns.

The TTCmi incorporates an optical signal monitor and a biphase mark encoder for local TTCtx laser transmitters, which can broadcast the TTC signals to up to 8960 destinations per crate. It can also deliver the low-jitter clocks electrically to multiple TTCex encoder/transmitters at LHC experiments with up to 40 independent trigger partitions.

A TTCmi has been constructed for each of the LHC experiments and units have been installed at the X5 and X7 test beam facilities in the West Area and at H2, H4 and H8 in the North Area. As with the TTC systems at the experiments, the use of a single CERN-wide system for the distribution of the LHC machine timing signals is expected to result in cost savings and operational and maintenance advantages.

Development of a 24 ch TDC LSI for the ATLAS Muon Detector

Yasuo Arai, KEK, National High Energy Accelerator Research Organization, Institute of Particle and Nuclear Studies
and
T. Emura, Tokyo University of Agriculture and Technology

Abstract:

A TDC LSI for the ATLAS precision muon tracker (MDT) has been developed. A prototype chip (AMT-1) was processed in a 0.3 um CMOS Gate-Array technology. It contains full functionality of the final TDC.

To get a high resolution around 300 ps, an asymmetric ring oscillator and a PLL circuit are used. All the I/O signals which are active during measurement has LVDS interfaces. A JTAG interface is used for boundary scan and internal register setup. All the memory and control bits has parity bits so that a SEU can be detected. Radiation tolerance for Gamma-ray and Neutron are also reported.

Summary:

A TDC LSI for the ATLAS precision muon tracker (MDT) has been developed. A prototype chip(AMT-1) was processed in a 0.3 um CMOS Gate-Array technology. It contains full functionality of the final TDC; 24 input channels, 256 words level 1 buffer, 8 words trigger FIFO and 64 words readout FIFO. It also include trigger matching circuit which selects data according to the trigger ID. The selected data are transferred through 40~80 Mbps serial line with DS-Link protocol.

To get a high resolution around 300 ps, an asymmetric ring oscillator and a Phase Locked Loop(PLL) circuit are used. These time critical parts were routed in manually. All the input and output signals which are active during measurement has LVDS interfaces. A JTAG interface is used for boundary scan and internal register setup. All the memory and control bits has parity bits so that a Single Event Upset can be detected.

The chip is packaged in a 144 pins plastic QFP with 0.5 mm pin pitch and about 107k gates are used. Gamma-ray irradiation and Neutron exposure are planned. Performance of the TDC chip and radiation tolerance will be reported.

Implementation of Sorting Schemes in a Programmable Logic

Mikhail Matveev (Rice University, Houston, TX 77005)

Abstract:

Trigger systems of each CMS muon subdetector (Cathode Strip Chambers, Drift Tubes, Resistive Plate Chambers) will have a muon sorter unit in their upper parts. We report on a design and simulation results for the following sorting schemes: "3 objects out of 18", "4 objects out of 8", "4 objects out of 24" and "4 objects out of 36". All designs are targeted to a single chip implementation based on Altera 20KE Programmable Logic Devices (PLD). The PLD internal sorting latency varies between 1 and 3 cycles of 40MHz clock frequency. Proposed schemes can be used for the fast sorting at the CMS Muon subsystems as well as other trigger systems at LHC experiments.

Summary:

All experiments proposed at the Large Hadron Collider at CERN require a fast and sophisticated multi-level trigger system for data selection. For example, the main task of Level 1 Trigger System at the Compact Muon Solenoid (CMS) Experiment is to reduce the frequency of events from 40MHz down to 100kHz. Level 1 decision should be made in about 3 us after the interaction in the collision area. There are three major muon subsystems at the CMS: Cathode Strip Chambers (CSC), Drift Tubes (DT), and Resistive Plate Chambers (RPC). Currently it is decided that only four best candidates from each subsystem will be passed to the Level 1 Global Muon Trigger. It is considered that there will be a sorter module at the upper part of each muon trigger subsystem which selects four best candidates from several tens of incoming. We propose a fast and flexible solution which would allow to implement such a sorters. Four sorting schemes are discussed: "3 objects out of 18", targeted to Muon Port Card at the CSC Trigger system, "4 objects out of 8" intended for the RPC Sorting Processor, "4 objects out of 24" for the DT Muon Sorter, and "4 objects out of 36" for the CSC Muon Sorter.

We assume that sorting is based on the value of input patterns: higher ranks correspond to "better" patterns for the purpose of sorting. All schemes are targeted to a single chip implementation in order to reduce the overall sorting latency. Each chip receives 8, 18, 24 or 36 7- or 8-bit input patterns and outputs three or four best along with their 5- or 6-bit addresses. We also assume that all patterns come to sorter chip in parallel being synchronized with the main master clock. Input, output and in some cases intermediate latches provide a reliable synchronous operation and predictable timing. Our task was to provide a reliable operation at 40+Mhz with the minimum latency. Finally we assume that all inputs are not pre-selected (or ranked), but all outputs of the sorter chip should be ranked, or present on the outputs of the sorter chip in descending order.

We focus on the implementation of all sorting schemes in Programmable Logic Devices (PLD) rather than in ASIC. The important advantages of using PLD are low non-recurring fees, reprogrammable features as well as a shorten design cycle. Our designs are targeted to Altera 20KE PLD family. All timing parameters are obtained for the fastest available devices.

All sorting schemes are based on multiple comparisons and data multiplexing. We perform as much comparisons as possible (taking into account the architecture of particular PLD) in parallel at the beginning of sorting in order to reduce the number of steps in sorting tree. In case of (n) input patterns the total number of all comparisons between them in N=n(n-1)/2. N results of comparisons would allow us to obtain (4n) combinatorial signals indicating that the particular pattern is the first, second, third, or fourth best. Further these (4n) signals are used for pattern multiplexing onto chip outputs.

Results of simulation using Altera Quartus software are presented. Sorting "3 out of 18", "4 out of 8", "4 out of 24" and "4 out of 36" can be done inside PLD in one, one, two and three clock cycles of 40Mhz clock frequency respectively.

Single Event Upset Studies for the ATLAS SCT and Pixel Optical Links

D.G.Charlton, J.D.Dowell, R.J.Homer, P.Jovanovic, G.Mahout, H.R.Shaylor, J.A.Wilson
School of Physics and Astronomy, University of Birmingham,UK

R.L. Wastie, A.R. Weidberg
Physics Department, Oxford University, U.K.

J.K. troska, D.J. White
Rutherford Appleton Laboratory, U.K.

I-M Gregor
Physics Department, Wuppertal University, Germany.

Abstract:

The readout of the ATLAS SCT and Pixel detectors will use optical links. The radiation hardness of all the components has been extensively studied but this paper discusses the operation of these links in simulated LHC radiation environments. Nuclear interactions can deposit large amounts of energy in electronic components which can cause Single Event Upsets
(SEU). The SEU rates have been measured with MIPS from a beta source, low energy neutrons, pions and protons at PSI. The dominant source of SEU effects is from energy deposition in the active region of the PIN diodes.

Summary:

Optical links will be used in the ATLAS SCT and Pixel detectors to transmit data from the detector modules to the off-detector electronics and to distribute the Timing, Trigger and Control (TTC) data from the counting room to the front-end electronics. The radiation hardness of the individual components has been extensively studied. The optical links have been shown to operate at very low Bit Error Rates (BER) in the laboratory. This paper reports on studies of the operation of the links in simulated LHC radiation environments. The flux of pions during high luminosity operation at the LHC will be up to 4 10**7/cm**2/s for the detector closest to the beam line (the Pixel B-layer). The particle flux falls of rapidly with perpendicular distance from the beam line. Nuclear interactions in the detector can deposit sufficient energy in the active volumes of the opto-electronics and electronics to cause bit errors. The rates of Single Event Upsets (SEU) have been studied by measuring the BER while irradiating the opto-electronics with different particles. Minimum Ionising Particles (MIPs) were produced with a Sr90 source, neutrons from deuteron stripping and (d,t) reactions. The SEU rates have also been measured with pions and protons in the momentum range 215 MeV/c to 465 MeV/c at the Paul Scherrer Institute. This momentum range is very similar to that of pions produced in minimum bias interactions at the LHC.

MIPs do not cause any measurable SEU. A significant rate of SEU has been measured for neutrons, pions and protons. The dominant source of this SEU is due to nuclear interactions in the active volume of the PIN diode which deposits sufficient energy to trigger the DORIC4 receiver ASIC. Hence from the point of view of the DORIC4, the energy deposition is effectively a genuine signal. The effective threshold can therefore be raised by increasing the amplitude of the TTC optical signal generated in the counting room. The rate of SEU is found to decrease strongly as the effective threshold is increased. The ASICs have been designed to avoid destructive effects and no evidence for such effects has been found.

The measured SEU data are compared with theoretical calculations. These calculations are then used to extrapolate the measured BER to LHC conditions and hence predict the bit error rate during LHC operation. Even for the highest particle fluxes at the B layer of the Pixel detector, the BER can be reduced to a level below 10**-9, by using a sufficiently large amplitude optical signal for the TTC data. Therefore the problem can be reduced to a rate which is acceptable for ATLAS operation.

Radiation Hard Optical Links for the ATLAS SCT and Pixel Detectors

D. Charlton, J.D.Dowell, R.J.Homer, P. Jovanovic, G.Mahout, H.R.Shaylor, J.A.Wilson.
School of Physics and Astronomy, University of Birmingham, Birmingham, B15 2TT, UK

I.M. Gregor, R.Wastie, A.R. Weidberg
Physics Department, University of Oxford, Keble Road, Oxford, OX1 3RH, UK.

S.Galagedera, M.C.Morrissey, J.Troska, D.J.White.
CLRC Rutherford Appleton Laboratory, Chilton, Didcot, Oxon, OX11 0QX, UK.

A.Rudge
CERN, Geneva, Switzerland.

M.L.Chu, S.C.Lee, P.K.Teng
Institute of Physics, Academia Sinica, Taipei, Taiwan 11529, Republic of China.

Abstract:

A radiation hard optical readout system designed for the ATLAS Semi-conductor Tracker (SCT) is described. Two independent versions of the front-end optical package housing two VCSEL emitters and an epitaxial Si PIN photodiode have been irradiated with neutron fluences over 1015 n.cm-2, the level encountered in the ATLAS pixel detector. Environmental tests have been performed down to -20o C. Extensive radiation and lifetime tests have also been carried out on the opto-electronic components and the front-end VCSEL driver and timing/control ASICs. Bit error rate and cross-talk measurements using irradiated devices show that the system easily meets the performance specification.

Summary:

The ATLAS SemiConductor Tracker (SCT) and Pixel detectors will be read out using optical links. The Timing, Trigger and Control (TTC) data are delivered from the off-detector electronics to each detector module by a single optical fibre using an epitaxial Si PIN photodiode as the receiver. The binary data are transmitted using VCSELs operating at 850 nm. Two VCSELs and one photodiode are mounted in a low mass, non-magnetic optical package on each module. Several packaging technologies have been studied and so far two different packages have been successfully developed using different methods for optically coupling the optical fibres to the VCSELs and photodiodes. Radiation hard ASICs have been developed to drive the VCSELs (VDC chip) and to recover the 40 MHz clock and the TTC data from the photodiode signals (DORIC4 chip). Each component, as well as the complete packages, has been extensively tested after irradiation with neutrons and gammas.

Mitel VCSELs have been tested and show good recovery after a short annealing period following irradiation with 2.9x1015 1 MeV equivalent neutrons.cm-2, which is a typical fluence in the pixel detector after 10 years of LHC operation. The total light output before irradiation is typically 1 mW for a current of 10 mA. The main effect of neutron irradiation is to shift the threshold current upwards substantially, which reduces to about 1 mA after annealing, without changing the slope of the light output vs current. The PIN photodiodes (manufactured by Centronic) show a drop in responsitivity of about 30% to 0.3 A/W after irradiation up to 1015 n.cm-2 and an increase in dark current to 60 nA at room temperature which is negligible. Both VCSELs and photodiodes have undergone accelerated ageing tests at elevated temperatures after irradiation. They show excellent reliability (no failure) after several hundred equivalent LHC years corresponding to a failure rate of < 1% after 10 years of LHC operation.

The VDC and DORIC4 use bipolar npn transistors in the AMS 0.8 micron BiCMOS technology. Samples have been exposed to 2.5 1014 1 MeV equivalent neutrons/cm2 and 115 kGy of gamma radiation. All chips work correctly after irradiation. The circuits are designed to work with transistor beta values as low as 10. Measurements of beta before and after irradiation are presented. Accelerated ageing tests have been carried out at 100oC on a sample of DORIC4s under operational conditions without any failure, corresponding to a 0.3% upper limit (90% c.l.) on the failure rate after 10 years of LHC operation.

Bit error rate and cross talk measurements have been carried out using packaged devices after irradiation. The performance is well within specification (< 10-9 BER for an optical power of 200 muW). Single event upset measurements using neutrons and ionising radiation have also been performed and are reported in a separate paper.

The conclusions are that a successful readout scheme has been developed for the SCT, and that the optoelectronic components and packaging are also adequate for the higher radiation levels in the pixel detector.

Measurements of Radiation Effects on the Timing, Trigger and Control Receiver (TTCrx) ASIC

Thomas Toifl, Paulo Moreira, Alessandro Marchioro
CERN

Abstract:

The Timing, Trigger and Control Receiver Asic (TTCrx) receives and distributes the clock, the trigger decision, and other synchronisation signals. In this paper the radiation-hard version of the TTCrx, manufactured in DMILL technology, is discussed. First, the architecture of the circuit is described, where we concentrate on the changes to the existing prototype and on the measures taken to increase robustness with respect to single event upsets (SEU). In the second part we will present measurements of the circuit characteristics before and after irradiation with gammas and neutrons. In the last part we will then show measurements of the SEU behavior.

Summary:

A tree network of optical fibres will be used for the distribution of the clock, trigger and control signals to the LHC particle detector systems as defined by the RD12 collaboration. At the receiver side, a photodiode converts the optical signal into electrical impulses, which are then received by the Timing, Trigger and Control Receiver ASIC. The circuit recovers the clock and the encoded data from the incoming Biphase Mark encoded bitstream. It contains fine-deskew units to adjust the delay of the clock with a nominal delay resolution of 104 ps. The level 1 trigger and other synchronisation signals, e.g. the bunch counter reset signal, can be delayed by a programmable number of cycles. In addition, the chip decodes slow control data and makes them available to connected electronics on a parallel bus.

In the first section of the paper we will discuss the architecture and functionality of the circuit, where we concentrate on the changes to a previous prototype. We will also describe the design measures taken for increased robustness with respect to SEU effects.

In the second section of the paper we will present measurement results, divided into three parts: The first part contains general performance measures before irradiation. The second part is concerned with the measurement of total dose effects due to gamma and neutron irradiation. In the third part we will then show measurement results for the SEU sensitivity, for which the chip and the photodiode were irradiated in a proton, neutron and heavy ion beam.

The CMS DT Muon DDU: a PMC based interface between frontend and data-acquisition

F.Benotto, F.Bertolino, R.Cirio, G.Dellacasa
INFN Torino

Abstract:

CMS will use gas drift tubes as active part of the barrel muon sub-detector. In total 200.000 wires will be readout by TDCs and signals will be sent to data acquisition. The entrance door to the standard CMS DAS will be a board (Detector Dependent Unit - DDU) that will be specific to each sub-detector. We have built a PMC based prototype of the DT muon DDU that features two input channels with Optolink, data check and reconstruction with FPGA and PCI slave output through a FIFO. A description of the board and the FPGA schematics will be given and results from lab tests will be shown.

Summary:

We are developing a PCI Mezzanine Card based digital board that will be used as interface between the frontend electronics of the CMS barrel muon drift chambers and the standard CMS data acquisition system. The drift chambers that instrument the barrel muon detector of CMS will provide 200.000 TDC outputs. The whole frontend electronics will be housed in miniracks located inside the chambers mechanical structure. Each of the 60 sectors (12 phi * 5 weels) in which CMS is segmented will provide an output towards the standard CMS data acquisition. The board we are developing, named Detector Dependent Unit (DDU), will receive data from the sectors, work on them and send them to the standard CMS DAQ.  At the nominal LHC luminosity, the average occupancy of the barrel Drift Tubes will be 1 track/cm^2/s. This figure reflects in 1 muon/sector/event, that adds up to 144 bytes/sector. The total rate for the whole detector will then be 8 MBytes/s. The PMC that we are developing has two inputs, both with an optical transceiver, a serial link, a FIFO. After the two input FIFOs, data are flowing through a Xilinx, that formats them, detects errors and takes appropriate actions. The output of the Xilinx is  sent to a 32 bit output FIFO. The board is a PCI slave, through a PLX 9080 bridge, that can be read with DMA from the CMS DAQ. In case of  errors, the PMC can generate interrupts. The overall schematics of the board will be presented, together with the VxWorks based test setup and test results.

Project status of the CMS tracker optical links

F. Vasey, C. Azevedo, T. Bauer(1), B. Checucci(2), G. Cervelli, K. Gill,
R. Grabit, F. Jensen, A. Zanet
CERN, Geneva (Switzerland)
(1)HEPHY, Vienna (Austria)
(2)INFN, Perugia (Italy)

Abstract:

The development phase of the optical data transfer system for the CMS tracker is now complete. This paper will present the project status and review the preparation for production. In particular, it will focus on the results of the market surveys for front-end components, and on the performance evaluation of a close-to-final readout chain.

Summary:

The development phase of the optical data transfer system for the CMS tracker is now complete. The ~50000 uni-directional analogue links used for data readout are based on edge-emitting laser transmitters and pin photodiode receivers operating at a wavelength of 1310nm. In every single-mode fibre, 256 electrical channels are time-multiplexed at a rate of 40MSamples/s. Two in-line patch-panels allow to fan-in the individual fibres originating from the transmitters, first to a 12-way ribbon, and then to an 8-ribbon cable carrying 96 fibres away from the detector to the counting room. All system components situated inside the detector volume (lasers, fibres and connectors) are radiation resistant and non-magnetic. The laser transmitters and their connectorised pigtails are based on single-channel devices to best fit the distributed nature of the sensor elements, while in the counting room, the receivers are 12-channel arrays. The ~1000 bi-directional digital links used for control and timing distribution are based on almost identical components as the analogue readout system, but with a different modularity. The transceiver modules placed inside the detector include radiation resistant photodiodes and discriminating amplifiers (which are not needed in the readout system), and the transceiver modules located in the counting room are based on standard commercial components.

Apart from the custom designed electronics for the analogue and digital laser-drivers and photodiode-receivers, all optical link components are based on Commercial-Off-The-Shelf products (COTS). Slight deviations from the standard manufacturing process are only allowed to meet specific functionality requirements such as low back-reflection, or environmental constraints such as high magnetic field. This development strategy has the advantage of minimising development and system cost, but dictates the launch of extensive validation programmes to confirm that as wide a range of COTS as possible can be used reliably in the CMS tracker environment. Before invitations to tender can be sent out and orders can be placed to start the production of optical links in large quantities, potential suppliers must be qualified in the framework of open market surveys. In the case of the CMS tracker, optical components suppliers have been grouped in four categories: manufacturers of lasers, connectors, fibre-cables and receiver modules. As long as the tendering process for these components is not complete, it is not possible to know which exact devices will be used in the final system. By mid-2000, market surveys for semiconductor lasers and optical connectors will be complete, while the remaining surveys of fibre-cables and optoelectronic receiver modules will still be ongoing. In our presentation, we will present the status of these market surveys, review the results of the evaluation procedures, and discuss the plans and timescales to enter production.

In parallel to the tendering procedure, tests of readout and control chains are being performed with close-to-final components and architecture. The specifications will be reviewed and a model simulating the effects of components tolerances on full system performance will be discussed. New experimental results obtainted on a very realistic readout chain will then be presented, including for the first time an opto-hybrid transmitter module and a 12-channel analogue receiver module.

In summary, this presentation will review the system architecture and specification, discuss the results of the market surveys for front-end components, and present the performance evaluation of a close-to-final readout chain.

Calibration of the ATLAS Hadronic End-Cap Calorimeter

H. Brettel, W.D. Cwienk, L. Kurchaninov, H. Oberlack, P. Schacht
(Max-Plank-Institute for Physics, Munich, Germany)

A. Jusko, P. Strizenec
(Institute of Experimental Physics SAS, Kosice, Slovakia)

On behalf of the ATLAS HEC Collaboration

Abstract:

The calibration chain of the ATLAS HEC is described. A model based on detailed studies of all individual parts is presented.

The characteristics of the steering and data taking system for both the test-beam runs and for the acceptance tests of the HEC modules is summarized.

The calibration and signal reconstruction procedure is developed and results of the test-beam data are presented.

Radiation Test of CMS Endcap Muon Front-end Electronics with 63 MeV Protons

T.Y. Ling

Abstract:

After brief overview of the CMS EMU electronics system, results on Single Event Effects, TID and Displacement Effects due to neutron and ionizing radiation will be reported. These results are obtained by irradiating the front-end electronics boards with 63 MeV protons. During the irradiation, the electronics board was fully under power, all ASICs and COTS on the board were active and the data was readout in the same way as designed for CMS.

Silicon DAQ based on FPDP and RACEway

PHOBOS collaboration

Abstract:

DAQ for Si-detector of PHOBOS setup (RHIC) with Scalable Power for read out and Zero Suppression is described. Data from VA-HDR chips with analog multiplexor, are digitized by FADC. Digital buffers are multiplexed by DMU modules at speed 100 MBytes/sec and transmitted through FPDP and virtual extender of FPDP to fiber (FFI).

At the receiver end (in counting house) data from fiber are distributed between a number of dedicated processors (in RACEway multiprocessor frame) for Zero Suppression. After ZS data are concatenated and transmitted to Event Builder.

Summary:

Read out and Zero Suppression of Si-detector of PHOBOS experiment at RHIC is described.

Data from VA-HDR chips with analog multiplexor, are digitized by FADC. Digital buffers are multiplexed by DMU modules at speed 100MBytes/sec and transmitted through FPDP and virtual extender of FPDP to fiber (FFI).

As an interface for interconnection a Front Panel Data Port is used ( FPDP - a 160 Mbytes/s Front-Panel Data Port ). This is defacto standard in high data rate read-out and on February 11, 1999, FPDP was approved as an American National Standard Institute Standard, ANSI/VITA 17.

A number of firms supply products in that standard now, and there are few "extenders" which use Fiber Channel (ICS-7240, AAEC: FFOIB ) or HIPPI-Serial or G-link interfaces for FPDP.

FPDP is 32-bits synchronous data interface (with clock up to 40 MHz)

It's relatively simple, no backplane requires.

It could be "bussed" (up to 20-30 modules with FPDP could be connected to a 80-wires cable)

It doesn't require "software" control.

It's quite natural for FIFO read-out.

In the case of PHOBOS DAQ use of FPDP is attractive because it permits to make constructive block relatively simple and independent from fiber link. At stage of testing, FPDP cable could be connected without fiber link to RIN-T daughter-card of "Mercury" FPDP/RACEway interface).

Custom designed FFIs (Fiber FPDP link Interface) are used as an "virtual" extenders of parallel FPDP bus. HP's G-link and optical module FTR-8510 are main components of serial data transfer, and control logic is implemented in two fast ispLSI-2128. FFI module is built on VME-like board and uses only "+5V" and "Ground" lines. So it could reside either in standard VME crate or in custom crate. In the counting house we need RACEway access, so FFI is connected to RIN-T and ROU-T boards in MERCURY crate. In at the front end MDB crate FFI is connected to MDC (control unit) and DMUs.

At the receiver end (in counting house) data buffers from fiber interface (FFI) are distributed between a number of dedicated processors (in RACEway multiprocessor frame) for Zero Suppression. After ZS data are concatenated and transmitted to Event Builder.

Such approach permits to scale the power/speed of ZSS by changing the number of fibers and/or number of processors. It permits to use C language for ZS code, and to use different algorithms for different parts of detector.

Optical Data Transmission from the CMS Cathode Strip Chamber Peripheral Trigger Electronics to Sector Processor Crate

N.Adams, M.Matveev, T.Nussbaum, P.Padley (Rice University)
J.Hauser, V.Sedov (UCLA)

Abstract:

Data representing three muons will be sent from each sector of the CMS Cathode Strip Chambers to the Sector Processor crate residing in the counting room 100 m apart of the detector. We report on the data transmission scheme based on Agilent HDMP-1022/1024 serializer/deserializer chipset and Methode MDX-19 optical transceivers. Six chipsets and six pairs of optical modules are needed in order to transmit 120 bits of data every 25 ns of the main LHC frequency from the peripheral Muon Port Cards to Sector Receiver modules. Results of prototyping, laboratory tests as well as a possible future options for data transmission are discussed.

Summary:

The CMS Muon System consists of three detectors: Cathode Strip Chambers (CSC), Drift Tubes (DT) and Resistive Plate Chambers (RPC). There are up to four stations of CSC in each CMS endcap. CSC front-end electronics is located on chambers as well as in the VME crates mounted on the periphery of chambers. Trigger Motherboard (TMB) matches anode and cathode tags called Local Charged Tracks (LCT) and sends two best combined LCTs from each chamber to Muon Port Card (MPC). Each MPC collects muon tags from up to nine TMBs, which corresponds to a 60 degree sector for stations ME2-ME4 and a 30 degree sector for station ME1. All TMB and MPC cards are located in the VME 9U crates on the periphery of CSC. The MPC selects the three best muons and sends them over optical links to the Sector Receiver (SR) residing in the counting room 100 meters from the detector.

The main goal of the design was an evaluation of existing commercial solutions for the optical data transmission at 40.08MHz. Proposed design is based on Agilent HDMP-1022/1024 chipset and Methode MDX-19 optical transceivers. Six 20-bit chipsets and six pairs of optical transceivers are needed in order to transmit 120 bits of data representing three muons. Our implementation assumes simplex data transmission from the MPC to the SR without a return path. The transmitters use the main 40.08MHz frequency as a reference clock. At the receiver end, a clock oscillator with slightly different frequency is used for frequency acquisition.

Our prototypes have demonstrated a reliable operation at 40MHz. High power consumption and large board space required for optical modules and serializers or deserializers are drawbacks. Further possible implementations of data transmission circuitry from MPC to SR are discussed. One of these options may utilize the latest Agilent HDMP-1032/1034 chipset for serialization and deserialization. Another approach is to use a multi-channel optical receivers and transmitters. We can also use an appropriate commercial or custom solution adopted by other CMS groups.

Recent Progress in Field-Programmable Logic

Peter Alfke, Director, Applications Engineering, Xilinx, Inc

Abstract:

1. Programmable logic for ultra-low power applications. CPLDs operating with a few microamps of supply current, and FPGAs retaining configuration and register content with less than 100 microamps of supply current. An autoranging 400 MHz six-digit frequency counter consumes <2 mA in idle, <40 mA at 400 MHz input frequency.

2. FPGAs with > 1 Mbit of dual-ported on-chip RAM. FIFOs up to 1024 deep, 64 bits wide ( or wider), clocked at >150 MHz with independent read and write clocks

3. LVDS and LVPECL interfaces running at 622 MHz data rate, and recent developments at GHz serial data I/O.

4. Recent and ongoing experiments with radiation-hardened FPGA.

Performance of a Prototype Track-Finding Processor for the Level-1 Trigger of the CMS Endcap Muon System

D. Acosta, A. Madorsky, B. Scurlock, S.M. Wang, University of Florida
A. Atamanchuk, V. Golovtsov, B. Razmyslovich, St. Petersberg Nuclear Physics Institute

Abstract:

We report on the development and performance of a prototype track-finding processor for the Level-1 trigger of the CMS endcap muon system. The processor links track segments identified in the cathode-strip chambers of the endcap muon system into complete three-dimensional tracks. It then measures the transverse momentum of the best track candidates from the sagitta induced by the magnetic bending. The processor logic for the prototype is implemented in high-density FPGAs and SRAM memory. It receives approximately 3 gigabytes of data every second from a custom backplane operating at 280 MHz. Test results of the prototype are consistent with expectation.

Summary:

The prototype track-finding processor links track segments from individual cathode-strip chambers in the overlap and endcap regions of the CMS muon system into complete tracks. The overlap region is the region that the barrel and endcap muon systems overlap. The processor calculates the transverse momentum (Pt) of the track from the sagitta induced by the magnetic bending, and reports the highest quality tracks to the Level-1 Global Muon Trigger. Each processor handles information from a 60-degree sector in azimuth only.

The processor is pipelined at the LHC bunch crossing rate of 40 MHz. Approximately 500 bits of information from the track segments are sent into the processor every crossing, and the overall latency is 400 ns. The processor consists of a Bunch Crossing Analyser, Extrapolation units, Track Assembly units, a Final Selection unit, and an Assignment unit.

The Bunch Crossing Analyzer (BCA) gathers tracks segments in a window of at least two bunch crossings for the processor to analyze. This feature is important because the barrel muon trigger sends two muons from each chamber in the overlap region to the endcap muon track-finder over consecutive bunch crossings, and the bunch crossing assignment to the track segments of both muon systems is not 100% accurate.

An Extrapolation unit (EU) takes the three-dimensional spatial information from two track segments in different stations, and tests if they are compatible with a muon originating from the nominal collision vertex with a curvature consistent with the magnetic bending in that region. All possible extrapolation categories are performed in parallel to minimize trigger latency. Intermediate results on the extrapolations are shared amongst some EUs to resolve the ambiguity in the association of the azimuth and polar hits when there are two track segments in a same chamber.

A Track Assembly unit (TAU) links successful extrapolations into complete tracks. One TAU performs the linkings for the overlap region, and two TAUs for the endcap region. The Final Selection Unit (FSU) gathers the information from the TAUs, cancels redundant tracks, and forwards the three best distinct tracks to the Assignment Unit (AU).

The AU determines the azimuth and polar coordinates, Pt, sign, and the overall quality for each of the identified muon tracks. The muon Pt is measured using the azimuth angles of the track segments measured in two or three stations. A more accurate Pt measurement for low Pt muons is achieved with the three-station measurement.

Each processor delivers up to three best muon candidates to the Endcap Muon Sorter, which forwards the four best muon candidates to the Level-1 Global Muon Trigger.

The track-finding processor is implemented on a 13-layer 9U VME board. The trigger algorithms of the processor are fully programmable as the BCA, EU, and FSU logic is implemented in high-density Field-Programmable-Gate-Arrays (FPGA) from the Xilinx Virtex family. The TAU and AU are implemented in static RAM (SRAM) memory.

Some tests were performed on the prototype. The measured latency agrees with our estimation. The output from the logic algorithms are consistent with those from our simulation of the prototype. We have also measured the maximum clock rate that the processor can be driven.

First-Level End-Cap Muon Trigger System for ATLAS

K. Hasuko, T. Kobayashi, T. Niki, D. Toya, Y. Katori (University of Tokyo)
O. Sasaki, M. Ikeno, T.K. Ohska (High Energy Accelerator Research Organization KEK),
C. Fukunaga, H. Kano (Tokyo Metropolitan University),
H. Sakamoto, S. Nishida (Kyoto University),
H. Kurashige and R. Ichimiya (Kobe University)

Abstract:

We present the first-level end-cap muon trigger system for ATLAS. The system has the main tasks which are to identify bunch crossings and to make trigger decisions for high transverse-momentum muon candidates. It is being developed under requirements on trigger electronics: e.g. trigger rate, latency, acceptable number of tracks, etc. Such the requirements, trigger scheme, and overview of trigger logic are shown in this presentation. Details of the logic are given in the following presentation.

Summary:

The first-level (LVL1) muon trigger system consists of synchronous pipelined processors running at the bunch-crossing rate of 40 MHz. Its main tasks are to identify bunch crossings and to make trigger decisions for high transverse-momentum (Pt) muon candidates. It has to be operated with Pt threshold in the rage of 6-35 GeV. The trigger rate is required to be limited up to 100 kHz at a high luminosity. The latency of trigger decisions at front-end electronics is required to be less than 2.5 us, including 0.5 us for contingency.

High-Pt muons are identified from Resistive Plate Chambers (RPCs) and Thin Gap Chambers (TGCs) in the barrel and end-caps respectively. The ATLAS has air-core toroidal magnets creating magnetic fields for muon detection. A muon is bent in the fields and the information on its charge and momentum is extracted from the deviation of the bending path with respect to the non-bending projection toward the interaction point.

The TGCs with totally about 320K channels are arranged in seven layers (one triplet and two doublets) in each side. A hit signal is read out in r and phi independently. A muon track is identified by requiring coincidence criteria for hits in layers. A track satisfying 3-out-of-4 coincidence in both doublets is labeled as a low-Pt track. If the track also satisfies 2-out-of-3 (1-out-of-2) in a triplet for r (phi), it is labeled as a high-Pt track. The end-cap region is divided into totally 144 trigger sectors. The two highest-Pt tracks should be selected in each trigger sector.

This trigger system consists of four parts, which we call Patch Panel (PP), Low Pt (or Slave Board; SLB), High Pt and Sector Logic (SL).

At first, PPs receive digitized TGC signals to identify the bunch crossing, adjust signal timing and construct trigger segmentation. SLBs follow the PPs to perform coincidence operations for low-Pt tracks.

The results of SLBs are sent to High-Pt Boards (HPBs) to be combined for high-Pt tracks for r and phi separately. The information on r and phi is sent to SL performing r-phi coincidence and final track selection. The results are sent to the rest of LVL1 trigger system to be combined with the information on barrel muon and calorimeter systems. A trigger signal is finally generated and distributed to the front-end readout electronics. All chamber hits are read out from pipeline-clocked buffers on SLBs with event information.

This system also has functionalities to set up various parameters on detectors and trigger logic. These functionalities are totally controlled from outside.

The core logics in PP, SLB and HPB are implemented with full-custom ASICs. SL is implemented with FPGAs so that the r-phi coincidence is fully programmable. This provides the required range of Pt thresholds. The total latency of the end-cap system is less than 2 us, satisfying the requirement.

We will explain the system overview in this presentation and details of the ASICs are given in the other. These two presentations will complete the explanation of the muon end-cap trigger system.

DILOGIC-2 A SPARSE DATA SCAN READOUT PROCESSOR FOR THE HMPID DETECTOR OF ALICE

H. Witters, IMEC vzw, 3001 Leuven, Belgium (witters@imec.be)
J.C. Santiard, CERN, Geneva, Switzerland (jean-claude.santiard@cern.ch)
Paolo Martinengo, CERN, Geneva, Switzerland (paolo.martinengo@cern.ch)
For the ALICE collaboration

Abstract:

Processing of analog information are always spoiled by additional DC level and noise given by the sensors or their additional readout electronic. The Dilogic-2 ASIC circuit has been developed in a 0.7um n-well CMOS technology to process the data given by Analog to Digital Converters, in order to eliminate the empty channels, to subtract the base line (pedestal) and store locally the true analog information.

Summary:

The Dilogic-2 can handle up to 64 channels by group of 16, 32, 48 or 64 channels. At the present time, the Gassiplex0.7-3 front-end analog circuit is used by group of 48 channels that are multiplexed on the same ADC. The processing has to be done in two steps, firstly pedestals and noise of each channels have to be measured and stored on the chip, then the normal operation can start, zeros will be eliminated and the on-chip memory will be loaded by true value information. The sparse data scan section is made of a digital comparator and a subtractor; the pedestal field has been limited to 8-bits while the data have 12-bits range. These two elements are fed on one side by the analog information and on the other side by the contents of two separate memories filled respectively for each channel by the chosen level of comparison (threshold) and the pedestal value. Calling PED(i) and SIG(i) the average and r.m.s. values of a pedestal distribution, the operating threshold of the channel (i) is defined as: TH(i) = PED(i) + N*SIG(i), where N is a selectable constant, usually =3.

Thresholds and pedestals are first measured and stored in a memory, for every channel; the channel address allows finding the right values of each channel during the processing. A BIT-MAP memory (64w x 16-bits) is filled with "1" for channels above threshold or "0" for channels below the threshold, while an analog data FIFO memory (512w x 18-bits) is loaded with the amplitude information (12-bits) and the address of the selected channels (6-bits). These two operations are performed in parallel at a clock speed of 10MHz. Each event readout is turned off by an End-Event word, which contains the number of good channels (7-bits) and the corresponding event number (11-bits). A presettable almost-full flag prevent over-writing the FIFO; an internal 4-bits controller has been implemented to perform the different front-end and back-end operations, particularly one, which is used to test the functionality of the chip by an outside processor. Finally, the Dilogic-2 can be daisy-chained to allow the readout of several hundreds of channels on the same bi-directional data bus at a maximum speed of 20MHz.

Timing, Trigger and Control distribution and dead-time control in ATLAS

Abstract:

The RD12 TTC system is the backbone for the timing, trigger and control distribution in ATLAS. The last developments of TTC modules as well as their use in ATLAS will be presented.

The strategy for the dead-time control of the experiment will also be presented.

Summary:

The ATLAS readout elements, such as the front-end electronics, the readout drivers (ROD) and possibly the readout buffers (ROB), need the bunch crossing signal (BC) and the level-1 accept signal (L1A). The Timing, Trigger and Control (TTC) system allows the timing and trigger signals to be distributed to the readout electronics elements. The timing signals comprise the LHC clock (BC) and the synchronisation signals (BCR, ECR). The trigger signals include the L1A, test and calibration triggers. The TTC allows the timing of these signals to be adjusted.

The ATLAS TTC system is based on the optical fan-out system developed within the framework of RD12 which allows signals to be distributed from one source to up to 1024 destinations. The system is partitionable and subdetectors can be running with the central ATLAS timing and trigger signals, or independently, with their specific timing and trigger signals. The TTC system receives the LHC 40 MHz clock (BC) and the ORBIT signal from the LHC, the L1A signal from the central trigger processor (CTP), and commands and data from either the CTP or subdetector-specific electronics. A proper encoding allows this information to be transmitted on a single optical link which is fanned out to up to 1024 destinations. At the receiving end, an ASIC decodes the incoming signal and makes available the BC clock, the L1A signal, the ECR and BCR signals, the L1ID and BCID and the user commands and data. Provision is made to adjust the timing of all the signals. The way the TTC system will be used in different subdetectors depends on the specific requirements of each of them. Most of the sub-systems will use more than one partition to allow concurrent running of different parts of the detector in different trigger modes during commissioning or calibration periods.

In ATLAS, the TTC system will be used in different ways:

- In normal running, each TTC partition receives its clock from the LHC and the L1A from the CTP. The BCR is derived from the LHC ORBIT signal. After each L1A, an 8-bit trigger type is forwarded to the destinations as well as (optionally) a 24-bit event ID. The trigger type is formed in the CTP and contains information on what gave rise to an L1A, while the 24-bit event ID is formed in the TTC VME interface (TTCvi). The TTC system can also transmit specific subdetector data and commands without introducing dead time, e.g. test pulses when there are no bunches (LHC gap), front-end parameters (e.g. delay values).

- During commissioning and for test and calibration runs, triggers can be injected locally in each TTC partition.

The ATLAS front-end electronics and readout systems contain many levels of buffering. Information may be lost at any of a number stages of the readout chain if buffers become saturated. Different strategies can be adopted to handle this situation, the two extreme ones being:

- introduce deadtime to avoid uncontrolled information loss;

- accept information loss and build a readout system able to accept incomplete events and possible loss of synchronization.

The first of these strategies has been chosen and it has been decided to introduce deadtime in the Central Trigger Processor in order to:

- easily control and monitor the deadtime of the experiment;

- have a relatively simple and safe readout system relying on the presence of data for every event;

- simplify the front-end electronics systems by imposing an upper limit on the event rate and a minimum time between consecutive events.

Custom chips developed for the trigger/readout system of the ATLAS end-cap muon chambers

H.Kano, C.Fukunaga, Tokyo Metropolitan University,
M.Ikeno, O.Sasaki, T.K.Ohska, KEK (National Organization for high energy accelerator physics),
R.Ichimiya, H.Kurashige, Kobe University,
S.Nishida, H.Sakamoto, Kyoto University,
K.Hasuko, Y.Katori, T.Kobayashi, T.Niki, and D.Toya, University of Tokyo

Abstract:

Three custom ASICs are now being developed for the trigger/readout system of the ATLAS end-cap muon chambers. Each chip is the master component in three out of four subparts of the system. Beside the standard circuitry as an ATLAS subsystem, several implementations have been devised in each chip, which are required from various physical and boundary conditions as an electronics system for the end-cap muon chambers. We discuss the implementation of the level-1 muon identification logic as well as these customarily developed data handling technology

Summary:

The trigger/data acquisition (TDAQ) system for the muon end-cap chamber of ATLAS (TGC) is required to be divided into several partitions. This requirement comes from the structure and characteristics of the TGC as a sub-detector of ATLAS. The partitions are installed just on either the detector surface or top of it. All signals are passed through these partitions of so-called Patch-panel, Low-Pt and Hi-Pt in turn to an upper stream.

We have developed three custom ASICs, each of which contains almost all functionality of a partition. By making ASICs for these partitions, we intended to simplify and lighten the overall electronics system. In this system TGC output is used to produce the ATLAS level-1 muon trigger, we must make a trigger generation logic with minimum latency. Thus we also expect to shorten the latency by implementing the trigger logic into ASICs.

The TGC trigger logic uses signals from three sets of total seven TGC layers, which are called triplet, middle-doublet and pivot-doublet from inside to outside. We identify a muon track with these three layers. In the first step we try to find muon with hit signals of both doublets of the pivot and middle. If a signal sequence passes this check, it is labeled as a low-Pt muon track. A check for Hi-Pt is followed using signals of the triplet and the Low-Pt output.

The TGC signals are input at first to the patch panel in which the patch panel ASIC converts the level from LVDS to TTL and adjusts the signal timing in sub-nanosecond precision with a variable delay accomplished by a DLL circuit. The chip also makes synchronization of the TGC signal with own bunch crossing signal.

TGC signals processed in the patch panel are relayed to the Low-Pt. The hit information of signals for relevant TGC layers are made matching with a coincidence matrix embedded in the ASIC. This ASIC contains also the readout system of the TGC data beside the trigger logic that consists of the standard pipeline and derandomizer buffer.

The Hi-Pt system accepts trigger signals produced by the Low-Pt and makes own muon identification with more-or-less the same algorithm with the Low-Pt ASICs. Each Hi-Pt chip recognizes up to six high-Pt tracks. Contrary to the Low-Pt system, the output signal of the Hi-Pt must be transferred over 80 m for further processes. The transfer is done with an optical link with the high speed serial transmission protocol (G-link). In order to reduce data volume to be transferred, we applied a zero suppression mechanism and send the information of max. two highest Pt tracks for the next trigger processing. In principle we can achieve this with two consecutive primary encoding logic clock by clock. Instead we have developed a quick method to select two highest track within a clock. This encoding logic contributes to both reduction of latency and data volume on the G-link.

In the presentation we explain in detail the functionality and necessity of each chip from physical volume, space and latency point of view. The evaluation of the chips must be presented through analyses of both simulation and actual measurement.

Readout system for the CMS RPC Muon Trigger

Krzysztof Kierzkowski a), Ignacy M. Kudla a), Esko Pietarinen b), Michal Pietrusilski a), Krzysztof Pozniak c)
a) Warsaw University, Institute of Experimental Physics,
b) Univ.of Helsinki Fac.of Science, Helsinki Institute of Physics HIP,
c) Warsaw University of Technology, Institute of Electronics Systems

Abstract:

The CMS detector will have a dedicated subdetector (RPC chambers) to identify muons, measure their transverse momenta pt, and determine the bunch crossing from which they originate. Trigger algorithm is based on muon track search and classification in raw data from the RPC chambers. Trigger system can be built in the control room (far away from detector) where all trigger data are concentrated. Dedicated synchronous compression/decompression algorithm is used to sent all data for each bunch crossing via optical links. Readout system uses the same data as Trigger system and will be placed in Trigger Rack. The idea of readout system and its limitations are discussed. Paper includes description of prototype boards and test results on synchronous CERN test beam.

Summary:

Very low rate of the RPC chamber data enables to use a synchronous compression/decompression data algorithm to transfer only the non zero RPC data from the detector to the control room. Original structure of the data is restored from the string of frames received through data link with additional latency on the control room side. Zero suppression included in synchronous compression scheme is the base of RPC readout system.

Structure of readout system is based on results of theoretical analysis performed for station ME1/1( highest level of rate) with regard of own noise 100Hz/cm2 and zero suppression algorithm realized by LMUXes. Assumed, that 48 links are read and losses of trigger efficiency can not exceed 1%.

All electronic boards of readout system are placed in trigger crates and joint from oneself by local bus. Single module of readout system serves 40 optical links and cooperates with one RDPM. Maximum size of event sent to RDPM reaches about 1kB, instead average prospective size of event attains about 300 bytes. Both sizes are considerably less than 2kB page size fixed for CMS experiment and large margin of safety is warranted. Large number of links forced division of system on two functional parts:

- Slave Readout Board ( SRB): compressed data stream from optical links derandomizes synchronously to trigger experiment ( L1Accept). One SRB serves 8 optical links. All SRB work simultaneously,

- Master Readout Board (MRB): in two stages passes concentration of data stored in buffer memories of SLBs: within crates in first phase and for both crates in second phase. First phase is passed by both MRBs simultaneously, instead in second phase MRB possessing DDU interface executes of final data concentration and make these data available to RDPM.

Prototype of the readout system has been realized in Altera CPLD device (10K series) in 1999 and will be (was) tested on synchronous test beam at CERN.

Description of the Slave Readout (SR) and Master Readout (MR) algorithms were realized in AHDL. Slave Readout test board covers two SR modules working in parallel. The input signals of compressed data stream may be fed by two ways (electrically, by front connectors or optically, through the interface of fibre optic link). The Master Readout test board may work autonomously (has internal clock and requires external trigger signal) or co-operates with TTC circuit (additionally stores event number and bunch crossing number). The event packet, stored in event data buffer, is accessible via VME interface (for computer reading system) and standardized DDU interface (via PCI). The Readout test system assumes nominal parameters for CMS RPC trigger and works with a nominal clock 40 MHz (data transmission from Slave boards to Master board via internal bus is performed with 20 MHz).

Study of LVDS Serial Links for the ATLAS Level-1 Calorimeter Trigger

G.Anagnostou, P.Bright-Thomas, J.Garvey, R.Staley, W.Stokes, S.Talbot, P.Watkins, A.Watson
University of Birmingham, Birmingham, UK

R.Achenbach, P.Hanke, D.Husmann, M.Keller, E.-E.Kluge, J.Krause, K.Mahboubi, R.Megele, K.Meier, U.Pfeiffer, V.Schatz, K.Schmitt, C.Schumacher, B.Stelzer, O.Stelzer, P.Stock, E.Ulses
University of Heidelberg, Heidelberg, Germany

B.Bauss, K.Jakobs, U.Schaefer, J.Thomas
University of Mainz, Mainz, Germany

E.Eisenhandler, W.R.Gibson, M.P.J.Landon
Queen Mary and Westfield College, London, UK

B.M.Barnett, I.P.Brawn, J.Edwards, C.N.P.Gee, A.R.Gillman, R.Hatley, K.Jayananda, V.J.O.Perera, A.A.Shah, T.P.Shah
Rutherford Appleton Laboratory, Chilton, Didcot, UK

C.Bohm, M.Engstrom, S.Hellman, S.B.Silverstein
University of Stockholm, Stockholm, Sweden

Abstract:

This paper presents an evaluation of the proposed LVDS serial data transmission scheme for the ATLAS level-1 calorimeter trigger. Approximately 7000 high-bandwidth links are required to carry data into the level-1 processors from the preprocessor crates. National Semiconductor's Bus LVDS serialiser/deserialiser chipsets offer low power consumption at low cost and synchronous data transmission with minimal latency. Test systems have been built to measure real-time bit error rates using pseudo-random binary sequences. Results show that acceptable error rates better than 10^-13 per link can be achieved through compact cable connector assemblies over distances up to 20m.

Summary:

The ATLAS level-1 calorimeter trigger requires approximately 7000 high-bandwidth serial links to transfer data from the preprocessor into the algorithmic processor systems. Each processor module must receive data in excess of 4 Gbyte/s over these links, with minimal latency and a bit error rate (BER) better than 10^-10 for each link.

It was originally proposed to use HP G-link chipsets, which have performed well in tests, but do lead to a very high power density on the processor modules. This high power dissipation would require serious attention to module and crate cooling. LVDS links offer much lower power consumption, and the National Bus LVDS serialiser/deserialiser chipsets DS92LV1021/DSLV1210 etc. are easily interfaced to the trigger system while transmitting data synchronously with minimal latency.

Three separate test systems were produced. These involved up to eight channels in parallel, and measured BERs over electrical links using various cable types with lengths from 10m to 20m. Test systems were designed to transmit and check pseudo-random and repetitive data patterns in real-time in order to achieve the statistics required for measurements of very low BERs.

Several types of cable and connector were also evaluated for use within the ATLAS environment. The processor modules will share data via a high-speed backplane, and the LVDS links will be connected through this backplane in order to allow easy installation and replacement of modules. Compact cable assemblies are needed because of the high channel count per module: up to 96 LVDS channels per module are required and each 9U processor module requires up to 830 backplane pins.

The final installation within ATLAS requires inter-crate links over distances of 10m to 15m, and a low BER is crucial for these links in order to minimise false triggers. For minimum latency, only error detection, not correction, is possible. To minimise the error rates, the cable assemblies being considered require some form of equalisation for the attenuation at high frequencies, as the raw data rate on each link is 480 Mbit/s. Both active and passive pre-compensation techniques at the transmitter have been investigated. BERs better than 10^-13 per link have been achieved with cable lengths from 10m to 20m even with simple and straightforward L-R equalisation.

Experience showed that use of these parts was not straightforward, operating as they are at the limit of their specified data rate. The causes of power supply noise must be kept to the minimum, and board layout is critical. In particular, it is important to ensure that the transmitter clock has a low level of jitter. However the problems encountered have been understood and solutions found.

In conclusion, the LVDS links form a viable scheme for transfer of large volumes of data, having the advantages of low latency, low power and low cost. They also offer high-density connectivity, which is essential for compact cable plant. Prototype processors are now being designed that will incorporate a large number of such links.

Test results of the ALICE SDD electronic readout prototypes

G. Mazza[INFNTo], G. Alberici[INFNTo], G. Anelli[CERN], G.C Bonazzola[UniTo],
D. Cavagnino[UniTo], P.G. Cerello[INFNTo], P. De Remigis[INFNTo],
D. Falchieri[INFNBo], A. Gabrielli[INFNBo], E. Gandolfi[INFNBo],
P. Giubellino[INFNTo], M. Masetti[INFNBo], L.M. Montano[INFNTo],
D. Nouais[INFNTo], A. Rivetti[CERN][UniTo], F. Tosello[INFNTo],
A. Werbrouck[UniTo], R. Wheadon[INFNTo]
for the ALICE collaboration

Institutes :
[INFNTo]        INFN sezione di Torino, Italy
[INFNBo]        INFN sezione di Bologna, Italy
[UniTo]         Universita` di Torino, Italy
[CERN]          CERN, Geneve, Switzerland

Abstract:

The first prototypes of the front-end electronic of the ALICE silicon drift detectors has been designed and tested. The integrated circuits have been designed using state-of-the-art technologies and, for the analog parts, with radiation-tolerant design techniques. In this paper the test results of the building blocks of the PASCAL chip and the first prototype of the AMBRA chip are presented. The prototypes fully respect the ALICE requirements; owing to the use of deep-submicron technologies together with radiation-tolerant layout techniques, the prototypes have shown a tolerance to a radiation dose much higher than the one foreseen for the ALICE environment.

Summary:

The design of the readout electronic for the ALICE silicon drift detector is a very challenging task, due on one side to the huge amount of data produced by those detectors ( 256 10-bit words for each detector anode, in the case of the ALICE SDDs ) and on the other hand to the stringent constraints in term of space, power consumption and radiation hardeness. The chosen architecture is based on 2 integrated circuit, PASCAL and AMBRA. It works in two different phases : during the acquisition phase the detector signal is amplified and stored into a fast analogue memory; when the trigger signal validates the data, the readout phase starts and the analogue informations in the memory are converted by an A/D converter and transferred into a digital multi-event buffer. All the analogue functions ( amplification, storage and conversion ) are embedded in a single chip ( PASCAL ) while the digital event buffer plus most of the control logic are on a separate chip ( AMBRA ). The analogue memory is of the write-voltage read-voltage type; it uses MOS capacitors as storage elements in order to save space. The intrinsec MOS capacitor non-linearity limits the dynamic range to about 1.5 volts over a 2.5 power supply. The A/D converter is of the switched-capacitor, successive approximation type; the 10 bit resolution is obtained by an 8 bit main DAC followed by a 2 bit secondary DAC with direct coupling. Prototypes of the analogue memory and the A/D converter in a commercial 0.25 um technology with radiation tolerant design techniques have been designed and tested. The results show that both prototypes fully satisfy the ALICE requirements in terms of performances and power consumption. Owing to the adopted radiation tolerant technique, the prototypes does not show any significant degradation after a total dose up to 10 Mrads. The first prototype of the PASCAL chip is currently under production. The first prototype of the AMBRA chip has been designed and tested in a 0.35 um technology. The chip fully satisfy the ALICE requirements; radiation test are ongoing in order to check the radiation tolerance of a fully digital deep submicron technology without radiation tolerant layout techniques.
 

Low Noise Amplifier

J.D. Schipper, NIKHEF R. Kluit,NIKHEF

Abstract:

As a design study for the LHC experiments a 'Low Noise Amplifier Shaper' for capacitive detectors is developed. This amplifier is designed in 0.6 um technology from AMS. The goal was to design an amplifier with a noise contribution of 250 electrons, a 12 electrons per pF contribution from the input capacitor and a relative high gain. A test chip with two versions of the amplifier, a 'radiation tolerant' (gate-around FET's) and a 'normal' version has been fabricated and is now under test. These designs and there characteristics, simulated and measured, will be compared and discussed.

Summary:

For the LHC experiments at CERN a 'Low Noise Amplifier Shaper' for the readout of Silicon Micro Strip detectors is developed. The goal for this 'Low Noise Amplifier Shaper' is to study an amplifier design with a relative high gain and an equivalent noise charge of 250 electrons, plus 12 electrons / pF detector capacity at the input. These noise requirements are based on a 150 u Silicon strip detector (12000/MIP). The design of the amplifier is based on the amplifier in the HELIX-128 chip developed for HERA-B. The principle of the circuit is a folded cascode. This scheme is used for two reasons: Speed and power supply (dynamic range). A test chip with two versions of the amplifier, a 'radiation tolerant' (gate-around FET's) and a 'normal' version has been fabricated and is now under test. The both versions are a not equal, caused by the size limitations of the 'gate around' N-FET's. In the 'normal' version of the circuit the input P-FET is connected with the source to ground. In the 'gate around' version the feedback FET must be a P-type FET. The fact that the gate for an N-FET must be a closed figure makes it impossible to realise a W/L ratio smaller then about 4. This has been implemented by redefining the DC levels of the amplifier. During the design phase the design has been simulated intensively to verify the functionality and the predicted noise figure.

Version            Simulated         Measured                  Tpeak                                  Gain Noise     Gain   Noise
Gate around     57 mV        1741 el.                         56 mV                                                    3235el.                22 nsec
Normal            29 mV        1956 el.                         38 mV                                                        2305el.                25 nsec

In the table above some preliminary results are given. The Gain and bandwidth are as expected, but the noise is higher as expected.

Single Event Upset measurements on the Resistive Plate Chambers Front-End chip for the Compact Muon Solenoid experiment

S. Altieri(1), G. Bruno(1), F. Loddo(2), A. Ranieri(2), P. Vitulo(1)
(1)Dipartimento di Fisica Nucleare e Teorica dell'Università di Pavia e I.N.F.N. Sezione di Pavia
(2)Dipartimento Interateneo dell'Università di Bari e I.N.F.N. Sezione di Bari

Abstract:

A measurement of irradiation damaging has been made on the analog front-end electronics of the RPC detector in the CMS experiment. The measurements were performed according to the estimated neutron fluence foreseen in the most irradiated area of the apparatus. The test results are shown, considering all the possible irradiation effects on the custom RPC front-end electronics, encouraging us on the use of the 0.8m Bi-CMOS technologies from AMS, chosen for such type of application.

Summary:

We report on the results of an irradiation test made at the Pavia 250 kW reactor in which some CMS RPCs 8 channels FE chips have been exposed to neutrons.

The Single Event Upset (SEU) rate has beeen measured as a function of the neutron fluence up to some units in 10e11 cm-2.

The Macroscopic Cross Section for SEU events induced by neutrons into the chips has been measured and results will be shown.

The neutron energy spectrum ranged from 0.4 eV to 10 MeV. The SEU rate has been measured to be 0.02 Hz/chip and the relative Macroscopic Cross Section to be around 1.1 x 10-5 cm-1.

No evidence of a sensible deviation from these numbers has been observed while integrating a neutron flux equivalent to what is expected in 10 years of running in almost all of the CMS muon regions.

Moreover other measurements made using more energetic neutron irradiation are also shown, together with the effects obtained on the off-the-shelf electronics mounted on the front-end board to control the analog RPC chip.

A Demonstrator for the ATLAS Level-1 Muon Trigger Interface to the Central Trigger Processor

A. Corre, N. Ellis, P. Farthouat, Y. Hasegawa, G. Schuler, C. Schwick, R. Spiwoks
CERN

Abstract:

The Level-1 Muon Trigger Interface (MUCTPI) to the Central Trigger Processor (CTP) receives trigger information from the detector- specific logic of the muon trigger. This information contains up to two muon-track candidates per sector. The MUCTPI combines the information of all sectors and calculates total multiplicity values for each of six pT thresholds. It avoids double counting of single muons by taking into account that some of the trigger sectors overlap. The MUCTPI sends the multiplicity values to the CTP which takes the final Level-1 decision. For every Level-1 Accept the MUCTPI sends region-of-interest information to the Level-2 trigger and event data to the data acquisition system. A demonstrator of the MUCTPI has been built which has the performance of the final system but uses a simplified algorithm for calculating the overlap. The functionality and the performance of the demonstrator are presented.

The Trigger Menu Handler for the ATLAS Level-1 Central Trigger Processor

N. Ellis, P. Farthouat, G. Schuler, R. Spiwoks
CERN

Abstract:

The role of the Central Trigger Processor (CTP) in the ATLAS Level-1 trigger is to combine information from the calorimeter and muon trigger processors, as well as from other sources, e.g. calibration triggers, and to make the final Level-1 decision. The information sent to the CTP consists of multiplicity values for a variety of pT thresholds, and of flags for ET thresholds. The algorithm used by the CTP to combine the different trigger inputs allows events to be selected on the basis of menus. Different trigger menus for different run conditions have to be considered. In order to provide sufficient flexibility and to fulfil the required low latency, the CTP will be implemented with look-up tables and programmable logic devices. The trigger menu handler is the tool that translates the human-readable trigger menu into the configuration files necessary for the hardware, stores several prepared configurations and down-loads them into the hardware on request. An automatic compiler for the trigger menu and a prototype of the trigger menu handler have been implemented.

Development of HERA-B high-pT level-0 trigger logic system

H.Riege, J.Schutt, R.van Staa
II Institut fur Experimentalphysik Universitat Hamburg, Germany

V.Popov
Institute for Theoretical and Experimental Physics, Moscow, Russia

Abstract:

High-pt trigger has been developed for the HERA-B fixed target experiment as complementary option to the basic trigger. It increases considerably the number of B mesons decay channels detectable by the experiment. The high-pt trigger performs fast and effective selection of particles with high transverse momenta. Trigger system includes three layers of gaseous chambers placed in the magnetic field with 19000 readout channels. Hit information is being transfered from the chambers to the trigger logic via high-speed optical link lines. Selection algorithm is performed by the dedicated logic electronics which allows to select O(107) events out of 1012combinations per second. Pretrigger logic consists of a number of sections. Selection capability of the pretrigger logic is on average 16 events from 192000 combinations each 96 ns (time interval between two consequent bunches). Various tests of hardware prototypes have been done. The commissioning of the high-pt trigger logic system is on-going.

Summary:

High-p t trigger has been proposed for the HERA-B fixed target experiment as complementary option to the basic trigger [1]. It increases considerably the number of B mesons decay channels detectable by the experiment and thus the physics program. The high-p t trigger performs fast and effective selection of charged particles with high transverse momenta.

The high-p t trigger provides preliminary selection ('pretrigger') of events and initiates Kalman filter procedure of the first level trigger. The selection procedure based on triple coincidences between signals coming from gaseous chambers. The high-p t pretrigger system organized using approximately 19000 detecting pads of different sizes distributed among three superlayers of chambers mounted in the magnet.

Challenging design of front-end electronics is done. Special low-mass twisted pairs cable has been developed to carry signals from the signal wires to the front-end cards. In order to reduce total amount of material in the fiducial volume of the detector these cables have no additional shield.

The front-end preamplifier cards are mounted on the edge of the detector fiducial area. They based upon the ASD-8 amplifier-shaper-discriminator ASIC [2].

A charged particle traversing the detector fires projective pads in three layers. Logical signals from front-end electronics is being transfered to the pretrigger logic system in serial form via high-speed optical link lines with data rate 800 Mbits/s. Dedicated logic electronics performes selection of 0(10 7 ) events out of a few 10 12 combinations per second. Several predefined coincidence combinations of fired pads are used to produce the pretrigger signal. The result is being transformed into a data stream of initial track parameters and transmitted to the appropriate first level trigger processors.

The high-p t trigger logic electronics is implemented in VME standard. The logic system has sectional structure and is composed of boards of two types - the Pretrigger Board and the Master Card. Each section consists of one Master Card and a number of pretrigger boards. Two processes are running asynchronously in every section - incoming data filtering procedure and serialization-encoding process. Output of the first process is the input for the second one. A pretrigger board fulfils filter procedure for raw input data in order to diminish the data rate to the level acceptable by the next process. Only that information which passed the test for coincidences is being passed to the next, serialization and encoding, procedure.

The master card acquires data from a group of pretrigger boards, completes pretrigger logic task, defines track parameters and sends messages to the appropriate FLT processors.

A pretrigger board accepts signals from 576 pads of six entire rows. Since the board serves entire rows of pads no readout overlapping occurs and no additional 're-mapping' modules are needed.

Selection capability of the pretrigger logic is on average 16 events from 192000 combinations each 96 ns (time interval between two consequent bunches).

The high-p t pretrigger latency is not more than 0:5 mu s.

The trigger logic has flexibility to the selection criteria - coincidence combinations can be easily reprogrammed.

In order to reduce pretrigger rate further optimization of selection algorithm is forseen in the master card. Important additional facilities for monitoring and testing are implemented in the pretrigger logic.

The high-p t trigger prototype has been developed and intensively tested in the HERA-B experiment environment. The first half of pretrigger logic system has been installed. The commissioning of the high-p t trigger system is going on. Some results obtained are presented. The perfomances of the system are discussed.

References

[1] E.Hartouni et al., DESY-PRC 95/01 (January 1995).

[2] F.M.Newcomer, IEEE Trans.Nucl.Sci, 40(1993) 630.

PERFORMANCE AND RADIATION TESTING OF A LOW NOISE SWITCHED CAPACITOR ARRAY FOR THE CMS ENDCAP MUON CHAMBERS

R.E. Breedon, B. Holbrook, Winston Ko, D. Mobley, P. Murray, S.M. Tripathi
University of California, Davis, CA 95616 USA

Abstract:

The 16-channel, 96-cell per channel switched capacitor array (SCA) ASIC developed for the cathode readout of the cathode strip chambers (CSC) in the CMS endcap muon system is ready for production. For the final full-sized prototype, the Address Decoder was re-designed and LVDS Receivers were incorporated into the chip package. Under precision testing, the chip exhibits excellent linearity within the 1V design range and very low cell-to-cell pedestal variation. Performance of the SCA during beam tests of a fully-instrumented chamber and results from radiation testing at a 63.3 MeV proton cyclotron will be presented.

Summary:

During the first-level trigger latency period of approximately 128 bunch crossings (3.2 us), signals from the front-end electronics of sub-detectors in CMS must be held in temporary storage before being passed to the DAQ system or rejected. The endcap muon system employs a switched capacitor array to allow full-wave sampling and storage of the precise cathode measurement before digitisation. This enables a higher level of control over pileup effects (baseline shift) than other pipeline options. The SCA supports random addressing and simultaneous reading and writing for deadtimeless operation.

A pulse on a strip of a CSC emerges from the preamp/shaper (Tpeak = 100 ns) and is split into two signals: one for the level-1 trigger, the other sampled by the SCA at 20 MHz. Eight samples of each pulse are saved in the SCA, the first 2-3 of which are taken before the pulse rise to establish the baseline. Sixteen cathode strip channels from each of the six layers in a muon station are connected to a front-end board (CFEB). Sixteen channels from one layer are handled by one SCA. Each channel has 96 capacitor cells; cells selected for readout are multiplexed within the SCA. As the SCA will be used also for the innermost ME1/1 chamber, a total of 16,632 CSCs will be required.

The final prototype SCA was fabricated in the AMI 0.8 um CWL process via submission to MOSIS. A custom test board provides the interface to a Tektronix Data Analysis System (DAS) 9200, which selects test voltages and provides SCA addresses. The design is optimised for a 1V input range, although pulses up to 3V may be handled with reduced accuracy. Operating at full speed, the RMS deviation from linearity over 0-1V is about 0.6%. There is remarkably low noise affecting the cell-to-cell pedestal variation: With a fixed input voltage, the RMS variation of output voltages over all capacitor cells is 0.05-0.06%.

For the final production design, we have incorporated LVDS receivers into the ASIC to conserve space on the CFEB and reduce noise. Thirty samples of the previous iteration were used to populate five CFEBs to instrument a full-sized CSC prototype for beam tests at CERN in September 1999. The SCA performed excellently and results from the cathode analysis will be presented.

We monitored samples of the production design while they were exposed to a 63.3 MeV proton beam. We will present threshold shift curves for both powered and unpowered irradiated chips. The performance of chips bench-tested after exposures of up to 100 krad was within tolerances of an unexposed part.

Instrumentation amplifiers and voltage controlled current sources for LHC cryogenic instrumentation

J. A. Agapito(3), F. M. Cardeira(2), J. Casas(1), A. P. Fernandes(2), F. J. Franco(3), P. Gomes(1), I. C. Goncalves(2), A. Hernandez Cachero(3), J. Lozano(3), M. A. Martin(3), J. G. Marques(2), A. Paz(3), A. J. G. Ramalho(2), M. A. Rodriguez Ruiz(1) and J. P. Santos(3).
1 CERN, LHC Division, Geneva, Switzerland.
2 Instituto Tecnol¢gico e Nuclear (ITN), Sacav‚m, Portugal.
3 Universidad Complutense (UCM), Electronics Dept., Madrid, Spain.

Abstract:

Two different topologies for the basic instrumentation amplifier have been studied. Both amplifier and current source circuits have been designed, constructed and tested under radiation. All radiation campaigns have been carried out in ITN (Portugal) research nuclear reactor. A new facility for neutron beam extraction has been constructed. On line measurements of the offset voltages, offset currents, closed loop gain, and bias currents have been performed on the two structures for two different operational amplifiers, OPA124 & TLE2071. A study of the influence of each individual parameters to the whole has been carried out. Three voltage controlled current sources have been made with every instrumentation amplifier. Three values of current for each set of amplifiers have been fixed, adjusted to the different ranges of measurement of the cold mass temperature sensor. On line measurements of the currents are presented as a function of neutron radiation. And finally on line measurements of commercial voltage references are presented as a function of radiation.

Summary:

The influence of neutron and gamma radiation on operational amplifiers parameters was studied and experiments in a nuclear reactor were performed and reported in LEB99. Those tests provided the necessary information to select the amplifier that exhibited a better radiation tolerance to the expected doses in LHC cryogenic system. None of the amplifiers were instrumentation operational amplifiers, to be used in the signal conditioners for the cold mass temperature measurement and control. We decided to analyze instrumentation amplifiers and current source circuits designed with single operational amplifiers using the characteristics obtained in last campaigns. Two different topologies for the basic instrumentation amplifier have been studied. Both amplifier and current source circuits have been designed, constructed and tested under radiation. All radiation campaigns have been carried out in ITN (Portugal) research nuclear reactor. A new facility for neutron beam extraction has been constructed so that the gamma radiation has been reduced and the neutron fluence maintained to a rate as to obtain the whole desired dose in 5 days, 12 hours work. On line measurements of the offset voltages, offset currents, closed loop gain, and bias currents have been performed on the two structures of instrumentation amplifiers for two different operational amplifiers, OPA124 & TLE2071. The radiation is monitored by mean of three photodiodes placed in the center and the two ends of the set of circuit boards.

A study of the influence of each individual parameters to the whole has been carried out. The open loop gain is severely affected by neutron radiation. The circuits under study exhibit a stable closed loop gain as long as the open loop gain is maintained over 100V/mV. When this is lower, the structure with 2 opamp's is less affected than the 3 opamp's circuit. There is also an increase of the common mode gain, which affects in the reduction of the CMRR. These is also more important in the 3 opamp's circuit because of its low CMRR even without radiation. On the other hand the circuit with 2 opamp's needs a restricted voltage sweep values for common mode input. The gain of the reference voltage input is 1 and no significant differences between both structures have been detected.

Both circuits are very sensitive to offset voltage deviations of their components. Input opamp's contribute most largely to the offset voltage of the whole amplifier than any other component. Thus the output offset voltage of the instrumentation amplifier is a function of the characteristics of the input amplifiers. The values of all the individual parameter are compared after radiation with those obtained before and presented in a plot.

Three voltage controlled current sources have been made with every instrumentation amplifier. Three values of current for each set of amplifiers have been fixed, adjusted to the different ranges of measurement of the cold mass temperature sensor. The influence of the deviation of the individual parameters does not affect in the same manner to these circuits as it does to the instrumentation amplifier. When the open loop gain decrease dramatically to a value of 10V/mV the current across the sensor deviates less than 0.2% of its nominal value.

On line measurements of the currents are presented as a function of neutron radiation. Finally on line measurements of commercial voltage references are presented as a function of radiation.

Development of Fluorocarbon Evaporative Cooling Recirculators and Controls for the ATLAS Pixel and Semiconductor Tracking Detectors

C. Bayer (Wuppertal), M. Bosteels (CERN), P. Bonneau (CERN), H. Burckhart (CERN), D. Cragg (RAL), R. English (RAL), G. Hallewell (RAL/CPPM), B. Hallgren (CERN), S. Kersten (Wuppertal), P. Kind (Wuppertal), K. Langedrag (Oslo), S. Lindsay (Melbourne), M. Merkel (CERN), S. Stapnes (Oslo), J. Thadome (Wuppertal), V. Vacek (CERN/Czech Technical University, Prague)

Abstract:

We report on the development of evaporative fluorocarbon cooling recirculators and their control systems for the ATLAS Pixel and Semiconductor Tracking (SCT) detectors. A prototype circulator uses a hermetic, oil-less compressor and C3F8 refrigerant. The mass flow rate to each circuit is individually tuned via feedback according to the circuit load variation, using dome-loaded pressure regulators in the liquid supply lines piloted with analog compressed air from DAC-driven voltage to pressure ("V2P") converters. Evaporated C3F8 exits each circuit through an analog air-piloted back-pressure regulator, which sets the circuit operating temperature. A hard-wired thermal interlock system automatically cuts power to individual silicon modules should their temperature exceed safe values.

All elements of the circulator and control system have been implemented in prototype form. Temperature, pressure and flow measurement in the circulation system uses standard ATLAS CanBus LMB ("Local Monitor Box") DAQ and CanBus interfaced DACs in a large (300 + channel) multi-drop Can network administered through a BridgeView user interface. Prototype 16 channel interlock modules have been tested.

The performance of the circulator under steady state, partial-load, and transient conditions is discussed and future developments are outlined.

Summary:

We report on the development of evaporative fluorocarbon cooling recirculators and their control systems for the ATLAS Pixel and Semiconductor Tracking (SCT) detectors.

The front-end electronics and silicon substrates of these detectors collectively dissipate around 50kW of heat, which must be removed from the ATLAS inner detector cavity through around 400 separate evaporative cooling circuits. For an operational lifetime of around 10 years in the high radiation field close to the LHC beams, the silicon substrates of these detectors must operate at a temperature below ~ -6 C, with only short warm-up periods each year for maintenance. Evaporative cooling is chosen since it offers minimal extra material in the tracker sensitive volume.

Following our studies of evaporatively-cooled Pixel and SCT thermo-structures (LEB 99), we have addressed the development of evaporative fluorocarbon recirculators and their control systems for use with per-fluoro-n-propane (C3F8) at an evaporation temperature (pressure) of ~-25 C (~1.7 bar abs).

A prototype circulator is centered around a hermetic, oil-less piston compressor operating at an aspiration pressure of ~ 1 bar abs and an output pressure of ~ 10 bar abs. Aspiration pressure is regulated via PID variation of the compressor motor speed from zero to 100%, based on the sensed pressure in an input buffer tank. High pressure C3F8 vapor is condensed and passed to the detectors in liquid form, with optional pre-cooling to a temperature of ~ -15 C.

Coolant liquid will be split into around 400 circuits in racks on the ATLAS service platforms. The mass flow rate to each circuit will be individually tuned via feedback according to the circuit load variation, using pressure regulators in the liquid supply lines. These regulators will operate in an inaccessible, high radiation, magnetic field environment, and will be dome-loaded, using analog compressed air delivered from DAC-driven voltage to pressure ("V2P") converters.

Evaporated C3F8 will exit each circuit through an analog air-piloted dome-loaded back-pressure regulator, which will determine the boiling pressure, and hence the operating temperature. Such individual temperature control is impossible in a parallel flow liquid cooling system.

A hard-wired thermal interlock system will automatically cut power to individual silicon modules should their temperature exceed safe values for any reason.

All elements of the circulator and control system have been implemented in prototype form. Temperature, pressure and flow measurement in the circulation system uses standard ATLAS CanBus LMB ("Local Monitor Box") DAQ and CanBus interfaced DACs in a large (300 + channel) multi-drop Can network administered through a BridgeView user interface. Prototype 16 channel interlock modules have been tested in combination with NTC (negative temperature coefficient) sensors attached to dummy silicon modules.

The performance of the circulator and the temperature distribution on powered silicon modules under steady state, partial-load, interlock-trip, start-up and shutdown conditions will be discussed. Finally, aspects of a full-scale demonstrator with ~ 25 cooling circuits and 6kW cooling capacity, currently undergoing commissioning, will be outlined.

Design and test of a readout chip for LHCb

Niels van Bakel, Jo van den Brand, Hans Verkooijen (Free University of Amsterdam / NIKHEF Amsterdam)

Daniel Baumeister, Werner Hofmann, Karl-Tasso Knoepfle, Sven Loechner, Michael Schmelling, Edgar Sexauer (Max-Planck-Institute for Nuclear Physics, Heidelberg)

Martin Feuerstack-Raible (University of Heidelberg)

Neville Harnew, Nigel Smale (University of Oxford)

Abstract:

For the LHCb experiment a first prototype of a 128 channel analogue pipeline chip, named Beetle, has been developed and submitted in a standard 0.25 um CMOS process.

It integrates 128 channels with charge sensitive preamplifiers and shapers, whose outputs are sampled with 40 MHz into an analogue pipeline with a maximum latency of 160 sampling intervalls. A comparator behind the shaper provides a binary signal. The 128 channels can be multiplexed on either 4, 2 or 1 outputs. The bias settings are programmable and monitorable via a standard I2C-interface. The architecture of the chip is described as well as simulation and test results are presented.

Summary:

For the LHCb experiment a first prototype of a 128 channel analogue pipeline chip, named Beetle, has been developed and submitted. This readout chip will be made in a standard 0.25 um CMOS process.

It integrates 128 channels with low-noise charge-sensitive preamplifiers and shapers. The risetime of the shaped pulse is 25 ns wih a 25% remainder of the peak voltage after 25 ns. A comparator with configurable polarity and threshold level behind the shaper provides a binary signal. Four neighbouring comparator channels are being ORed and brought off chip via LVDS ports. Either the shaper or comparator output is sampled with the LHC-bunch-crossing frequency of 40 MHz into an analogue pipeline with a programmable maximum latency of 160 sampling intervalls and an integrated derandomizing buffer of 16 stages. The pipeline cells are realized as nmos gate-capacitances. The stored charge is read out via a charge-sensitive amplifier and multiplexed with 40 MHz onto 4 or 1 ports. In binary readout multiplexing runs at 80 MHz on two ports. Current drivers bring the serialized data off chip.

The chip works with a trigger rate of 1 MHz and performs readout deadtimeless in 900 ns. For testability and calibration purposes a charge injector with adjustable pulse height has been implemented. The bias settings and various other parameters are programmable and monitorable via a standard I2C-interface. The chip contains only synthesized logic which has been placed and routed automatically. The architecture of the chip is described in detail as well as simulation and test results are presented.

Overview of the ATLAS Policy on Radiation Tolerant Electronics

Martin Dentan, CERN & CEA-DAPNIA
Philippe Farthouat, CERN

Abstract:

ATLAS Sub-systems will integer a very large quantity and variety of electronics boards which will be submitted to radiations ranging from few krads and few 1E10 n/cm2 to few 10 Mrads and few 1E14 n/cm2, and to energetic particles capable of producing SEE (Single Event Effects). ATLAS Technical Coordination has developed in collaboration with the Sub-systems a new policy on radiation tolerant electronics. It provides guidelines for the pre-selection and for the qualification of all the commercial electronics components that will be used in ATLAS, in order to make sure they will resist to the foreseen radiation constraints. This paper summarises the main guidelines given in the ATLAS Policy on Radiation Tolerant Electronics, and the benefits resulting from this policy.

Summary:

The first goal of ATLAS Policy on Radiation Tolerant Electronics is the general safety of the ATLAS materials and of the persons working on the experiment. Therefore, all the components or systems on which radiation effects can cause fire or induce high and long term radioactivity levels are not allowed.

The second goal of this policy is to help ATLAS Sub-systems to build electronics complying with the level of radiation tolerance which is necessary for their system. This level must be determined by the Sub-systems. It represents the minimum doses and fluences which must be tolerated by the electronics, and the maximum rate of soft, hard or destructive Single Event Effects (SEE) acceptable for the electronics. This level of reliability must be maintained during the 10 years of operation of the experiment. This can be obtained by qualifying ASICs developed with a radiation-hard technology that complies with the radiation tolerance required for 10 years of operation, or by selecting and qualifying standard electronics components (COTS) that comply with the radiation tolerance required for 10 years of operation, or by selecting less radiation tolerant COTS and making sure that it will be possible to replace them if necessary after their expected lifetime.

The third goal of this policy is to help Sub-systems to build electronics within the foreseen schedule. Therefore, it includes a strategy for pre-selection, qualification and purchase of components which is built with the aim of reducing procurement risks.

A MIXED SIGNAL ASIC FOR THE SILICON DRIFT DETECTORS OF THE ALICE EXPERIMENT IN A 0.25 UM CMOS

A. Rivetti (1,2), G. Anelli(1), F. Anghinolfi(1), G. Mazza,(2) P. Jarron(1)
(1)CERN, CH-1211 Geneva 23, Switzerland
(2)INFN, Sezione di Torino, Via Pietro Giuria 1, 10125, Torino, Italy

Abstract:

A mixed signal integrated circuit developed for the read-out of Silicon Drift Detectors (SDDs) is presented.

The chip contains 32 channels and 16 ADCs. Each channel is made of an amplifier and an analog pipeline with 256 cells. One ADC is shared by two adjacent channels. The circuit is optimized to match the specifications of the SDDs of the ALICE experiment, where large dynamic range and low power consumption are key issues. The input noise is calculated to be 200 e- rms for an input capacitance of 3pF and a detector dark current of 10nA. The power consumption is 5mW/channel.

Summary:

Silicon Drift Detectors offer the advantage of a two-dimensional position measurement while requiring a very low amount of processing electronics. These detectors are well suited for experiments in which a very high particle density is coupled with a relatively low event rate, as is the case of heavy-ion experiments. For example, SDDs are used in the two intermediate layers of the Internal Tracking System (ITS) of the ALICE experiment. The constraints on material budget, power consumption and noise make the design of the front-end electronics for the SDDs in ALICE particularly challenging. In fact, in order to reach the required resolution (30 um in both coordinates) the noise should be limited below 250 e- rms. The maximum power consumption (including also the digitization of the data) must be kept below 5mW/channel. The electronics is DC coupled to the sensor and the baseline has to be stabilized against variations of the detector leakage current. Input signals up to 8 mips have to be correctly processed by the front-end.

We have developed an ASIC which is able to meet all of the previous requirements. The chip provides amplification of the input signal, temporary storage of the analog data in a 256 cells pipeline and a 10 bit analog-to-digital conversion.

All the operations are controlled by a digital unit implemented on chip. The chip has been implemented in a commercial 0.25 um CMOS technology, using radiation tolerant layout approach. This should guarantee immunity to radiation damage at least up to a total dose of 10 Mrad (SiO2).

The amplifier uses a charge integrating scheme, with pole-zero cancellation and CR-RC^2 shaping. The coupling between the preamplifier and the shaper is made with the help of an error amplifier. In this way, the value of the baseline can be regulated via an external voltage and is completely insensitive to the variations of the detector leakage current. The power consumption of the amplifier (including the output buffer) is 1.7mW/channel and the maximum signal swing is 1.4 Volt. The gain of the amplifier for a delta input signal is 170mV/mip.

In the analog memory gate capacitors are used in order to reach a satisfactory circuit density. A voltage-write voltage-read scheme has been selected to minimize the effect of the voltage dependence of these capacitors.

The 10 bits analog-to-digital converters is implemented using a switched capacitor charge redistribution scheme. Since in this circuit the capacitor linearity is crucial metal to metal capacitor are used. The ADC is able to perform a full conversion cycle (sampling +digitization) in 500 ns. Due to layout constraints one ADC is used to convert the data of two adjacent channels.

For the analog memory and the ADC we used preliminary circuits developed as analogue demonstrators in the framework of the CERN RD49 program. The tests performed on these building blocks have shown very satisfactory results; on both parts a resolution of 10 bits with very low power consumption (3.5mW/channel for the memory and 1mW/channelfor the ADC) has been measured.

Implementation of a Serial Protocol for the Liquid Argon Atlas Calorimeter (SPAC)

F.Hubaut, B.Laforge, O.Le Dortz, D.Martin, Ph. Schwemling
LPNHE Paris

Abstract:

The Serial Protocol for the Atlas Calorimeter (SPAC) has been designed to provide the loading and reading of all parameters of the front-end boards of the ATLAS Liquid Argon Calorimeter.

This single master / multiple slaves serial protocol is designed to be transmitted optically and electrically, at up to 10 Mbits/s, and enables broadcast or individual transfers from the master to one or a set of slaves.

Some test results about the SPAC performance and its implementation within the ATLAS framework will be presented.

Summary:

The Serial Protocol for the Atlas Calorimeter (SPAC) has been designed to provide the loading and reading of all parameters of the front-end boards of the ATLAS Liquid Argon Calorimeter.

This single master / multiple slaves serial protocol is designed to be transmitted optically and electrically, at up to 10 Mbits/s, and enables broadcast or individual transfers from the master to one or a set of slaves.

One SPAC network, controlling one front-end crate, includes one master module in the counting room and slave ASICs, made in DMILL technology and housed on each front-end board. The slaves integrate a I2C master interface and a parallel interface to be exploited by the boards.

Some test results about the SPAC performance and its implementation within the ATLAS framework will be presented.

A FAST BINARY FRONT-END IMPLEMENTED IN A 0.25 UM CMOS TECHNOLOGY USING A NOVEL CURRENT-MODE TECHNIQUE

D. Moraes(1), F. Anghinolfi(1), P. Deval(2), P. Jarron(1), A. Rivetti(1).
(1)CERN, CH-1211 Geneva 23, Switzerland.
(2)MEAD Microlectronics S.A., Venoge 7, 1025 St. Sulpice, Switzerland.

Abstract:

A prototype of an IC has been developed with a very fast and low noise preamplifier, using a 0.25micron CMOS technology. The prototype contains a low- and high gain version of the preamplifier. It was designed to have an input impedance below 10 Ohms and an peaking time of 10ns at an input capacitance of 20pF. The low gain version was specially developed to be used on the Cathode Pad Chambers of the LHCb Muon System, where a very low threshold combined with high speed and low noise are required in order to obtain high efficiency and good time resolution.

Summary:

The investigation of the characteristics of state-of-the-art deep submicron CMOS technologies show that analogue circuits with very good performance can be designed using these processes. In particular, deep submicron technologies are well suited for the design of binary front-end systems. In these applications, in fact, the limitation on the dynamic range imposed by the squeezed power supplies (typically 2.5 V for a 0.25 um CMOS) is not a primary issue.

Current-mode architectures can be a viable alternative to the more conventional voltage-mode ones to build very fast circuits Therefore, combining current-mode techniques with the use of deep submicron technologies provides the opportunity of building analog circuits with very good speed/power consumption trade-off.

In high energy physics applications the radiation tolerance of the circuits is often a critical point. The thin gate oxide inherent in deep submicron CMOS technologies, combined with the systematic use of enclosed layout transistors and guard-rings, has shown to provide very good resistance to total dose radiation damage. However, the use of enclosed geometries imposes constraints on the aspect ratio of MOS transistors. This is of particular concern in the design of current mirrors, which are fundamental building blocks in current mode circuits.

To investigate the above issues we have designed two current mode binary circuits. The circuits use the same topology, but the input stage has been optimised to match two different input capacitance (10pF and 20pF respectively), having in mind two different applications:

1) The front-end of medium capacitance silicon detectors (for the 10pF version)

2) The front-end of the Cathode Pad Chamber of the LHCb muon system (for the 20 pF version).

Each processing channel is formed by a current mode preamplifier and a two-stage discriminator. The first step of the discrimination is carried out in the current domain, whilst the second stage is a conventional voltage mode differential pair. In fact, to interface the chip with the outside circuitry is more practical to have the signals in the voltage domain. LVDS signals are hence provided at the output of each channel., The input impedance is very low (less than 10 Ohms) , owing to the novel current mode feedbackintroduced in the preamplifier.

The gain of the preamplifier is different for the two versions. A current gain of 6 has been chosen for the low gain version ( 20pF input capacitance). For the high gain version (input capacitance 10 pF) a gain of 64 has been selected.

The noise has been calculated to be 600 electrons rms for the high gain version (14 ns peaking time) and 1100 electrons for the low gain version (10 ns peaking time)

The power consumption is 3.5 mW and 10 mW for the high and low gain version, respectively.

A prototype of 2x2 mm^2 containing four channels of each type has just been submitted for fabrication. Extensive tests results are expected to be presented at the conference.

Developments for Rdaiation Hard Silicon Detectors by Defect Engineering - Results of the CERN RD48 (ROSE) Collaboration

Gunnar Lindstroem (cospokesman of RD48) on behalf of the RD48 collaboration

Abstract:

The success of the Oxygen enrichment of FZ silicon as a highly powerful defect engineering technique and its optimization with various commercial manufacturers are reported. Major focus is on the changes of the effective doping concentration (depletion voltage). Other aspects (reverse current, charge collection) are covered too. Diode characteristics of test pad- and LHC-strip detectors are compared. The RD48 model for the dependence of radiation effects on fluence, temperature and operational time is verified; projections to operational scenarios for main LHC experiments demonstrate vital benefits. Present microscopic understanding of damage effects including differences caused by charged and neutral hadrons are discussed too.

Summary:

The RD48(ROSE) collaboration has succeeded to develop radiation hard silicon detectors, capable to withstand the harsh hadron fluences in the tracking areas of LHC experiments. In order to reach this objective, a defect engineering approach was employed resulting in the development of Oxygen enriched FZ silicon (DOFZ). Systematic measure- ments have been carried out with various standard and oxygenated material in fluence ranges between 5e10 and 5e14 cm-2 (1MeV-n- equivalent). The defect generation on a microscopic scale was also studied, gaining invaluable insight in the underlying physics. Only macroscopic effects of the O-enrichment with direct relevance for LHC detector application are summarized in the following:

* Leakage current: the damage parameter alpha is material independent (no dependence on conduction type, crystal orientation, resistivity and impurities) and is scaling almost ideally with NIEL (non ionizing energy loss) independent of particle type and energy.

* Effective doping concentration (depletion voltage): the damage induced change in Neff is considerably improved after charged hadron irradiation. Short term annealing (10 days at RT) leads to about 3 times less increase in the depletion voltage as compared to standard silicon and the reverse annealing even shows an unexpected saturation at higher fluences. This amounts to a decrease in the Neff-change by as much as a factor of 4 and is also connected with a 5 times larger annealing time, thus offering an additional safety margin for detectors kept at room temperature during maintenance. To present knowledge these improvements hold only for proton irradiation (in accordance with existing checks for pions), for neutrons a beneficial effect was observed by using low resistivity material (e.g. 1 kOhmcm instead of the standard 5 kOhmcm silicon decreases the change in Neff after 2e14 n/cm² by a factor of about 2).

* Charge collection efficiency: while the measurements for Neff have mostly been performed on test pad diodes using C/V methods, these results have been checked both with test and silicon strip detectors measuring the charge collection efficiency as function of bias voltage. The results show a good agreement between both techniques also revealing that the systematic analysis done with test diodes can reliably be used for strip detectors.

* Model description for macroscopic damage effects and projection to LHC: For the above described effects the "Hamburg-model" had been applied for the O-enriched silicon detectors and relevant parameters were extracted. The application of the model to LHC operational scenarios indicates that by using oxygenated instead of standard silicon the lifetime of e.g. the sensors in the B-layer of the ATLAS pixel detector would be extended to almost 10 years. In fact, the ATLAS pixel group had meanwhile decided to use the RD48 developed technique.

* Optimization of the DOFZ technique: So far feasibility studies with various companies have shown that the oxygenation of the silicon bulk by prolonged tempering after normal oxidation (diffusion of O from the SiO2-Si interface) does not result in any problem. Optimization experiments are presently carried out with O-diffusion in the range between 6 days at 1200C and 8 hours at 1150C.

HDMC: An object-oriented approach to hardware diagnostics

V.Schatz, C.Schumacher University of Heidelberg, Heidelberg, Germany
M.P.J.Landon Queen Mary and Westfield College, London, UK

Abstract:

A software package has been developed, which provides direct access to hardware components for testing, diagnostics or monitoring purposes. It provides a library of C++ classes for hardware access and a corresponding graphical user interface. Special care has been taken to make this package convenient to use, flexible and extensible. The software has been successfully used in development of components for the pre-processor system of the ATLAS level-1 calorimeter trigger, but it could be useful for any system requiring direct diagnostic access to VME based hardware.

Summary:

Developing electronics involves a fair amount of testing, where direct access to hardware via a computer is required. In addition to low-level test tools like oscilloscopes or logic analysers higher level diagnostic facilties are essential for more complex tests. This includes software to access the developed hardware in an extensive and easy-to-use way to perform diagnostics and monitoring of individual or complete groups of components. Similar functionality is required for later integration in extended hardware and software frameworks.

The presented software package, called HDMC (Hardware Diagnostics, Monitoring and Control), addresses these needs. It provides a library of components for accessing hardware objects like registers, memories or FPGAs on VME modules or within devices not directly accessible to VME, but located on a VME module. It's also possible to access a VME bus via a network connection in a client/server configuration. A graphical user interface based on this library provides hardware access without requiring special knowledge about software development. The library can also be used for more direct access based on compiled or scripting programming languages for testing or integration into other software environments.

HDMC is implemented as a set of C++ classes, representing hardware components in a common framework. This is used to provide common ways to access similar components, to transmit data between components and to handle them in a uniform way. A simple and clean interface for direct hardware access is provided as well as a more abstract one for access through a graphical user interface. Register descriptions are loaded from human-readable configuration files in such a way that a lot of hardware development can be made without the necessity to recompile the software.

The graphical user interface allows construction, manipulation and access to VME modules and other components in a convenient and uniform way. Access to hardware configurations can be built using the interface and changed at run-time. There is also a plot and histogram component and facilities to present special views of hardware configurations like modules and crates.

HDMC supports a variety of UNIX platforms like Linux, Solaris and HP-UX, For VME access several VME single-board computer are supported, running Linux or LynxOS. Platform support could be extended to Windows without major rewrite and addition of other bus systems like CompactPCI is possible without change in the remaining framework or components.

For development of HDMC an open-source process is used. Source code and documentation is publicly available in the internet and it is open for contributions of any interested party.

The software package has proven to be a useful and reliable tool for diagnosing hardware. It has been used for the pre-processor system of the ATLAS level-1 calorimeter system, whose current development activities are based on a flexible VME test system, but other systems in need for a software tool for hardware diagnostic could also benefit from the HDMC software.

Specification and Simulation of ALICE DAQ System

Giovanna Di Marzo Serugendo, CERN / Predrag Jovanovic, School of Physics and Astronomy, University of Birmingham / Pierre Vande Vyvre, CERN / Orlando Villalobos Baillie, School of Physics and Astronomy, University of Birmingham
for the ALICE Collaboration.

Abstract:

The Trigger and Data Acquisition System of the ALICE experiment has been designed to support the high bandwidth expected during the LHC heavy ion run.  A model of this system has been developed. The goal of this model is twofold. First, it allows to verify that the system-level design is consistent and behaves according to the requirements.  Second, it is used to evaluate the theoretical system performances using the measurements done on sub-systems prototypes. This paper presents the specification and simulation of a model of the ALICE DAQ system using a commercial tool (Foresight). This specification is then executed to simulate the system behaviour.

Summary:

The ALICE Trigger and Data Acquisition System (DAQ) system is required to support an aggregate event building bandwidth of up to 2.5 GByte/s and a storage capability of up to 1.25 GByte/s to mass storage. The system must also be able to combine different types of physics events: a slow rate of central triggers generating the largest fraction of the total data volume, together with faster rates of dielectron and dimuon events.

The ALICE DAQ system has been decomposed in a set of hardware and software components. The detailed system design is going on in parallel with the development of prototypes of these components. We wish to verify this design in order to check that it can reach the expected behaviour and the target performances.

However, such a complex system happens to be difficult to verify manually, since there is no corresponding mathematical description. A tool that enables to define a model of the system, and to perform its verification is therefore an extremely valuable help.

This paper presents the formal specification and simulation of the DAQ of the ALICE experiment. The tool used is a modelling and simulation tool, called Foresight.  It allows to specify the system by successive decomposition.  It enables to describe the system in an abstract manner in order to focus on the functionality and also to refine it by adding the details of its implementation.

The Foresight specification is made of hierarchical data flow diagrams, finite state diagrams, and pieces of a procedural modelling language. The specification provides a unambiguous description of the system. The semantics of the specification provides a model of the system whose behaviour is very close to the behaviour of the system.  The verification process is performed during the simulation.  It demonstrates the functional correctness of the system.

The Foresight simulation consists of the execution of the specification.

It offers debugging functions like animation of diagrams, breakpoints, and monitor windows.  The simulation is used to evaluate the theoretical system performances using the measurements done on sub-systems prototypes.  It also enables to perform some analysis such as the system sensitivity to some key parameters.  One can also explore other algorithms, and new architectures.  This is useful when he final architecture has not yet been defined (as it is the case for ALICE), since it helps to compare architectures or implementation choices.

The current ALICE specification describes the functionality of the whole experiment and of the major sub-systems: Trigger, Trigger Detectors, Tracking Detectors, DAQ, Permanent Data Storage.

Till now focus has been given to the trigger system. The trigger system performance (trigger types rates) has been simulated under different conditions (different buffer sizes for the detectors, and different bandwidth to the DAQ). This has shown the upper limit of each trigger type rate.

Future work will focus on the DAQ performances and the investigation of different architectural choices. The model will be enriched with a more detailed specification of some existing DAQ components such as the ALICE Detector Data Link (DDL) or the DAQ software framework (DATE).

The nonlinear behaviour of p-i-n diode in high intense radiation fields

P.K.Skorobogatov, A.S.Artamonov, B.A.Ahabaev Specialized electronic systems

Abstract:

The dependence of p-i-n diode ionizing current amplitude vs dose rate is defined using twodimensional software simulation. It is shown that analyzed dependence becomes nonlinear beginning with relatively low dose rates near 107 rad(Si)/s. This effect is connected with the modulation of p-i-n diode intrinsic region by irradiation. As a result the distribution of electric field becomes non-uniform that leads to decrease of excess carriers collection. The ionizing current pulse form becomes more prolonged because of delayed component contribution. It is necessary to take into account when p-i-n diode is used as dose rate dosimeter.

The p-i-n diodes are widely used for the measurements of ionizing radiation dose rates. The high electric field in its intrinsic region provides the full and fast excess carriers collection. As a results the ionizing current pulse waveform repeats the ionization pulse with the accuracy of several nanoseconds. To investigate the p-i-n diode possibilities at high dose rates the original software simulator "DIO-DE-2D" [1] was used. The "DIODE-2D" is the fundamental system of equations two-dimensional solver. It takes into account carrier generation, recombination and transport, optical effects, carrier's lifetime and mobility dependencies on excess carriers and doping impurity concentrations. The typical p-i-n diode with 380 micrometers intrinsic region width under 300 V reverse bias was investigated. The simulation of p-i-n diode structure have shown that linear dependence between dose rate and ionizing current is valid only at relatively low dose rates up to 107 rad(Si)/s. In the field of high dose rates this dependence becomes non-linear and ionizing current increases more slowly than dose rate. The reason of non-linearity is connected with the modulation of p-i-n diode intrinsic region by excess carriers. Because of low level of initial carriers concentration the modulation takes place at relatively low dose rates. As a result of modulation the distribution of electric field in the intrinsic region becomes non-uniform that leads to decrease of excess carriers collection. The behavior of p-i-n diode becomes similar to that of ordinary p-n junction with prompt and delayed components of ionizing current. The prompt component repeats the dose rate waveform. The delayed component is connected with the excess carriers collection from regions with low electric fields. As a result the ionizing current pulse form becomes more prolonged and dose not repeat the dose rate waveform. The numerical results were confirmed by experimental measurement of p-i-n diode ionizing reaction in wide range of ionizing radiation dose rates. The non-linear character of behavior and prolonged reaction must be taken into account when p-i-n diode is used as dose rate dosimeter.

References [1]. The "DIODE-2D" Software Simulator Manual Guide, SPELS, 1995.

Use of external resistor to prevent radiation induced latch-up in commercial CMOS IC's

P.K.Skorobogatov, A.Y.Nikiforov, A.A.Demidov Specialized electronic systems

Abstract:

It is shown that in the case of external resistor usage to prevent radiation induced latch-up in commercial CMOS IC's we have the increase of IC recovery time up to tens of microsecond due to deep saturation of parasitic bipolar transistors. Under numerical calculations it was found that there is an optimal value of external resistor that provides the minimal recovery time of IC.

The usage of commercial CMOS IC's in radiation environment is restricted by the possibility of its latch-up behaviour under irradiation. The external resistor in power supply circuit is a well-known way to prevent latch-up. This method is found on the restriction of IC power supply current to the level lower than latch-up holding current. The experiments were shown however that in this case we unfortunately have the increase of IC recovery time up to tens of microsecond. Under numerical calculations it was found that this effect is connected with deep saturation of parasitic bipolar transistors on the external resistance. It was found that there is an optimal value of external resistor that provides the minimal recovery time of IC. In the case of low resistance the large recovery time is connected with deep level of parasitic transistors saturation. In the case of high resistance value the recovery time is defined by well-substrate p-n junction ionizing current delayed component voltage drop on the external resistance that increases with resistance growth. For CMOS IC's under investigation the optimal value was near 80 Ohm. This effect must be taken into account when commercial CMOS IC's are used in radiation environment.

THE ATLAS LIQUID ARGON CALORIMETERS READ OUT DRIVERS

Julie Prast for the ATLAS Collaboration

Abstract:

The Read Out Driver (ROD) for the Liquid Argon calorimeters front-end electronics of the ATLAS detector is described. Those ROD modules are designed for the ATLAS electromagnetic, hadronic end-cap and forward calorimeters. Each ROD module receives data from two Front-End Boards (FEB). The FEB amplifies, shapes, samples and stores the signal from 128 calorimeters cells at the frequency of the LHC (40 MHz). Then, the data are digitized and sent to the ROD modules for each Level-1 trigger (maximum rate of 100 kHz). These data are transmitted by two 32 bits data optical links. The principal function of the ROD is to reconstruct the precise energy and timing of each cell signal from the time samples. In addition, the ROD checks and histograms the data. The treated data are then sent towards the Read Out Buffers (ROB), according to a defined format, where they are stored.

A demonstrator system consisting of a mother board and several daughter boards Processing Units (PU), is under development. The goal of the demonstrator is to prove the feasibility of the project and serve as an intermediate step towards the construction of the final ROD module for the ATLAS experiment. The design of the prototypes are presented here.

The mother board is a full size 9U VME module able to carry four daughter boards. It allows all the input/output connections with the FEB and ROB, the controls of the board and the VME interface. This board offers maximum modularity and allows the development and testing of different Processing Units (PU). Three PU are being studied. Two are designed with the Texas Instrument TMS320C6202 fixed point DSP, while the other one is designed with the Analog Devices 21160 floating point DSP. These PU present the same overall architecture. The example of the Analog Devices PU will be taken.

Each PU treats data from an half FEB (8 ADC). Each ADC digitizes signals from 8 calorimeters cells. Each channel is composed of five 12-bit samples. These FEB data enter an FPGA at the speed of 40 MHz They are parallelized, parity checked and formatted before being buffered into the internal FIFO of the FPGA. This FIFO is connected to the external memory bus of the DSP. Once the DSP finishes the processing of the event, the results are formatted according to the ROB format and then put into a FIFO. This output FIFO is read by the mother board Output Controller.

The PU also contains a communication port, through which all the control of the board is done. It uses the DSP link ports to communicate with the mother board VME interface. It is also used to send monitoring or debugging information to the local CPU. All the communications between the DSP and its peripheral are done by Direct Memory Access (DMA), thus being transparent for the DSP core.

Results for the different PU will be presented and compared (functioning, performance, DSP algorithm). The first tests have shown that the demonstrator board meets the ATLAS requirements in term of bandwidth and accuracy, although the DSP used are not the next generation of DSP foreseen for the final version of the board.

Performance of a High Voltage Power Supply incorporating a Ceramic Transfomer

Yoshiaki Shikaze(Department of Physics, Faculty of Science, University of Tokyo), Masatosi Imori(ICEPP, University of Tokyo), Hideyuki Fuke(Department of Physics, Faculty of Science, University of Tokyo) Hiroshi Matsumoto(ICEPP, University of Tokyo), Takasi Taniguchi(National Laboratory for High Energy Physics(KEK))

Abstract:

This paper describes the performance of a high-voltage power supply incorporating a ceramic transformer. Since the transformer doesn't include any magnetic material the power supply can be operated under a strong magnetic field. In the article, the efficiency of the power supply is studied against various parameters. It was found that the efficiency reaches more than 50 percent when zero-voltage switching was realized. From a voltage source of 2V, the power supply can supply 3000V at a 21 megohm load. A voltage source of 5V is enough to supply 4000V at the same load.

Summary:

This paper describes the performance of a power supply incorporating a ceramic transformer which uses the piezoelectric effect to generate high voltage. By using the ceramic transformer and a air-core coil, the power supply can produce high voltage under a strong magnetic field. The output high voltage is stabilized by feedback. A feedback loop includes divider resistors, an error amplifier, a voltage controlled oscillator (VCO) and a driver circuit. An output high voltage is produced by a Cockcroft-Walton (CW) circuit. The driver circuit generates a sinusoidal carrier the frequency of which is genertaed by the VCO. The driver circuit drives the transformer, applying the sinusoidal carrier. The amplitude ratio of the transformer has dependence on the frequency, which is utilized by the feedback.

The transformer shows a sharp resonance in the vicinity of 120kHz. From a view point of efficiency, it is favorable to drive the transformer at efficient frequencies ranging from 120kHz to 124kHz. When 3V is supplied to the driver circuit, the power supply produces 1500--3000V at a 21 megohm load with the above efficient range of frequency. The driver circuit includes FETs and the air-core coils. The inductance of the coil and the input capacitance of the transformer composes a oscillation circuit, by which the sinusoidal carrier is produced. The inductace is adjusted so that the frequency of the oscillation can be in the efficient range. So the FETs are switched while the voltage applied to the FETs is zero. The zero-voltage switching of the FET was realized, which contributed to improving the efficiency.

On-resistance of the FET is important for the efficiency. Yet the efficiency depends on characteristics of the FET intricately. Several kinds of FET are tested. For each FET, many plots on the efficiency were drawn against various parameters such as output high voltage, frequency, inductance, and capacitors of CW circuit. The efficiency increases as the frequency moves to the resonant frequency, being saturated at the level of more than 50 percent at the frequency in the efficient range with zero-voltage switching. When the voltage supplied to the driver circuit is 2V, 3V and 4V and output high voltage is 2000V at a load of 21 megohm, the current to the driver circuit is about 200mA,130mA and 110mA, respectively.

The amplitude of the sinusoidal carrier is about three times the input voltage to the driver circuit. The output voltage of the transformer is furthermore multiplied by about six times in the CW circuit. When the voltage to the driver circiut is 1.5V, the maximum output high voltage of the power supply reaches 3000V at a load of 18 megohm. It can be seen that the amplitude ratio of the transformer reaches a hundred at the resonance frequency. So Feeding 5V to the driver circuit is enough to supply 4000V. Hence the power supply could be available for any of Thin Gap Chamber, Monitored Distributed Tube (MDT) and Resisted Plate Chamber (RPC) of ATLAS experiments.

The performance of a Pre-Processor Multi-Chip Module for the ATLAS Level-1 Trigger

R.Achenbach, P.Hanke, D.Husmann, M.Keller, E.-E.Kluge, J.Krause, K.Mahboubi, R.Megele, K.Meier, U.Pfeiffer, V.Schatz, K.Schmitt, C.Schumacher, B.Stelzer, O.Stelzer, P.Stock, E.Ulses
University of Heidelberg, Heidelberg, Germany

Abstract:

We have built and tested a mixed signal Multi-Chip Module (MCM) to be used in the Pre-Processor of the ATLAS Level-1 Calorimeter Trigger. The MCM performs high speed digital signal processing on four analogue trigger input signals. Results are transmitted serially at a serial data rate of 800 MBd. Nine chips of different technologies are mounted on a four layer copper substrate. Analogue-to-digital converters and serialiser chips are the major consumers of electrical power on the MCM, which amounts to 7.5 Watts for all dies. Special cut-out areas are used to dissipate heat directly to the copper substrate. In this paper we report on design criteria, chosen MCM technology for substrate and die mounting, experiences with the MCM operation and measurement results.

Summary: The ATLAS experiment requires a highly selective trigger system with optimal efficiency. The event selection at ATLAS will be achieved by a three level trigger system. The first level trigger (Level-1) is a fast pipelined system for the selection of rare physics processes. It achieves a rate reduction from the 40 MHz LHC bunch crossing rate down to the Level-1 accept rate of 75 kHz (100 kHz upgrade). This is done by searching for trigger objects within a total Level-1 trigger latency of 2.0 us. The number of presummed analogue calorimeter signals which are used as input to the Level-1 trigger is about 7200.

Regarding the timing constraints and the large number of analogue signals, the Level-1 trigger needs a hard-wired front-end to perform fast signal processing on all analogue input signals in parallel. This system, which is referred to as Pre-Processor system, provides the input data for the Level-1 trigger algorithms and it performs the readout of data on which the Level-1 trigger has based its decision.

The motivation behind the usage of a Multi-Chip Module (MCM) technology inside the Pre-Processor system is the high number of channels, which must be processed by each Pre-Processor board (64 signals), and the high number of semiconductor devices per printed circuit board. Hence, a MCM technology is essential for the Pre-Processor system to realize a compact system architecture. MCMs represent a technique whereby bare dies and their interconnections are combined inside a single package. The MCM contains both analogue and digital devices. In total it comprises nine dies: two dual FADCs, four Front-End ASICs performing the pre-processing, one multipurpose level conversion ASIC (Finco), and two high speed gigabit transmitter dies from Hewlett Packard (Glink) running at 1.6 GBd.

The design process of the MCM multi-layer structure is based on an industrial available production technique for high density printed circuit boards. This process, called TwinFlex, is characterized by its usage of plasma drilled Micro-Vias for interconnection between layers and its combination of small feature sizes and prices.

One of the most challenging tasks in the MCM design is the thermal management. The increasing of the packaging density and the use of high power dies leads to the exponential nature of component failure rates with temperature. Therefore the dies on the MCM need different thermal resistance from the chip to the case. This difference has been achieved by using a thermal cutout for the gigabit serial transmitter and thermal vias for the FADCs. The total power consumption of the MCM is about 7.5 W.

We will present design criteria, chosen MCM technology for substrate and die mounting and experiences with the MCM operation. System measurements will demonstrate the performance of the Pre-Processor relying on this Multi-Chip Module technology.

Fiber Optic based readout for BTeV's Pixel Detector

Gustavo I. E. Cancelo*, Sergio Zimmermann*, Sergio Vergara**, Peter Denes*, Guilherme Cardoso*, Bob Downing*, Jeff Andresen* * Fermilab, **University of Puebla, Mexico

Abstract:

The current paper describes the design of BTeV's Fiber Optics Pixel Detector readout. The pixel detectors will be located as close as 6mm from the accelerator's beam into the vacuum pipe. The readout electronics will be located at about 6cm from the beam, imposing strong constrains regarding radiation, mass, power dissipation, vacuum and size. This paper includes an analysis of the convenience of using a fiber optic based readout versus alternative solutions. Since the current design will place several components in a high dose proton and gamma radiation environment the fiber optic based readout will need some radiation hardened custom components, which are here specified. Furthermore, test results on optoelectronic devices are provided along with future plans to complete the design.

Summary:

BTeV's pixel detector consists of 31 double-plane stations of about 100cm² of active detection area. These planes are perpendicular to the direction of the beam. The beam passes through the center of the plane formed by two halves as shown Figure 1. Since BTeV intends to use the pixel detector as part of the lowest level trigger system, one of the most important requirements is hit readout speed [1]. The primary goal is to achieve a data transfer rate high enough to sustain the hit readout rate generated at a luminosity of p/cm² and a bunch crossing (BCO) time of 132 ns at Fermilab's Tevatron. Furthermore, the required readout bandwidth must be achieved while keeping small power and mass budget. In particular, mass is very critical for the Pixel Detector, the most inner part of BTeV's detector where multiple scattering must be minimized.

A fiber optic based design, as proposed in this paper, is the technology that best adapts to BTeV's requirements. Every pixel plane will generate, in average, 4Gb/s of data. The pixel amplifier and discriminator chips, located underneath the pixel detectors will store that information. However, since the pixel detector is the primary component of BTeV's trigger, the data must be readout as soon as possible. A modular design is being proposed for the pixel detector electronics as shown in Figure 1. Every module is autonomous. It groups a certain number of Pixel amplifier/discriminator chips and the readout electronics to transfer the data from the pixel planes to the experiment's counting room. Furthermore, every module must allow for an incoming link to receive several commands to initialize and control the pixel devices and provide them with timing information (i.e. clocks).

The readout electronic serializes the data from the pixel chips into high speed serial links. A 1.06Gb/s link is being proposed based on a custom CHFET GaAs design[2]. This device has undergone functionality, BER and radiation tests. It has shown to be radiation resistant and SEU free. Several test results are provided in this paper. The serializer device has a built in VCSEL driver. VCSELs have proven to operate at very high speeds and be radiation resistant. Test results will be shown.

The control and timing link will have a fiber optic receiver to decode the signal coming from a PIN photodiode. The operative frequency is 53.4MHz. This device must also be radiation resistant. The specifications of this chip are completed. In order to reduce the number of fibers to minimize the total mass, the data and clock signals will be encoded together following a bi-phase encoding. A prototype board has been developed to qualify the bi-phase approach working together and generating a low jitter clock for the gigabit serializer. Performance results will be supplied.

Finally, two new developments are being worked out with a company in the optoelectronic business to generate a very small profile optical assembly for the VCSEL and PIN components, and a hermetic package to exit the accelerator's vacuum pipe. The semi-custom VCSEL and PIN assembly design will allow the Pixel Module to be connected and disconnected from the fiber, allowing the modules to be tested and assembled individually, decoupling the inherent module's yield from the optoelectronic issues. In order to reduce the number of points where the vacuum pipe is disrupted, he hermetic package will handle several fibers. The optimum number is still unknown, but decoupling the modules from the fibers is important to better track the problems and increase the overall yield by being able to change individual pieces.

REFERENCES: [1] BTeV: An Expression of Interest for a Heavy Quark Program at C0, BTeV collaboration, Fermilab, May 18, 1997. [2] Radiation Hard Gigabit Systems. Second Workshop on Optical Readout Technologies for ATLAS, Oxford, January 7-8 1999.

HIGH-SPEED COMPARATOR IC WITH LOW TIME DISPERSION

E.V.Atkin

Abstract:

The high-speed comparator for fast time reference is represented. It can be used as a leading edge discriminator or as a core for building constant fraction discriminator and can be useful for the development of time-of-flight systems.

It is manufactured with a bipolar process. Its main feature is a small time dispersion of output signal (200 ps) at the presence of a wide dynamic range of input signals (overdrives from 10 mV to 1V).

This paper describes the approach to the design of the new version of a low time dispersion comparator. The structure of such a comparator, features of schematics of its separate stages and its parameters are described.

Summary:

The paper reflects the results of the activities, being the continuation of the MEPhI group's efforts on developing precise timing discriminators [1].

The cost effective high-speed comparator IC for fast time reference is represented. It can be used as a leading edge discriminator or as a core for building constant fraction discriminator. It can be useful for the development of time-of-flight systems (such as ALICE TOF), providing a time reference accuracy at the order of tens of picoseconds.

It is manufactured on the basis of an application specific semicustom array with a bipolar process [2].

This paper describes the approach to the design of the new version of a low time dispersion comparator. The structure of such a comparator and its schematics were designed to make it a functional analog of the well-known IC AD96685 from Analog Devices.

The comparator contains three symmetrical differential stages and is added by the circuits of built-in hysteresis (from 0 to 4 mV) control and output signal logic variation. Its main peculiarity consists in the fact, that the small time dispersion of output signal (~200 ps) is specified for a wide dynamic range of input signals (overdrives from 10 mV to 1V) and for a temperature range from 0 to 70 °C. The propagation delays were defined with a 100 mV pulse.

The mentioned parameters were achieved at the expense of using: · non-standard differential stages built as current amps; · dynamic nonlinear loads, providing the compression of input signals.

Especial attention was paid to minimize the static errors and intrinsic noise of the comparator. The following table presents certain comparator parameters.

Parameter Value Units

Input bias current 20 max uA

Input offset current 2.0 max uA

Input offset voltage 2.0 max mV

Input voltage range ±2.5 V

Intrinsic input noise 1.0 rms mV

Outputs provide complementary digital signals fully compatible with ECL 10K logic families. The output signal logic variation is provided by applying a control potential to a separate IC pin.

Power consumption of the comparator does not exceed 150 mW at standard supply voltages of ±5V.

References

1P.Khlopkov et al. A discriminator PCB for precise timing signal generation. Third Workshop on Electronics for LHC experiments, London, Sept. 22-26, 1997, CERN/LHCC/97-60, p. 497-499.

2A.Goldsher et al. A semicustom array chip for creating high-speed front-end LSICs. Same as previous, p. 257-259.

A BiCMOS discriminator interface for the SPD

A. Diéguez, S. Bota Departament d'Electrònica, Sistemes d'Instrumentació i Comunicacions, Universitat de Barcelona, C/Martí Franquès, 1, E-08028, Barcelona. Spain

D. Gascón, L. Garrido Departament d'Estructura i Constituents de la Matèria, Universitat de Barcelona, C/Martí i Franques 1, E-08028 Barcelona. Spain.

M. Roselló Departament d'Electrònica, Enginyeria i Arquitectura La salle, Universitat Ramon Llull, Pg. Bonanova 8, E-08022, Barcelona. Spain.

Abstract:

A prototype chip for the analogue readout of the SPD in the LHCb Calorimeter is presented. The chip has been designed using the 0.8mm-BiCMOS technology of AMS and optimised for minimum size and maximum performance at the required frequency of operation in LHC experiments. It consists of a dual structure formed by two integrators, two track and hold circuits, two substractors, two comparators and a multiplexer. The die size occupied by one discriminator circuit is approximately 1720 mm x 330 mm.

Summary:

The microelectronic circuit designed is a pulse discriminator interface for the Scintillator Pad Detector (SPD) at the Electromagnetic Calorimeter (ECAL) at LHCb. It has to operate at the L0 trigger level of LHC (f=40MHz, T=25ns) to detect the signals from electrons at the SPD, discriminating the signal originated by photons (background). The signal entering the discriminator is originated at the SPD, transmitted through an optical fibre and amplified in a photomultiplier. The jitter of the input signal makes better to integrate it rather than consider its maximum value. So, the first block of the discriminator is an analogue integrator. On the other hand, because of the shape of the input signal, only its 83% is integrated in 25ns. This mandates the use of at least a dual architecture (two channels in each discriminator) in order to allow the substration in the current period of the 17% of the signal integrated in the previous one. A dual architecture avoids also to have dead time on integration. The integrated value to be substracted is stored in a track and hold. After the substraction, a comparator with tunable treshold gives a logic signal indicating an interesting event to be stored in the experiment. The last signal is finally multiplexed.

So, each channel of the discriminator comprises an integrator, a track and hold, a substractor and a comparator. The output of the discriminator is obtained through a final 2/1 differential multiplexer. In the prototype chip all blocks have been included separately and two different discriminators. Each one of these discriminators corresponds to two different integrator circuits. The circuit is fully differential in order to reduce noise effects. All the blocks in the circuit are biased between 2.5V and -2.5V, and polarisation currents are lower than 250mA in all blocks. The circuit has been implemented with the 0.8mm-BiCMOS technology of AMS in order to have the required frequency of operation. Because of the large number of channels to process (6000), the design has been optimised for minimum area. Each discriminator circuit, including the routing area and clock distribution is about 1720 mm x 330 mm.

It will be presented a detailed description of each block in the discriminator, as well as their functional behaviour and the final performance of the entire discriminator.

Grounding and Shielding of the ATLAS TRT

Martin Mandl for the TRT collaboration

Abstract:

This paper addresses practical considerations for the engineering of the grounding and shielding system of the ATLAS-TRT.

Summary:

A ground system serves three primary functions: personnel safety, equipment and facility protection, and electrical-noise reduction. Defining the potential of each conductive material to be within certain margins achieves safety. A proper signal reference system together with shielding of sensitive as well as noisy parts provide noise reduction. Defining the potential of the conductive structures and building a signal-reference system inside the TRT, can be chosen within two philosophies: either strongly connecting everything together or trying to control the currents which flow in the system. The first one yields the lowest impedance between any two points of the system, but simultaneously allows loops and shield currents to flow inside the system. The second approach allows to break these loops and to ban shield currents from intruding the system through carefully provided low-impedance paths.

Each ATLAS sub detector has to follow "The ATLAS Policy on Grounding and Power Distribution" which gives the following guidelines:

• [...] electrical isolation of all detector systems, [...]

• [...] floating low-voltage power supplies, [...]

• [...] floating high-voltage power supplies, [...]

• [...] data transmission, clock and trigger distribution through optical links
  or shielded twisted-pair cables, [...]

• [...] detector located inside a faraday cage. [...]

This negates the first philosophy at an intersystem level, but still allows it inside the sub detector. Only the final system will show all systematic effects which could not be predicted from a small prototype. Implementing provisions for both philosophies allows us to postpone the choice until more experience has been acquired. Therefore a way of realizing both approaches has been defined.

A data driven high-resolution Time-to-Digital Converter

J. Christiansen, A. Marchioro, P. Moreira, M. Mota, V. Ryjov CERN, CH-1211 Geneva, 23 Switzerland
S. Débieux Engineering School of Geneva, Microelectronics Lab, Geneva, Switzerland

Abstract:

A data driven multi-channel Time-to-Digital Converter (TDC) circuit with programmable resolution (25ps - 800ps binning) has been implemented in a 0.24um CMOS technology. An on-chip PLL is used for clock multiplication up to 320MHz from an external 40MHz reference. A 32 element Delay Locked Loop (DLL) performs time interpolation down to 97.5ps. Finally, finer time interpolation is obtained using an on-chip RC delay line. Time measurements are processed and buffered in a data driven architecture based on time tags. This results in a highly flexible triggered or non-triggered TDC which can be used in many different experiments.

Summary:

A highly flexible high resolution, multi-channel TDC has been built in a modern 0.24um CMOS technology. Its high flexibility enables it to be used in several LHC experiments: ALICE TOF detector, CMS muon drift chamber detector and LHCb outer tracker. The complete design containing more than 1 million transistors has been submitted for fabrication and will be fully characterized before LEB 2000.

The time digitization is based on a clock synchronous counter and a DLL with 32 delay elements both driven from an on-chip PLL.

An on-chip adjustable RC delay line spanning the "length" of a DLL delay cell is optionally used to further increase the time resolution. The RC delay line is divided into four segments each used to latch a time measurement. From these four measurements an interpolation with a resolution of 25ps can be obtained.

In low resolution modes ( 800ps - 100ps time binnig) 32 channels are available per TDC. In the high resolution mode four low resolution channels are controlled by the RC interpolator resulting in 8 channels.

The PLL and the DLL are self-calibrating being locked to the external reference clock. The RC delay line used in the high-resolution mode is to a high degree insensitive to the operating conditions (within +-20 deg.C) and only needs to be calibrated for process variations.

Individual channel buffers enable multiple time measurements to be performed with low dead time. The digitization of individual leading and/or trailing edges enables time over threshold measurements of signal amplitudes to be performed. Time measurements are written into four 256-deep latency buffers waiting to be serviced by a trigger-matching unit. The extraction of hits related to triggers are based on trigger time tags from an internal 16-deep trigger FIFO. Unique features of the data driven time tag based trigger matching is the fact that the trigger latency is not directly limited by the size of the latency buffers and that single hits can be matched to multiple triggers. Extracted measurements are written into a 256-deep readout FIFO waiting to be read out. Trigger matching can also be completely disabled whereby the latency buffers and the readout buffer works as simple FIFO's. Accepted time measurements can be read out via a 40MHz, 32 bit parallel bus for high rate applications or alternatively via a serial link.

Extensive error checking and monitoring is included in the TDC. Parity checks are applied throughout the data path to detect any malfunction caused by single event upsets. A JTAG interface is used to load programming parameters (~600bits) and access built-in test and verification features.

ATLANTIS - a modular, hybrid FPGA/CPU processor for the ATLAS Readout Systems

Christian Hinkelbein - Institute of Computer Science V, University of Mannheim, Germany Andreas Kugel - Institute of Computer Science V, University of Mannheim, Germany Reinhard Maenner - Institute of Computer Science V, University of Mannheim, Germany Matthias Mueller - Institute of Computer Science V, University of Mannheim, Germany Harald Simmler - Institute of Computer Science V, University of Mannheim, Germany Holger Singpiel - Institute of Computer Science V, University of Mannheim, Germany Lorne Levinson - Weizmann Institute of Science, Rehovot, Israel

Abstract:

ATLANTIS realizes a hybrid architecture comprising a standard PC platform plus different FPGA based modules for high performance I/O (AIB) and computing (ACB). CompactPCI provides the basic communication mechanism enhanced by a private bus. The system can be tailored to a specific application by selecting an appropriate combination of modules. Acceleration of computing intensive ATLAS LVL2 trigger tasks has been demonstrated with an ACB based system. The ATLAS RoD and RoB systems profit from the flexible and highly efficient AIB I/O architecture. Various high speed interface modules (S-Link/M-Link) are supported, allowing up to 28 links per CompactPCI crate.

Summary:

This paper introduces the hybrid FPGA/CPU based system ATLANTIS. Its utilization as a prototype system for investigating further ATLAS Readout Systems is described. The basic concept of ATLANTIS is to support flexibility and scalability on different levels. Due to this ATLANTIS is a modular system based on CompactPCI. Dedicated FPGA boards for computing (ACB) and I/O (AIB) plus a private backplane bus (AAB) for a data rate of up to 1 GB/s are part of the system. Programming of the FPGAs is done either with commercial VHDL tools or the C++ based HDL developed at Mannheim University. For a specific application a certain number and combination of ATLANTIS boards form the desired system. For investigating ATLAS Readout Systems one commercial host CPU along with up to 7 AIBs are used within a CompactPCI crate. Every AIB is able to carry up to four mezzanine I/O daughterboards. Two Xilinx VIRTEX(-E) FPGAs control the I/O ports. The nominal capacity of any of the four channels is 264 MB/s. Each AIB is equipped with 16 MByte SRAM controlled by the FPGAs. The two FPGAs of each AIB are connected both to the host CPU via the PCI bus and to every other AIB within one crate using the private bus. In the context of the ATLAS LVL2 trigger ATLANTIS has already shown its versatility and potential based on the ACB modules. Two further, high performance I/O applications in conjunction with the ATLAS Readout Systems utilizing the new AIB modules are presented in this paper: The use as a Readout Driver (RoD) and as a Readout Buffer (Rob Complex) prototype system. Both applications profit from the flexible and highly efficient ATLANTIS I/O architecture. The RoD acts as interface between detector and RoB. AIBs equipped with 2 SLinks/GLinks perform the I/O task with up to 160 MByte/s per link. Format conversion and zero-suppression is done "on the fly" by the FPGAs, prior to transmission. The AAB private bus is used for concentrating event data from different AIBs to one output port. The RoB Complex tasks are similar to the RoD tasks but more complex. Data fragments from a variable number of input links have to be assembled, temporarily stored and transmitted via a network interface upon request. A high speed buffer management is essential for this application and implemented on the AIB boards. The host CPU is used to steer the AIBs and to handle requests from the network. It may also provide additional computing power. To achieve a high density of links up to 4 M-Link interfaces can be used per AIB. Local control of the 4 input channels and collection of fragments per AIB help to decrease the frequency of control messages and data packets which significantly improves PCI bandwidth. Two ATLANTIS systems comprising ACB(s) and AAB modules plus a PC-compatible host CPU are available since autumn 1999. Also 4 M-Link modules are ready for use. Four AIBs are in manufacturing phase and expected to be available in June 2000.

Redundancy or GaAs ? Two different approaches to solve the problem of SEU (Single Event Upset) in a digital optical link optical

From SMU: Ryszard Stroynowski Bernard Dinkespiler Jingbo Ye Shouxuan Xie
From CPPM: Frederic Rethore
From ISN: Marie-Laure Andrieux Laurent Gallin-Martel
From KTH: Mark Pearce Johan Lundqvist Stefan Rydstrom

Abstract:

The fast digital optical links for the ATLAS Liquid Argon Calorimeter must survive in a high radiation environment with a total fluence of 2*1013 neutrons/cm2 and 800 Gy. The links based on Agilent Technologies -former HP- Glink chipset show a total dose radiation resistance to neutrons and gammas that would allow for 10 years of operation in the ATLAS detector. We have observed, however, an unacceptable rate of single event upsets (SEU) due to neutrons interacting in the silicon-based serializer. In order to solve this problem, we have developed two link systems. The first one - Dual-Glink-, is based on the principle of redundancy. Data are sent on two independent links. On the reception side, data are analyzed and error recovery is performed without dead time.

The second solution uses a GaAs serializer/deserializer chipset from TriQuint. This technology is intrinsically radiation hard. We expect a minimal number of SEU's and other radiation related problems. High speed of this chipset -2.5 Gb/s- allows for error recovery.

The design of the link, its performance in the laboratory environment and the results of the radiation tests will be presented for both systems.

Summary:

The ATLAS liquid argon calorimeter digital optical links are based on Agilent Technologies (former HP) Glink chipset. Although they show a total dose radiation resistance to neutrons and gammas that would allow for 10 years of operation in the ATLAS detector, they have an unacceptable rate of single event upsets due to neutrons interacting in the silicon based serializer. We developed a Dual-Glink system, composed of 2 independent links, each one sending the complete data set. On the reception side a smart switch realized in FPGA analyzes in real time the data streams from both links, detects errors and selects the link that is not affected by errors. The probability that an error occurs simultaneously on both links is negligible. The total latency of the switch is 20 clock cycles. This solution is more expensive than a simple link since all the hardware components are doubled.

In an attempt to make a cheaper solution, we also developed a digital optical link solution based on the recently available GaAs multiplexer/demultiplexer chipset TQ8123/8223 from TriQuint. The intrinsic radiation hardness of GaAs technology is expected to minimize the impact of radiation effects and of the single event upsets. Since the ATLAS LAr Calorimeter requires the 32 bit data transfer at 40 MHz, the very high speed of 2.5Gb/s provided by this chipset allows for sending the data twice over a single optical fiber. This permits an online error detection and error correction. The design of the link, its performance in the laboratory environment and the results of the radiation tests will be presented.

The Detector Control Unit: an ASIC for environmental monitoring in the CMS central tracker

Guido Magazzu' - INFN Sezione di Pisa
Alessandro Marchioro - CERN EP-MIC
Paulo Moreira - CERN EP-MIC

Abstract:

The readout system of the CMS central tracker performs several functions: readout of the data from the front-end ASICs, distribution of the timing and trigger signals, distribution and collection of the slow control and status information and collection of local environmental parameters. The DCU (Detector Control Unit) is an integrated circuit which monitors parameters such as the leakage current in the silicon detectors, local voltages and temperatures. All these measurements can be performed by one analog multiplexer followed by a A/D converter interfacing to the slow control system. Such functions could easily be performed by a number of commercial devices, but the constraints of radiation tolerance, low power and maximum integration lead us to design a special integrated circuit which will be here described.

Summary:

Silicon microstrip detectors, when exposed to the high level of radiations of the LHC, are subject to a number of damaging phenomena demanding a careful monitoring of their environmental conditions. To assure proper operation over the expected 10 years lifetime, one has to guarantee that the leakage currents in the microstrips do not exceed certain values and - to avoid reverse annealing phenomena - that the detector is kept at a conveniently low temperature during the whole lifetime. The vital quantities that one needs to monitor close to the silicon strip detector and to the front end modules are therefore the leakage currents of the silicon detectors in the range of 100uA to 10mA and the temperature of the detectors themselves (which can be fairly easily sensed through the utilization of appropriate thermistors) in the range -20 to 20 deg C with a precision of about one degree. Such quantities need to be read and logged with relatively low frequency, therefore a fast conversion time is not important. The hardware necessary for the monitoring of these quantities allows also to monitor other environmental parameters, for instance the local supply voltages, the temperature of the high density hybrid housing the front-end integrated circuits etc. The Detector Control Unit (DCU) perform all these functions in one single integrated circuit. This integrated circuit consists basically of a 12-bit A/D converter which uses a single slope architecture, preceded by an 8 input analog multiplexer. One input is reserved for an on-chip temperature sensor, which measures the temperature of the substrate onto which the chip is mounted, and seven other inputs which are available to measure voltages in the range -1.0 to +1.0 V (almost rail-to-rail). The A/D conversion time is ~ 1 ms and the analog reference to the A/D consists of an on-chip bandgap reference block. As the external temperature sensors are essentially resistors and the input of the DCU is capable of reading voltages, a temperature independent, stable current reference output is also made available from the chip. The DCU is interfaced to the tracker control system via a standard I2C port, through which the user can select one multiplexer input out of the 8 available, start a conversion in the A/D and read the conversion result. The DCU ASIC is designed in a commercial quarter micron technology using special layout techniques to enhance its radiation tolerance. The total chip area measures about 2.0 x 2.0 mm2, has 28 pins and the power consumption is estimated to be less than 50 mW. The digital part of the chip uses triple redundancy and voting to insure protection against SEU effects. To achieve almost rail-to-rail input compatibility, the analog circuitry uses some complementary solution based on double Nmos and Pmos transistors and has an automatic offset cancellation feature. The circuit has been submitted to fabrication and the measured results will be presented.

The Muon Pretrigger System of the HERA-B Experiment

M.Adams (Universitaet Dortmund), P.Bechtle (Universitaet Dortmund), P.Buchholz (Universitaet Dortmund), C.Cruse (Universitaet Dortmund), U.Husemann (Universitaet Dortmund), E.Klaus (Universitaet Dortmund), N.Koch (Universitaet Dortmund), M.Kolander (Universitaet Dortmund), I.Kolotaev (ITEP Moscow and Universitaet Dortmund), H.Riege (Universitaet Hamburg), J.Schuett (Universitaet Hamburg), B.Schwenninger (Universitaet Dortmund), R.van Staa (Universitaet Hamburg), D.Wegener (Universitaet Dortmund)

Abstract:

The muon pretrigger system of the HERA-B experiment is used to find muon track candidates as one of the inputs of the first level trigger. Due to the interaction rate of 40 MHz required to achieve an accuracy of 0.17 on sin(2beta) the total input of the muon pretrigger system is about 10 GBytes/s. The latency to define muon track candidates should not exceed 1 microsecond. Therefore the muon pretrigger is implemented as about 100 large size VME modules in a highly parallelized architecture.

We will present the system as well as performance studies and first physics results.

Summary:

The HERA-B experiment at the proton electron collider HERA at DESY, Germany, is designed to study the properties of B mesons with the main emphasis on CP violation. The B mesons are produced by hadronic interactions of protons with an energy of 920 GeV in a fixed wire target. An interaction rate of 40 MHz at an effective bunch crossing rate of 8.5 MHz is required to achieve an accuracy of 0.17 on sin(2beta). This leads to about 200 charged tracks per event in the detector and occupancies up to 20%. Therefore a highly selective and efficient trigger system is needed to suppress the background. It consists of four levels, the first level being a hardware trigger while the higher levels are software based using computer farms. The first level trigger (FLT) including the pretrigger systems must not exceed a latency of 10 microseconds and give a reduction of the input rate by a factor of 200 without causing deadtime. To meet these requirements it performs a track search algorithm either for high pT hadron, electron, or muon tracks, followed by a momentum and charge determination. Then the di-lepton invariant masses are calculated and adjustable cuts are applied.

The track searching of the FLT is being initiated by three distinct pretrigger systems, one of which is the muon pretrigger. It uses the hit information of two adjacent layers of muon chambers to define muon track candidates by means of a coincidence scheme. The building blocks of the muon pretrigger system are approximately 100 VME modules of three different types.

The pretrigger link boards (PLB) transfer the data used by the coincidence algorithm from the data buffers near the detector to the processing units of the muon pretrigger over a distance of 50m. The PLB also adds information to tag the detector data with an identifier to allow for an asynchronous data processing in the trigger system. The data are serialized and transferred via 800 MBit/s optical links to the pretrigger coincidence units (PCU). The main task of the PCU is to execute the coincidence algorithm. Therefore the input data from the PLB boards - amounting to about 20 GBytes/s in total - have to be partially duplicated and distributed to CPLDs which perform the main parts of the algorithm. The processing on the PCU takes place at a rate of 25 MHz. After serializing the coincidence data a pretrigger message generator (PMG) board translates it by means of look-up tables into messages for the FLT processors. These messages contain the track parameters and event identifiers used as starting points for the FLT tracking algorithm.

All muon pretrigger hardware is being operated in HERA-B since end of 1999 and used for triggering. We will present the system as well as results on its performance, which are achieved both from monitoring functions accessing the hardware and from archived event data. Also measurements of the efficiency and inefficiency will be shown, as well as first physics results using the muon pretrigger system.

Multichannel system of fully isolated HV power supplies for silicon strip detectors

Edward Gornicki (Institute of Nuclear Physics, Cracow, Poland) Stefan Koperny (Faculty of Physics and Nuclear Techniques of UMM, Cracow} Piotr Malecki (Institute of Nuclear Physics, Cracow)

Abstract:

A multichannel system of power supplies providing a bias voltage in the range of 0 - 410 V for silicon micro-strip detectors is presented. All channels are fully isolated allowing for flexible detector segmentation. A wide range of functions including e.g. a programmable current trip limit as well as a ramp-up and rump-down control independent for each channel are also described.

Summary:

The system consists of cards each of which contains several single isolated channels.The system is build in two similar versions. The full VME version for laboratory applications in small centers testing modules of silicon strip detectors. In this version a standard 6U card consists of four independent power supplies. The version for the final detector system of the ATLAS experiment uses standards of VME mechanics but a custom backup plane and crate control. In this version 8 channels are packed on each card.

The system provides digitally controlled stable bias voltage in 0 - 410 V range and a precise measurement of the output current. A maximum load of each channel is 5 mA. A current trip limit can be set independently for every channel in the range from hundreds of nA to the maximum of 5 mA. Another parameter which can be selected individually for each channel is the ramping speed with which the nominal voltage change is to be executed. Ramping speeds can be selected from the range of 10 - 100 V/s.

Single channel functions are controlled by programmable microprocessor which communicates with a programmable card controller via fast serial link. Communication with the crate controller for the VME version uses standard addressing mode. In the final production version this communication is realized with a fast custom parallel link. Mutual reaction times of processors to various conditions like requirement of a new setting, over-current and over-voltage trips etc are well below 1 ms.

First Level Trigger for H1, using the latest FPGA generation

M. Urban, A. Rausch, U. Straumann Physikalisches Institut Universitaet Heidelberg

Abstract:

To cope with the higher luminosities after the HERA upgrade, H1 builds a set of new MWPCs, which provide information to distinguish between beam background and true ep interactions. The first level trigger uses the latest 20K400 APEX FPGAs with 500 user IO pins to find tracks in 10000 digital pad signals. It allows to reconstruct the vertex and cut on its position. The system works deadtime free in a pipelined manner using 40 MHz clock frequency. The pipelines needed for data acquisition are also programmed into the same FPGAs. Test results including timing stability will be shown.

TDC based Readout for High-Rate Drift Tubes and Wire Chambers

H. Fischer*, J. Franz, A. Grunemaier, F.H. Heinsius, L. Hennig, K. Konigsmann, M. Niebuhr, T. Schmidt, H. Schmitt, H.J. Urban Fakultat fur Physik, Universitat Freiburg, 79104 Freiburg, Germany

Abstract:

The tracking system for the COMPASS experiment at CERN will consist of about 40000 drift tubes. In our report we discuss the design of and the practical experience with the drift-tube readout system which we set up during the year 2000 detector commissioning run.

The front-end board for the electronic processing of the signals produced by the drift tubes contains 64 preamplifiers, shapers, discriminators and time-to-digital converters. For the analog processing of the signals the ASD8b chip has been selected. For the COMPASS experiment we have developed a new TDC (F1) which comprises an asymmetric ring oscillator controlled by a phase locked loop. The digitised signals are transmitted via serial links to readout-driver modules. This 9U VME unit interfaces up to 16 front-end data-links to one optical S-LINK. Besides local event building the FPGA-based module covers front-end board initialisation, trigger distribution and data flow surveillance

Summary:

The tracking system for the COMPASS experiment at CERN will consist of about 40000 drift tubes. In our report we will discuss the design of and the practical experience with the digital readout system which we begin to set up during the year 2000 detector commissioning run.

The overall size of the experiment (6x4x40m^3), the expandability and the upgradability requirements of the experiment prerequisites a scalable and distributed readout system. The paradigm of the COMPASS readout foresees digitisation immediately at the detector. Data are stored on the front-end boards in random access memory or pipelines until trigger decisions have been taken. On-chip zero suppression, sparsification and signal over background extraction is accomplished by time correlation of hits with the trigger time.

The front-end board for the electronic processing of the signals produced by the drift tubes contains 64 preamplifiers, shapers, discriminators and time-to-digital converters. For the analog processing of the signals the ASD8b chip has been selected. The ASD8b has been originally designed for the drift tube readout of the SDC detector. Attractive attributes like short measurement time, good double pulse resolution and low operational threshold makes it the first choice for our application.

To ensure that the position resolution of the drift tubes is not spoiled by the electronics, the digitisation chain is required to have sub-nanosecond timing accuracy. In particular possible interference between the highly sensitive analog input and the high speed digital readout requires careful design and layout of the front-end board.

For the COMPASS experiment we have developed a new TDC chip (F1) which comprises an asymmetric ring oscillator controlled by a phase locked loop. A chain of 19 delay elements is used to tap time digitisation in steps of 120ps to 150ps (programmable). In a different mode, provided for multi-wire proportional chamber readout, 32 input lines are latched in groups of four to the eight TDC channels. In this case the resolution is 5~ns, and the last four bits of the time stamps are used to flag hits on the four connected lines. The F1 is based on a 0.6 micron sea-of-gates CMOS process. Excellent time resolution, high rate capability, low power consumption and wide flexibility due to in-system programmable setup registers let the chip appear as an ideal candidate for many applications not only in drift tube readout.

Further a common readout-driver module for all different detector front-ends has been developed. This 9U VME unit interfaces up to 16 front-end data-links to one optical S-LINK. Besides local event building the FPGA-based module covers front-end board initialisation, trigger distribution and data flow surveillance.

An FPGA-based implementation of the CMS Global Calorimeter Trigger

J. Brooke (University of Bristol) D. Cussans (University of Bristol) G. Heath (University of Bristol) A. J. Maddox (Rutherford Appleton Laboratory) D. Newbold (University of Bristol, Corresponding Author) P. Rabbetts (Rutherford Appleton Laboratory)

Abstract:

We present a new design for the CMS Level-1 Global Calorimeter Trigger, based upon FPGA and commodity serial link technologies. For each LHC bunch-crossing, the GCT identifies the highest pt electron, photon and jet candidates; calculates scalar and vector total transverse energies; performs jet-counting, and provides real-time luminosity estimates. The pipelined system logic is implemented using 0.18um Xilinx FPGAs. The traditional system backplane is replaced by fast serial links for trigger data, and Ethernet for control. These technologies allow an improvement in system flexibility and a considerable reduction in cost, complexity and design time compared to an ASIC/VME-based solution.

Summary:

The CMS Level-1 Global Calorimeter Trigger is the final component in the CMS calorimeter trigger chain. It reduces the data flow to the Level-1 Global Trigger by sorting the various categories of calorimeter trigger objects to find those with the highest transverse momentum. It calculates the scalar and vector total transverse energy for each LHC bunch-crossing to allow missing-energy triggers, and provides an indication of jet multiplicity to the Global Trigger to allow multi-jet triggers. The GCT will also perform luminosity monitoring in real time on a bunch-by-bunch basis, based on high-pt jet multiplicities, global energy flow measurements, and other signals.

The system design has recently been reviewed, and a new approach based upon high-performance commodity technologies has been proposed. The custom ASICs previously used for the sort, energy calculation, and other functions, are replaced by 0.18um Xilinx Virtex-E FPGAs. The system backplane is replaced by fast inter-board serial links based on a National Semiconductor Channel Link chipset, along with ethernet for system control and monitoring. The VME crate controllers are replaced by embedded processors on every trigger board, running the Linux operating system. The new system includes improved self-test capability, including JTAG for chip-level diagnosis. Taken together, these technologies allow an extremely flexible and modular system design; the entire range of trigger processing functions are implemented using seven identical boards, differentiated only by the FPGA programs. The cost and design time advantages of such an approach are highly significant. There are also benefits for the software creation and hardware and software debugging tasks. The system is at an advanced stage of prototyping, and the GCT generic trigger processor boards are also being considered as part of an upgrade to the ZEUS Level-1 trigger.

Possibility of SR8000 Supercomputer for ATLAS DAQ Event Building and Event Filtering

ANRAKU, Kazuaki (ICEPP, Univ. of Tokyo), IMORI, Masatosi (ICEPP, Univ. of Tokyo)

Abstract:

We are investigating the possiblity of adapting the SR8000 supercomputer system by Hitachi for ATLAS DAQ event building and event filtering. The SR8000 system is comprised of a number (up to 128) of nodes, each of which has RISC microprocessors sharing a main memory, and of high speed "multi-dimensional" inter-node network. The maximum total processing power amounts to 1024 GFLOPS and a bidirectional transfer rate of the inter-node network is 2 Gbyte/s. An arbitrary number of nodes can have I/O adapters of HIPPI, ATM, Ethernet, and Fast Ethernet. These features seem to be suitable to both the ATLAS DAQ event builder and event filter.

Summary:

The "Supertechnical Server" SR8000 system by Hitachi, Ltd. is a parallel processing computer system comprised of a variable number (up to 128) of nodes, each of which has 64-bit RISC microprocessors sharing a main memory, and of high speed "multi-dimensional" inter-node network. Each node has a maximum processing power of 8 GFLOPS and a maximum main memory of 8 GB, resulting in the maximum total processing power amounts to 1024 GFLOPS. The nodes are connected to each other by three-dimensional "crossbar network" with an unidirectional transfer rate of 1 Gbyte/s and a bidirectional transfer rate of 2 Gbyte/s. A cooperative microprocessors architecture in each node and pseudo-vector processing in each processor, together with the high speed inter-node communication, realize the high performance.

The nodes are classified to three types; supervisory node (SVN) unique to the system and controlling the whole system, I/O node (ION) processing and input/output operating, and processing node (PRN) processing only. Any node except for the SVN can be selected to be an ION or a PRN. IONs and SVN are equipped with I/O adapters to connect to I/O devices and/or outer industrial standard networks; HIPPI, ATM, Fast Ethernet, and Ethernet.

By feeding the detector data fragments from the ReadOut Crates (ROCs) via EventBuilder Interfaces (EBIFs) into the corresponding I/O nodes and exchanging data between the processing nodes, the SR8000 system can possibly work well as an event builder instead of a switching network implemented in the DAQ/EF -1 prototype. In addition to the event building, the maximum total processing power of a single SR8000 system is supposed to well fulfil the estimated minimum required processing power of the event filtering of 10^6 MIPS.

Supposing the SR8000 system to be a promising candidate for the event builder and event filter, we are now investigating the possiblity and feasibility of adapting the SR8000 system for the DAQ system.

CMS REGIONAL CALORIMETER TRIGGER HIGH SPEED ASICs

P. Chumney, S. Dasu, M. Jaworski, J. Lackey, W.H. Smith

University of Wisconsin - Madison

Abstract:

The CMS regional calorimeter trigger system detects signatures of electrons/photons, taus, jets, and missing and total transverse energy in a deadtimeless pipelined architecture. This system contains 19 crates of custom-built electronics. Much of the processing in this system is performed by five types of 160 MHz digital ASICs. These ASICs have been designed in the Vitesse submicron high-integration gallium arsenide gate array technology. The five ASICs perform data synchronization and error checking, implement board level boundary scan, sort ranked trigger objects, identify electron/photon candidates and sum trigger energies. The design and simulation of these ASICs and prototyping results are presented.

Summary:

The CMS Regional Calorimeter Trigger receives compressed data from the calorimeter readout electronics on 1.2 GBbaud copper links, each carrying data for two HCAL or ECAL trigger towers accompanied by error detection codes. 19 total crates (18 for the barrel/endcap and one for both forward calorimeters) each contain seven rear mounted Receiver cards, seven front mounted Electron Isolation cards, and one front mounted Jet Summary card plugged into a custom point-to-point 160 MHz differential ECL backplane. Each crate transmits to the global calorimeter trigger processor its sum Et, missing energy vector, 4 highest-ranked isolated and non-isolated electrons, and 4 highest energy jets and 4 tau-tagged jets along with their locations.

The five digital ASICs developed for the regional calorimeter trigger are the Adder ASIC, Phase ASIC, Boundary Scan ASIC, Sort ASIC and Electron Isolation ASIC. They were produced in the Vitesse FX(TM) and GLX(TM) gate arrays utilizing their submicron high integration gallium arsenide MESFET technology. Except for the 120 MHz TTL input to the Phase ASIC, all ASIC I/O is at 160 MHz ECL.

The Phase ASIC deskews the 120 MHz TTL data from the input 1.2 GBaud copper receiving and deserializing circuitry. It performs error detection and multiplexes the output at 160 MHz ECL. The Phase ASIC also provides test vectors for board and system diagnostics.

The Boundary Scan ASIC implements board-level Boundary Scan and backplane drivers.

The Adder ASIC provides a 4-stage pipeline with eight input operands and 1 output operand. There are three stages of adder tree, with an extra level of storage added to ensure chip processing is isolated from the I/O. The ASIC uses 4-bit adder macro cells to implement twelve bit wide adders.

The Electron Isolation ASIC, processes a total of 36 towers through three separate blocks. The Input Staging block places each reference tower and its neighbors in the same time frame. The Add/Compare block forms four sums between a reference tower and its top, bottom, left and right neighbors. The Find Max block places the single maximum from the original four sums in a register. The HAC Veto, neighbor HAC Veto, and neighbor EM Veto are stored with each of these sums. A final stage of logic sorts through all 16 maxima generated over a bunch crossing time and places that value, along with its Vetos, on the outputs.

The Sort ASIC reads in 4 sets of 4 operands every 25 ns. Each set of 8 operands is divided into two groups of four. The operands are compared in pairs between the two groups, with the larger of the two taking over the position of the left hand member of the pair. This comparison is performed in four stages with a rotation of compared pairs occurring between each stage. By the end of the fourth stage a sufficient number of comparisons have been made to ensure the four largest values of the 16 inputs are in the left-hand group.

Design of a comparator in a 0.25µm CMOS technology

Niels van Bakel, Jo van den Brand (Free University of Amsterdam / NIKHEF Amsterdam), Hans Verkooijen (NIKHEF Amsterdam), Daniel Baumeister, Werner Hofmann, Karl-Tasso Knoepfle, Sven Loechner, Michael Schmelling, Edgar Sexauer (Max-Planck-Institute for Nuclear Physics, Heidelberg) Martin Feuerstack-Raible (University of Heidelberg), Neville Harnew, Nigel Smale (University of Oxford)

Abstract:

A comparator for the LHC-B vertex detector front-end chip, the Beetle, has been designed in a 0.25µm CMOS technology and is sent for fabrication. To improve threshold uniformity, each comparator has a 3 bits DAC. The comparator can handle positive and negative inputsignals. A polarity signal changes the polarity of the threshold voltage and makes the outputsignal always positive when active. The outputsignal is latched by a 40MHz clock and is selectable between time-over-threshold (in 25ns bins) or active for one clockcycle. Simulation- and measurement results will be discussed.

Summary:

For fast primary vertex reconstruction and pile-up rejection binary hit information is needed from the LHC-B vertex detector front-end electronics. Therefore a comparator for the Beetle chip has been designed. The Beetle is a 128 channel analog pipeline chip for the LHC-B experiment and, like the comparator, implemented in a 0.25µm CMOS technology, using rad-tolerant layout rules. To make the comparator insensitive for low frequency inputsignals, e.g. temperature drift and different offsets, one of the inputs of the comparator has a low-pass filter to obtain the DC-voltage of the incoming signal. This voltage is summed to the threshold voltage. The threshold voltage is the combination of a controllable voltage used for all comparators and a individual voltage for each comparator controlled by a 3 bits DAC. The comparator operates in a 40MHz system. The outputsignal of the compared time-over-threshold voltage is latched at a well defined time by a 40MHz clock, which is related to the beam timing. The width of the analog inputsignals is roughly 25ns and therefore the time-over-threshold can be longer than one period. By means of a "output mode selection" the outputsignal can be time-over-threshold (in 25ns bins) or one pulse of 25ns once the inputsignal went over threshold. The comparator can deal with positive and negative inputsignals. A polarity signal switches the polarity of the threshold voltage and controlles the output stage so that the outputsignal is always a positive pulse. In addition a multiplexer to store hits as binary information has been designed. This multiplexer selects the signal to the analog pipeline between the shaper output or the comparator output and converts the digital signal from the comparator in 0 or 10 MIP signal. Specifications -The timewalk of the outputsignal is 10ns for signals between 5mV to 100mV above threshold. -The inputsignal should be between GND + 0.8V and VDD - 0.8V. -The powerconsumption is expected to be 350µW.

FEE tracker module developments for ALICE and STAR

Abstract:

Assessments of the front-end module developments in the frame of ALICE and STAR trackers in relation with the radiation effects on detectors and chips. Production of similar modules for the STAR SVT.

Comparative study of current-mode versus voltage-mode analog memory in a 0.25um CMOS technology

F.VAUTRIN, J.MICHEL, F.BRAUN

Abstract:

The aim of this work is the study of switched-current and voltage-mode memory cells in order to develop a model including non-ideal effects such as charge injections,non-linear capacitance and readout system influence. These models will allow non-linearity control regard to surface, speed and power criteria in digital dedicated submicronic technology. Such models lead to a memory cell optimization in order to include it in an analog memory for LHC experiments.

Summary:

By definition, an analog memory consists of several thousands of channels of several hundreds of depth cells. The study of these memories goes through memory cells performances identification The cells have to be faithfully reproducible, low noise, of minimum area and power. Power per cell and area per cell are critical points. A state of the art on analog memories works show that the balance between power and area can be achieved by using submicronic technologies. Moreover, such technologies can be used in radiative environment. It is important to study second generation switched-current structures as an alternative to voltage mode structures. These structures are fully compatibles with the new CMOS submicronic technologies dedicated to digital circuits. Indeed, there are not limited (first approximation) by linearity and hysteresis of storage capacitors, like in voltage-mode. The goal of this study is to identify accuracy limits that can be reached with minimum size architectures in a deep submicronic technology (0.25 um) for both types of cells: voltage mode and current mode. By comparison to a typical N bits acquisition system, accuracy error should be less than half a quantum. By studying operating phases of each cell, we have developed theoretical models that include non-linear effects such as charge injections, readout system influence for both types of cells, finite output conductance for current-mode cell, and non-linear capacitance for voltage mode cell. These models are polynomials of output signal as a function of input signal. Accuracy is divided in two parts: static and a dynamic accuracy. In fact, dynamic error is over-evaluated and final precision is only conditioned by static precision that is to say non-linearity error. In such a cell with a 40 MHz acquisition frequency, dynamic error is limited to a half quantum of 9 bits for an 8 bits final precision. This analysis highlights predominant factors that influence non-linearity error: memory capacitance value, output impedance, memory transistor size (switched-current). For both cell types, final accuracy, acquisition frequency and power dissipation are fixed constraints. Freedom degrees are full-scale, area and errors repartition. For voltage-mode cell, the full-scale is fixed by technology constraints. The model predicts an 8 bits non-linearity error for a 300fF capacitance value and a 60 um2 area. A comparison with current-mode cell shows an 8 bits non-linearity error for an 800 fF capacitance value and a 140 um2 area. The paper is focused on polynomials development and exploitation. Such models allow the optimization of a memory cell for LHC experiments. In current-mode cells, full-scale and bias current are variables. By exploiting these models, the designer is able to do compromises between accuracy, power dissipation and area in order to obtain the same accuracy than a voltage mode cell. Finally, two optimal cells are presented.

Overview of the ATLAS LAr front-end radiation tolerance

C. de La Taille (LAL Orsay)

Abstract:

The front-end electronics of the ATLAS liquid argon calorimeter must withstand a non-negligible radiation environment (20Gy/yr 5e11N/cm2/yr), in particular when various safety factors (simulation inaccuracies, lots variability or low dose rate effects) are put on top. The design of all the front end elements is now complete and has been tested on module0 on over 2,000 channels. Several key components have been extensively tested to radiation exposure (preamps, shapers, pipelines...) whereas other circuits (mostly digital) are being now migrated into DMILL. The results of these tests will be summarized and the design of the DMILL chips will be presented. The next milestone of the LAr collaboration is to have a final radiation hard complete front-end prototype by mid july.

Design Considerations of Low Voltage DC Power Distribution for CMS Sub-Detectors

B.Allongue, F. Fontaine, F. Szoncso, G. Stefanini CERN Switzerland S. Lusin, P. Robl University of Wisconsin, Madison, USA J. Elias Fermilab, USA C. Rivetta ETH Zurich/CERN Switzerland

Abstract:

A distinguishing feature of LHC detectors is the enormous number of front-end electronics (FE) channels in all of the sub-detectors. Low-voltage power supply systems in the range of multi-kilowatts are required to bias such electronic read-outs. Several configurations has been proposed and analyzed by the different groups showing particular advantages and disadvantages. For the CMS detector, the Hadronic Calorimeter (HCAL) and the Muon End-caps (EMU) have proposed a DC power distribution system based on DC-DC power switching converters.

The topology of this DC power distribution is as follows: AC/DC converters in the control room are used to rectify the three phase mains and generate the primary 311 VDC voltage. Each rectifier supplies several DC-DC converters located in the cavern near the FE. The switching regulators convert the high voltage into appropriated low voltages that are locally distributed to the detector read-outs. Local regulation is performed in the FE at the board level using special linear low-dropout voltage regulators developed by CERN RD-49 collaboration.

The main advantage of this topology is the reduction in volume of the distribution cables due to the relative low primary currents. Locating the DC-DC converters in the hostile environment of the detector cavern is a disadvantage due to the presence of magnetic fields and radiation. Analysis and tests are necessary to characterize the behavior of those units under such conditions and find acceptable solutions. Also, further studies and tests are necessary to mitigate the radiated and conducted noise generated by the switching converters, to ensure stability of multi-converter systems against interactions between units, etc.

In this paper, tests conducted to validate the application of commercial units are reported and future tests are described. Also, an analysis of the overall system performance is presented along with guidelines for design and selection of the components are presented.

Summary:

This paper describes the tests performed to validate switching converter units to be applied in the DC power distribution of CMS-EMU and CMS-HCAL sub-detectors.

Modularity of the DC-DC converters is the primary requirement. It will facilitate replacement of failed units during short-period scheduled access to the cavern providing a reduction in the time that a part of the sub-detector is down. Each modular unit will thus include not only the basic power converters to attain the required output low-voltages but also protection, filtering, monitoring system and interface for remote operation. The tendency is to use commercial units (COTS) to fulfill this design but it is difficult to satisfy all of the requirements with such units. Instead, a 'semi-custom' design has been used based on COTS with the collaboration of manufactures, assembly companies and the universities and laboratories involved.

The primary stage of the design is the search for suitable units that can operate in environments with radiation. A radiation test has been conducted and future tests are under evaluation. The idea is to characterize the radiation tolerance of candidate converters and analyze, in case of failure, critical component to be replaced in the prototypes.

These tests include total dose effects and Single Event Effects (SEE) (single event up-set, single event latchup, single event breakdown, etc.). The first test was performed at the Commisarat d'Energy Atomic (CEA), Dijon, France. A low energy neutron reactor was used to test commercial DC-DC units for total dose effects. Two Vicor converters with 300V input and 5V / 12 V output, 400W, were radiated up to a level of 3x10^11 neutrons/cm^2 during an 8 hrs exposure which represents the total dose for continuous operation over 10 years. The results were satisfactory measuring only less that 0.5% of drift in the output voltage of the converters. This behavior was the similar to the one experienced in previous tests performed on other Vicor units with different characteristics. In future tests, higher energy particles will be used to study the SEE performance of these units and of new prototypes acquired from different vendors.

The magnetic field, in the areas assigned for the DC-DC converters, is about 200mT (2000 Gauss). This level is inappropriate for good operation or performance of converters with magnetic components. This problem involves a study of the maximum levels of magnetic field in different directions that the converter can tolerate operating with good performance. Studies and tests of the inductance and transformer of Vicor converters have been performed using a constant magnetic field at CERN. In the experiment, the level of magnetic field around the converter units will be reduced to an adequate level using a soft-steel magnetic shielding.

Switching power supplies, in general, are noisier than equivalent linear power supplies. In the CMS application it is very important to keep the noise level below values that do not compromise the operation and performance of the FE and neighbor systems. Conductive and emitted noise tests are scheduled on the Vicor units and input/output cables. The first test is performed on Vicor units connected through standard input/output cables to allow a determination of the level of filtering necessary and the shielding necessary in the cables to reduce both the conducted and emitted noise. Similar tests are planned on new prototypes.

Due to the negative input impedance characteristic of the DC-DC switching regulators at low frequencies, interaction between switching regulators and the others part of the input system may result in system instabilities. Small and large-signal models of both converters and line conditioners have been evaluated to analyze the performance and stability of the whole system. Based on this analysis, guidelines to design the proper input filtering of the DC-DC converters is presented.

The Front-end electronics will use on board radiation tolerant linear regulators. This choice simplifies the design of the connection between the converters and the FE because remote sensing is not required. The regulators will absorb the voltage variation due to the drop in the line resistance by changes in the load current. The only consideration on this link is to provide enough damping on the lines with passive elements to avoid big voltage excursions at the FE input.

An additional, but important, last consideration is the reliability of the complete system. As presented above, the DC-DC converters should be modular to assure the easy replacement in case of failure. That allows consideration of units with industry standard mean time between failure (MTBF) performance. If it is not possible to replace units during scheduled weekly accesses, then units with longer MTBF or N+1 redundant units are necessary.

Experience with DMILL technology in the Development of the ASDBLR ASIC

N. Dressnandt, N. Lam, F.M. Newcomer*, R.P. VanBerg, H.H. Williams
University of Pennsylvania, Philadelphia Pa.

Abstract:

An engineering prototype of the ASDBLR ASIC has been fabricated in the rad hard, BICMOS, DMILL process offered by Temic. This ASIC integrates eight channels of high speed low power and low noise straw tube readout on a single substrate. Bi-level signal detection for ionizing tracks and TR photons at rates as high as 20MHz is accomplished utilizing six hundred custom sized components per channel. A previous DMILL prototype showed strong sensitivity to hookup conditions manifested as unexpected harmonics. Steps taken to eliminate these harmonics, including improvement of the device models appear to have been successful. Measured performance of the recent prototype nearly exactly matches SPICE calculations. Results from neutron and proton exposures, beam tests with the companion DTMROC readout chip and plans to include custom devices that have been fabbed for us by TEMIC will be discussed.

Summary:

The ASDBLR ASIC is intended to provide the full signal processing chain, input to tri-level discriminator output for the 430,000 straw ATLAS TRT detector. Measurements of a first version of this ASIC fabricated in a bulk analog bipolar process served to qualify the circuit technique for use in the ATLAS TRT. We have since decided to develop a version in DMILL, a rad hard SOI, BICMOS process recently commercialized by Temic. A six channel ASIC was designed in DMILL and submitted for fabrication in the summer of 1997. Our first tests with packaged chips indicated a sensitivity to hookup which was ultimately traced to on chip crosstalk through the SOI substrate. A more complete discussion can be found in the LEB99 proceedings.

In August 1999 we submitted a revised version of the ASDBLR and it's companion timing and readout ASIC, the DTMROC, for an engineering run. Both chips are fully functional and match well with pre submission simulations. Harmonic oscillation in the ASDBLR specific to the DMILL design was addressed with the following modifications that appear to have successfully resolved the problem: 1) Use of CEA developed shielded input pads. 2) Addition of a differential stage prior to tail cancellation to reduce single ended capacitor driven cross talk to the back substrate. 3) Addition of global substrate grounding rings around all sensitive devices to fix the potential of unused areas of silicon above the SOI substrate. 4) Addition of a small preamp supply R-C filter network on each channel.

The following circuit embellishments were added to improve the general performance: 1) Addition of dynamic current sources on the buffer transistors that drive the baseline restorer to reduce quiescent current. 2) Addition of a fixed 4ns delay in the output of the low level discriminator to align the output of low and high outputs for a clean ternary sum. 3) Programmable tuning of the ion tail cancellation.

Test Devices -

Significant stray, to the substrate underlying the insulator in DMILL devices combined with the relatively high gain and bandwidth required for the ASDBLR amplifier and shaper circuit make it desirable to minimize stray capacitance of on chip devices at the input. Large area devices at the input include, input pads, input protection, and transistors. A shielded input pad designed by a CEA group has been approved for use by TEMIC and was incorporated successfully in the ASDBLR. In December 1998 TEMIC fabbed several custom test structures for us including two types of multi-striped NPN transistors for use as input transistors and an input protection structure consisting of a large number of parallel connected NPN transistors. Multi-striped NPN transistors offer the advantage of lower base resistance and lower stray capacitance for the same collector current density compared to single emitter stripe devices. Expanded geometry single stripe NPNs with collector and base shorted to a supply were used for input protection. In this configuration the collector acts as a shield to the back substrate and is shorted to the base which becomes the anode of the input protection structure. The emitter acts as the cathode and has the desirable benefit of a comparatively low stray capacitance. The reverse bias of this base emitter junction is well controlled under ordinary conditions by the single Vibe drop of the ASDBLR common emitter input configuration.

Test Structure Measurements - Two transistors on the input protection test structure were wired in common emitter configuration to mimic the ASDBLR input and a repetitive pulse was amplified and observed while the input protection was tested by discharging repeatedly a capacitor charged by a variable voltage through 24 ohms at the input. Reliable protection to 1500uJ was provided by this structure.

ASDBLR Measurements - The peaking time appears to be about 15% faster than the desired 7.5ns value while the absolute threshold is within 5% of the SPICE calculated value for both high (TR photon sensitive) and low (tracking) discriminators. The functional yield is ~75% but after applying channel to channel threshold matching requirements the yield is only 35%, about half of that of a design of similar complexity fabbed by us in a bulk process. Resistor matching results reported by the foundry indicate a larger than expected variation which can be responsible for the lower yield. We have carefully examined the circuit and find no other plausible explanation at this time.

Radiation tests - Unbiased ASDBLR's from this run were exposed to 10^14 neutrons/cm^2 at Prospero and no change in performance is observed. On chip resistors were tested and changes were less than 1%. Both multi-stripe and single stripe NPN devices from the test structures were also exposed and found to have a beta of ~60 at a current density of 3.3uA/um of emitter. Pre-rad beta was ~280.

Future Measurements ASDBLR's and their companion chips (DTMROC's) have been exposed under power to 10^14protons/cm^2 at CERN and are awaiting the return of these devices for post rad characterization. Beam tests using prototype modules and a high density readout with ASDBLR and DTMROC ASICS are planned to take place at the H8 beam line at CERN over the summer. Results of these tests should be available for the September LEB meeting.

Statistical performance estimation and optimization of the CMS tracker optical links

F. Jensen, C.S Azevedo, G.Cervelli, K.Gill, R.Grabit, F.Vasey
CERN, Geneva, Switzerland

Abstract:

A significant number of analogue performance measurements have been carried out on the CMS tracker optical links with components selected to be close the final system. The measurements form the basis for an estimation of the expected analogue performance of the final tracker links. In particular the typical S/N and linearity performance will be estimated. Realistic performance limits based on estimations of the performance spread of the final 50000 links are also deduced. Finally we discuss ways to further optimize the analogue performance of the optical links using offline processing.

Summary:

The CMS tracker optical links project is in a phase where it is possible to identify the final components to be used in the tracker optical link system. Market surveys have been issued and the component selection process is well underway for the whole system with some additional development work remaining mainly for the electronics. These developments have enabled tests to be carried out with links that closely resemble the final system in significant numbers. These measurements form the basis for a statistical estimation of the analogue performance of the final tracker links. In particular the RMS-noise, Signal-to-Noise Ratio and non-linearity distributions are extracted. The analogue performance distributions enable realistic estimations of typical performance and performance spread of the final 50000 links to be deduced, and realistic system performance limits are shown. These results in turn make it possible to carry out a comparison with the link specifications and determine how successful the system and component specifications have been in achieving adequate analogue performance for the links. Finally we discuss ways to further optimize the analogue performance of the optical links using offline processing. In particular we look at ways to reduce system non-linearity by using a modified link calibration scheme.

Switching Power Supply Technology for ATLAS LAr Calorimeter

H. Takai and J. Kierstead
(for the ATLAS Liquid Argon collaboration)
Brookhaven National Laboratory

Abstract:

The ATLAS liquid argon calorimeter is designing a switching power supply to be meet the harsh environmental requirements imposed by the location where they will be installed. In addition the design addresses the inaccessibility issue. We will present the design and available tests regarding radiation and magnetic field susceptibility.

The ATLAS liquid argon calorimeter is planning to install power supplies for the front end electronics in the gap region between the tile barrel and tile extended calorimeters. The required power for the overall electronics is approximately 150 kW. This requirement rules out the use of copper cables to bring the power to the crates. In this location the environmental and access issues are such that the design will have to follow very tight specifications. The environmental issues are twofold: magnetic field and nuclear radiation. The radiation in the location of the power supply is a mixture of particles from the tails of Hadronic showers. They include photons, hadrons, and electrons. The expected integrated dose over a period of ten years is of the order of 10 kRad, and the overall flux of 1 MeV equivalent neutrons 1x10^12.cm-2. The flux of neutrons above 1 MeV is estimated to be 5 kHz.cm-2. The magnetic field in the region of the power supplies is estimated to be 50 Gauss. The current maintenance schedule allows access to the volume including the power supplies only once a year, therefore reliability and remote monitoring and control is essential. The final requirement that we have to meet is a very limited space.

With these requirements in mind, we have established a strategy for the development of appropriate power supplies. Currently, we expect to have prototypes ready by the end of year 2000. The plan calls for a radiation tolerant and single event upset resistant power supply with remote operational capabilities. At the heart of the power supply blocks of DC-DC converters will be used. A number of these blocks will be connected in parallel to form an N+1 redundant system. Each block will be monitored during the operation for temperature, fatal failure, over-current, and over-voltage. At the present time two potential manufacturers have been identified, Vicor and Modular Devices Inc. Vicor modules meet the requirements for electronic noise, magnetic field, and limited radiation tolerance but have not been tested for single event effects. The DC-DC converter manufactured by Modular Devices is known to be radiation tolerant but has not been tested for magnetic field or SEE effects. The control circuits are designed to be radiation and SEE tolerant.

In spring 2000 we plan to initiate tests for SEE susceptibility using heavy ion beams, followed by tests using 100 MeV or greater protons. We are particularly concerned with SEB or SEGR in the power mosfets as well as possible latchups in the control logic. We will report on the progress on the development of the power supply. In particular preliminary tests as far as radiation is concerned will be discussed.

CHARACTERISATION OF THE APVD READ-OUT CIRCUIT FOR DC-COUPLED SILICON DETECTORS (Final report)

J.D. Berst, C.Colledani, Y.Hu, R.Turchetta, LEPSI, IN2P3/ULP,
23 rue du Loess, BP20, F-67037 Strasbourg, France

G.Deptuch, U.Goerlach, C. Hu-Guo, P.Schmitt, IReS, IN2P3/ULP,
23 rue du Loess, BP20, F-67037 Strasbourg, France

M.Dupanloup, S.Gardien, IPNL IN2P3/CNRS, F-69622 Villeurbanne, France

Abstract:

The APVD integrated circuit for the front-end electronics of DC-coupled silicon detectors for CMS has been developed and produced in the radiation-hard process DMILL.The APVD_DC contains, like other members of the APV family 128 identical analog channels, each composed of a low noise preamplifier, a CR-RC shaper, an analog pipeline of 160 cells and a signal processing stage. A current compensation circuit is added in every preamplifier to sink the leakage current coming from the detector.

We report on the final test results: the complete circuit has been tested and measured also in the presence of significant leakage currents up to 11 microampere which do not deteriorate the analog performance of the circuit like pulse shape dynamic range and adding about 300 ENC to the noise.

Previous APVD circuits suffered from an instability problem in the analog stage of the circuit occurring at nominal bias values. The analog baseline of the new modified circuit is absolutely stable also under extreme operation conditions, like high bias currents demonstrating that the implemented solution stops indeed the oscillation of the circuit as we previously claimed based on extensive simulations of the circuit.

A Novel Monolithic Active Pixel Sensor for Charged Particle Tracking and Imaging using Standard VLSI CMOS Technology

J.D. Berst, B.Casadei, G.Claus, C.Colledani, W.Dulinski, Y.Hu, D.Husson,
J.P.Le Normand, R.Turchetta, J.L.Riester LEPSI, IN2P3/ULP,
23 rue du Loess, BP20, F-67037 Strasbourg, France

G.Deptuch, U.Goerlach, S.Higueret, G.Orazi, M.Winter IReS, IN2P3/ULP,
23 rue du Loess, BP20, F-67037 Strasbourg, France

Abstract:

A novel Monolithic Active Pixel Sensor (MAPS) for charged particle tracking made in a standard CMOS technology is proposed. The sensor is a photodiode with a special structure, which allows the high detection efficiency required for tracking applications. The partially depleted thin epitaxial silicon layer is used as a sensitive detector volume. A first prototype has been designed and fabricated using a standard sub-micron 0.6 um CMOS process. It is made of four arrays each containing 64 times 64 pixels, with a readout pitch of 20 um in both directions. Extensive tests made with soft X-ray source ( 55 Fe) and minimum ionising particles (15 GeV/c pions) fully demonstrate the predicted performances, with the individual pixel noise below 20 electrons(ENC) and the Signal-to-Noise ratio of the order of 40, both for 5.9 keV X-rays and Minimum Ionising Particles (MIP). A new version of the circuit has been submitted to the 0.35 um Alcatel-Mietec process. This novel device opens new perspectives in high precision vertex detectors as well as in other applications.

Summary:

A novel Monolithic Active Pixel Sensor (MAPS) for charged particle tracking made in a standard CMOS technology is proposed. The sensor is a photodiode, which is readily available in a CMOS technology. The diode has a special structure, which allows the high detection efficiency required for tracking applications. The partially depleted thin epitaxial silicon layer is used as a sensitive detector volume. Semiconductor device simulations, using either ToSCA based or 3-D ISE-TCAD software packages show that the charge collection is efficient and reasonably fast (order of 100 ns), and the charge spreading limited to a few pixels only. A first prototype has been designed, fabricated and tested. It is made of four arrays each containing 64 times 64 pixels, with a readout pitch of 20 um in both directions. The device is fabricated using standard sub-micron 0.6 um CMOS process, which features twin-tub implanted in a p-type epitaxial layer, a characteristic common feature to many modern CMOS VLSI processes. Extensive tests made with soft X-ray source ( 55 Fe) and minimum ionising particles (15 GeV/c pions) fully demonstrate the predicted performances, with the individual pixel noise below 20 electrons(ENC) and the Signal-to-Noise ratio of the order of 40, both for 5.9 keV X-rays and Minimum Ionising Particles (MIP). A new version of the circuit has been submitted to the 0.35 um Alcatel-Mietec process to improve radiation hardness and to explore the performance of deep-sub-micron technologies with thinner epitaxial layers and thus less primary exploitable ionization.

This novel device opens new perspectives in high precision vertex detectors in particle physics experiments at future colliders, as well as in other applications, like low energy beta particle imaging, visible light single photon imaging (using the Hybrid Photon Detector approach) and high precision slow neutron imaging.

Radiation hardness studies for CMS HF quartz fiber calorimeter

G. Dajkó, A. Fenyvesi, K. Makónyi, J. Molnár
Atomki, Debrecen, Hungary

P. Raics
University of Debrecen, Debrecen, Hungary

I.Dumanoglu
Cukurowa University, Adana, Turkey

J. P. Merlo
University of Iowa, Iowa City, USA

A Kerek, D. Novák
Kungl Tekniska Högskolan, Stockholm, Sweden

Abstract:

A project has been in progress to provide information on radiation hardness properties of Hamamatsu photomultiplier tubes and quartz-fibers to be used in the construction of CMS Very Forward Calorimeter. Neutron activation studies as well as neutron, gamma and electron radiation tolerance tests have been carried out, using 3.7 MeV average energy neutrons, 500 MeV energy electrons and Co-60 gamma radiation. The test setups, the irradiation conditions as well as the experimental results are described.

Summary:

Introduction

Very Forward Calorimeters (VFCs) in LHC detectors cover the pseudorapidity range from 2.5 to at least 5 in order to compute missing transverse energy and for jet tagging. The forward calorimeter (HF) in CMS will experience unprecedented particle fluxes. The 10 years of LHC operation will result in about 1 GRad total dose. Operation at such conditions requires the use of calorimetry technique that is insensitive to radiative load.

The CMS HF is based on the quartz-fiber technology, using silica-core and silica-clad fibers as the active component. This choice was based predominantly on their exceptional radiation resistance. In such a calorimeter, the signal is detected when charged shower particles above the threshold generate Cherenkov light.

The read-out of the light from the fibers are done by UV sensitive photomultiplier tubes (PMT).

The purpose of this paper is the presentation of the performances of the different kinds of silica fibers and ultra-violet photodetectors in the presence of radiation. We focused on a shorter wavelength region between 325 and 800 nm under an irradiation field, with special attention to the PMTs sensitivity range, 400 to 500 nm.

Test facilities and conditions

An IBM-PC based Ocean Optics Model (SD 2000 type) spectrometer with a pulsed Xe lamp was used for all fiber related measurements. One part of a Xe light pulse goes directly to the spectrometer as a reference. The second part is sent to the fiber sample under irradiation. This setup allows in-situ measurement of the fiber darkening. We performed measurements at two different facilities: at the LIL. The LIL , LEP pre-injector at CERN provides a 500 MeV electron beam on the target.

In the fast neutron tests at ATOMKI in Debrecen, Hungary the MGC-20 cyclotron based neutron source was used generating neutrons with an average energy of 3.7 MeV.

All the HAMAMATSU PMT tests - gamma, neutron, and activation - were carried out at ATOMKI.

Analysis and results

The expression for the light attenuation of the fibers can be written as:

A(l)=Ao(l)-(10/L)log(Iirr(l)/Io(l))

where Ao(l) is the attenuation of the fiber prior to irradiation, L is the length of the irradiated fiber and Iirr, Io are the spectral intensities measured for irradiated and unirradiated cases.

The LIL measurements exhibit the well-known absorption peak of high OH content quartz-fibers around 630 nm. In the range from 400 to 525 nm where the HF detector is sensitive for Cherenkov light, the attenuation is typically varying between 2-3 dB/m. In the results of fast neutron tests the UV-tail and the absorption band at around 630 nm are also clearly observable. At 1E15 n/cm2, the induced loss in the region of interest is about 1 dB/m.

Concerning the R5600 type PMTs we carried out a series of measurements like spectral response, dark current characteristics, gain variation, energy spectroscopy and activation as a function of the neutron flux-rate, fluence and the gamma total dose. We observed no degradation in optical characteristics of the tubes for low-flux and low fluence irradiations.

Compact Bidirectional 2.5 Gbit/s Optical Transceiver for the H1-Experiment

S. Lueders, R. Baldinger, R. Eichler, C. Grab, B. Meier, S. Streuli, K. Szeker
Institute for Particle Physics, ETH Zuerich, 5232 Villigen PSI, Switzerland

Abstract:

For triggering purposes, 9600 channels have to be read out within 96 ns, i.e. with a rate of 100 Gbit/s, using 40 identical very compact optical transceiver units --- each measuring 130 mm x 45 mm x 9 mm. Taking advance of VCSEL diodes and 90 degree fiber bending, 4x 850 Mbit/s of digitized trigger information as well as two channels with analog monitoring information are transferred to the receiver electronics 40 m away. From there two channels of 10 MHz clock information are received for timing adjustments.

Summary :

The upgrade of the multi-wire proportional chamber (CIP) of the H1-experiment at HERA (DESY) increases the number of chamber-channels to 9600. These channels have to be made available to the z-vertex trigger within the time between two bunchcrossings of 96 ns and thus need be transmitted at a total data rate of 100 Gbit/s. With the extremely tight spatial conditions at the CIP end flange --- an open cylinder with inner and outer radii at 150 mm and 200 mm, respectively, and a length of 130 mm --- a fast and compact bidirectional readout electronic is required, keeping the power consumption and the amount of dead-material in the experiment to a minimum.

40 identical transceiver units, stacked on top of each other in groups of five, were designed to feed the digitized trigger information and selectable analog chamber signals to the receiver electronics 40 m away. In the other direction, clock information is provided.

Using the CIPix chip from the ASIC laboratory, Heidelberg, a 16 fold multiplexing is performed on the digitized information.

A custom made optical hybrid serves as an interface between the optical and electrical world, driving VCSEL diode arrays with four channels of trigger information --- each with a data rate of 625 Mbit/s --- and two channels of analog signals. Aligned to the VCSEL array with a precision of 5 mum, an array of two PIN diodes receives the clock signals needed for internal timing. Firmly attached to the hybrid and positioned with high precision, a 8-fiber ribbon cable deflects the light by 90deg within 5 mm of height and transmits the information to and from the receiver electronics. There, the information is reconverted, demultiplexed and passed on to trigger and monitoring tasks.

The "MAD", a Full Custom ASIC for the CMS Barrel Muon Chambers Front End Boards

Franco Gonella and Matteo Pegoraro from INFN - Sez. Padova (Italy)

Abstract:

Front end electronics of CMS barrel muon chambers is built around a full custom ASIC, named MAD, designed and developed by INFN Padova, that provides amplification, discrimination and cable driving circuitry for a quadruplet of drift tubes.
The system is organized in compact boards located in the gas volume and includes I2C slow control features for channels enable/disable and temperature monitoring, and a flexible test pulse system for calibration purposes.
Attained results confirm the good performances of the system; particularly, big effort was put in radiation tests (neutron, gamma rays and ions) to check behavior and reliability in LHC environment.

Summary:

Front end electronics of CMS barrel muon chambers is organized in compact boards (Front End Board, located in the detector gas volume) whose fundamental component is a full custom ASIC (named MAD) that provides the primary processing of drift tubes signals. To accomplish the variable size of the chambers two version of FEBs are produced differing in the number of electronic channels: 16 or 20.
The ASIC, 2.5x2.5 mm2 die area, is made using 0.8 µm BiCMOS technology by Austria Mikro Systeme and housed in a TQFP44 package; the chip was designed and developed by INFN Padova.
The task of this IC is to amplify signals picked up by chamber wires, compare them against an external threshold and transmit the results to the acquisition electronics.
The working conditions of the detector set requirements for high sensitivity and speed combined with low noise and little power consumption. Moreover, as the basic requirement for the front end is the ability to work at very low threshold to improve efficiency and time resolution, a good uniformity is also needed for sensitivity and threshold between channels of different chips.
The ASIC implements 4 complete analog chains, each made of a charge preamplifier and a simple shaper with baseline restorer, whose output is compared with an external threshold by a latched discriminator; the output pulses are then stretched by a programmable one shot and sent to an output stage able to drive long twisted pair cables with LVDS compatible levels.
A temperature sensor with sensitivity of 7.5 mV/°K and masking features for disabling noisy channels at shaper stage and check trigger functionality are also included.
Gain value is 3.3 mV/fC in average, constant up to 500 fC input with less than 1% integral nonlinearity; saturation occurs at about 800 fC. Threshold uniformity is very good, the r.m.s. is below 0.6 mV; propagation delay is about 4 ns.
Key characteristics for low threshold operation are noise and crosstalk: bare chips exhibit ENC of 1400 e- (slope of 60 e-/pF) and a value below 0.1% for the latter while complete board increase these two figures to 1900 e- and 0.2% mainly because of input protection network.
Also included in the FEBs are an I2C bus interface to set masks and temperature probe output and a flexible test pulse system for time and trigger calibration. The total power dissipation of the system is very low, below 25 mW/channel.
The reliability of the whole system is presently under investigation regarding ageing and radiation tolerance both critical in a hardly accessible environment as CMS detector: tests performed still now on FEB (accelerated ageing and irradiation with neutrons, ions and gamma rays) show good MTBF characteristics and immunity to latch-up events.

The new ATLAS TRT read-out system

Peter Lichard CERN-EP

Abstract:

The ATLAS TRT detector is very demanding in terms of electronics performance because of the high occupancy of the detector. A new version of the full read-out system, including two new ASICs and the new back-end modules, has been designed and tested successfully at 40 MHz clock rate and high trigger rate on a detector prototype. A description of this system will be given, as well as test results and plan for future scaling.

Summary:

The ATLAS TRT is  a gaseous detector consisting of 420000 straws covering the barrel and end cap regions. It aims at providing tracking information with a good resolution and electron identification. The large occupancy of the detector requires special care on the analogue signal processing to cancel the ion tail signal, data compression and use of high speed digital links. The drift time measurement performed on the front-end electronics is indispensable  for good tracking resolution.
A new prototype of the read-out chain working at 40 MHz has been developed, constructed and tested. The on-detector electronics consists of an 8 channel analogue front end chip containing a fast preamplifier, a tail cancellation circuitry, base line restorer and two discriminators, followed by a 16 channel read-out chips including a 3ns time to digital converter, the level1 trigger pipeline and the readout protocol to extract the data corresponding to a level 1 trigger signal.  The off-detector electronics consists of a new prototype of a scaled down ROD module, which concentrates the data from 832 channels, format the data and apply the zero suppression scheme and make the data available to the data acquisition system through S-LINK; and the new version of a TTC module with a new protocol for controlling the front-end electronics implemented.
A complete description of the different components of this chain is given, as well as test beam results.
A description of a new prototypes of  TTC and ROD modules is presented, including data compression schemes and TTC protocol.

Progress in development of the readout chip for the ATLAS Semiconductor Tracker

W. Dabrowski, Faculty of Physics and Nuclear Techniques, UMM, Krakow, Poland
F. Anghinolfi, CERN, Geneva, Switzerland
A. Clark, University of Geneva, Switzerland
T. Dubbs, SCIPP, UCSC Santa Cruz, CA, USA
L. Eklund, CERN, Geneva, Switzerland
M. French, Rutherford Appleton Laboratory, Didcot, UK
W. Gannon, Rutherford Appleton Laboratory, Didcot, UK
A. Grillo, SCIPP, UCSC Santa Cruz, CA, USA
P. Jarron, CERN, Geneva, Switzerland
J. Kaplon, CERN, Geneva, Switzerland,
J. Kudlaty, MPI, Munich, Germany
C. Lacasta, IFIC, Valencia, Spain
D. LaMarra, University of Geneva, Switzerland
D. Macina, University of Geneva, Switzerland
I. Mandic, Jezef Stefan Institute, Ljubljana, Slovenia
G. Meddeler, Lawrence Berkeley National Laboratory, Berkeley, CA, USA
H. Niggli, Lawrence Berkeley National Laboratory, Berkeley, CA, USA
P.W. Phillips, Rutherford Appleton Laboratory, Didcot, UK
P. Weilhammer, CERN, Geneva, Switzerland
E. Spencer, SCIPP, UCSC Santa Cruz, CA, USA
R. Szczygiel, CERN, Geneva, Switzerland
A. Zsenei, University of Geneva, Switzerland

Abstract :

The development of the ABCD chip for the binary readout of silicon strip detectors in the ATLAS Semiconductor Tracker has turned into a pre-production phase, following comprehensive evaluation of the ABCD2T prototype chip. The ABCD2T design is one of the two options of the binary readout architecture which have been developed for the ATLAS SCT. It is manufactured in the DMILL process and comprises in a single chip all blocks of the binary readout architecture. In the paper we will present a summary of the ABCD2T performance as well as design issues and performance of the ABCD3T chip which is expected to be the final version for the ATLAS SCT detector.

Summary :

The development of the readout chip for silicon strip detectors in the ATLAS Semiconductor Tracker has entered into a pre-production phase, following comprehensive evaluation of the recent ABCD2T prototype chip. The ABCD2T design is one of the two options of the binary readout architecture which have been developed for the ATLAS SCT. It is manufactured in the DMILL process and comprises in a single chip all blocks of the binary readout architecture, the front-end circuits, discriminators, binary pipeline, derandomizing buffer, data compression logic, and the readout control logic as required for the ATLAS SCT. A significant improvement of the chip performance has been achieved by implementation of the individual threshold correction in each channel using a digital-to-analogue converter (TrimDAC) per channel.

Detailed evaluation of the ABCD2T design has been performed employing specific test procedures separately for the analogue and digital blocks. The design meets most of the specification, however, the test results indicate that some corrections and improvements are still possible. In particular, this applies to the TrimDAC circuit which is used for threshold correction in each channel. The response characteristics of this circuit exhibit significant non-linearity which degrades the final uniformity of the threshold. The source of the problem has been identified and corrected in the ABCD3T design.

In parallel to detailed evaluation the ABCD2T design the chips have been used extensively for building prototype SCT detector modules using various hybrid layouts and technologies. This work provided us with a complete evaluation of the chip performance.

The DMILL technology is qualified as a radiation resistant one, however, the radiation levels expected for the SCT detector in the ATLAS experiments are at the upper limits of those specified for the DMILL process, i.e. 10 Mrad of the ionising dose and 1E14 n/cm2 1 MeV eq. neutron fluence. In addition, if one takes into account very advanced requirements regarding the noise, speed and power consumption of the ABCD2T chip, it becomes obvious that radiation effects in the basic devices, although limited, can not be ignored.

Radiation hardness of the chip was evaluated in various tests which covered the total dose effects and the single event upset effects. The performed radiation tests indicated for some potentially weak points in the design. The two most important were a significant increase of the digital power consumption and decrease of the signal level in the token/data passing circuit after total ionising dose of 10 Mrad. Both problems have been traced down to particular circuit structure which are sensitive to drift of device parameters after irradiation. More robust solutions for these particular circuits have been elaborated and implemented in the ABCD3T chip.

In total, 16 wafers with the ABCD2T chips split in two different batches have been manufactured at TEMIC foundry. All the chips were fully tested at the wafer level and detailed analysis of yield and failure modes was performed.

In the paper we will present a summary of the ABCD2T performance as well as design issues and performance of the ABCD3T chip which is expected to be the final version for the ATLAS SCT detector.

Single Event Upset Studies on the APV25 Readout Chip

J Fulcher, G Hall, E Noah , M Raymond
Imperial College, London, UK

D Bisello, G. Marseguerra, J Wyss
Padova University, Padova, Italy

M French, L Jones, Q Morrissey, A Neviani
Rutherford Appleton Laboratory, Didcot, UK

Abstract

The microstrip tracker for the CMS experiment at the LHC will be read out using APV25 chips.  During high luminosity running of the LHC the tracker will be exposed to particle fluxes up to 107 cm2 s-1.  This high rate of particles introduces a concern that the APV25 could occasionally suffer from Single Event Upset (SEU).  In order to evaluate the expected upset rate under these circumstances the APV25 was run under controlled conditions in a heavy ion beam.  This enabled the measurement of the SEU upset cross-section, and hence a prediction of the upset rate in CMS.  The upset cross-section for a range of particle LETs (Linear Energy Transfer) was measured and the referred threshold energy and saturated cross-section was evaluated.  These data are then used to predict the upset rate for the APV25 in the CMS tracker.

Summary

During the research and design phases of the APV chip, much care has been taken to assure a high degree of total dose radiation tolerance.  The chips have been fabricated in AVLSI-RA Bulk CMOS, DMILL and deep sub-micron processes.  Extensive testing has been carried out on representative test structures from various processing runs, and the degree of radiation tolerance of these processes has been thoroughly investigated, including SEU measurements of the APV6 (the bulk CMOS version). However, the susceptibility of the APV25 to SEU was not known.  The new version of the APV has been fabricated in a 0.25 mm technology, in which the SEU effect is not yet well measured, so a full understanding of the implications of these single event effects is imperative.  An investigation of the behavior of the APV25 in a heavy ion beam makes it possible to extrapolate from the data to predict the SEU rate in the final system.

SEU is a non-destructive phenomenon, which affects the digital memory registers that store logic states within the APV.  It manifests itself as a soft error appearing in a device and is caused by the deposition of charge by an ionizing particle.  In the APV25 soft errors could cause a variety of undesirable effects, some of which would result in temporary malfunction and possible loss of data.  In the event of such errors the APV can be reset and after a latency ( ~ 3 ms ), normal operation would resume.  It is clear that an understanding of the upset rate will help in the determination of the required reset rate of the tracker, therefore it is important that this rate be evaluated to enable considered design of this part of the tracker system.

In order to calculate the predicted upset rate in the final system an evaluation of the SEU sensitivity was carried out by placing the APV25 in a beam of heavy ions, at the TANDEM accelerator at INFN Legnaro in Italy and measuring the SEU cross-section.  This was achieved by measuring the beam fluence and LET value along with the number of chip upsets caused by the heavy ion beam during a particular time interval.  Cross-section curves, in the case of heavy ion irradiation, typically represent the cross-section of the device as a function of Linear Energy Transfer (LET) of the bombarding ions.  These curves generally have a threshold LET, where upsets begin to appear, and a saturating cross-section for high values of LET.  These two defining features of the device behavior can then be used to make a prediction of the upset rate for other forms of radiation.  For the CMS tracker, the required calculations are complicated since the particles are typically of single charge and therefore only cause large enough ionization by virtue of nuclear interactions with silicon lattice sites.  Calculations of the cross-section through simulations of such interactions have been performed and form the basis of the SEU predictions in the CMS tracker

The results of the test have provided good measurements giving a threshold LET of around 13 MeV.cm2.mg-1, and the SEU cross-section for important elements of the circuit. Predictions have been made of SEU rates in CMS, of less than 10-6 upsets.chip-1.s-1, which allow detailed planning of the CMS system operation.

An electronic calibration for the readout chain of the ECAL-CMS

Youngwook Baek, Daniel Boget, Pierre Zves Davis, Jean Ditta, Nadia Fouque, Jean Pierre Mendiburu
LAPP Annecy-le-Vieux

Abstract :

A calibration system has been developped in 0.8 µ DMILL technology for ECAL-CMS. It consists of several logic and analogic chips that have been funded, and tested in lab and in irradiation beams.

Summary :

We present the status of the electronic calibration designed for the read-out chain of the CMS-ECAL.

In the LAPP (Annecy, France), we have developed several chips in DMILL 0.8 µ technology to integrate the functionalities dedicated to the electronic calibration. A control chip, receives the signals from outside opto-couplers, it de-serializes and transfers this information to a decoding logical circuit. This one recognizes calibration orders, generates a word  and transfers it to a DAC to select an amplitude or set a trigger to the injector.

The injector builds pulses that have  an amplitude proportional to the order given to the DAC and an exponential decaying shape, identical to the APD’s one. The characteristics of each chip have been measured at LAPP on a chain based on a PC through a Labview program  and VME specific elements. Each chip has been tested under irradiation in running conditions at least up to 1014 neutrons/cm2 and 400 krads in gammas  and proved to be hard at least to 10 years of full LHC luminosity.

Mono-phase cooling system for front-end electronics on the example of the ATLAS TRT detector

Magnus Andersson - Luleå University of Technology Sweden
Pierre Bonneau - CERN
Michel Bosteels - CERN
Jan Godlewski - INP Krakow Poland, CERN

Abstract :

The work presents the results of cooling tests performed for the ATLAS TRT electronics. The test installation and control equipment are described.

A model of a standard cooling unit designed for all ATLAS detectors is also presented together with its modifications corresponding to various limitations connected with experimental zone, magnetic field, limited access and localization of various detectors.

Summary:

The efficiency of cooling system for front-end electronics of TRT end-cap detector was studied both by Finite Element Analysis and experimental tests. A good agreement between the simulations and tests results was achieved. FEA model can predict the temperature of the electronics with a sufficient accuracy in a wide range of heat dissipation (better then 5ºC in 50 to 100 mW/channel range). A mono-phase cooling system was tested experimentally using a unit in which fluorocarbon was used as a coolant. The test results, which will be presented, made it possible to design a final installation.
In the next step various experiments will be included into the final configuration taking into account limitations of the experimental zone.The main goals are as follows: to install a minimum amount of active components in the cavern, to ensure safe and reliable functioning by using systems as simple as possible, enable a distant control and necessary action in the case of problems. The use of a very expensive liquid results also in the necessity of finding a reliable recuperation method.
A cooling unit is designed in such a way that it can function using any tape of liquid and at any temperature. In the ATLAS experiment one can define three distinct temperature zones cooled by mono-phase cooling liquid. On the one hand temperature screens isolating silicon detectors at about -10ºC and TRT at 14ºC, access to both of which is very limited which results in small pipes and as a consequence in high pressure drops. On the other hand, there are the remaining detectors operating at temperatures higher than the dew point in experimental cavern. The access here is less limited enabling the work at the low pressure. Depending on the localization of cooling units it is recommended to equip the pumps with hydraulic motors. Elements and the logic of control are described, while the complete design of a control system will be worked out basing on standards, which will be accepted by the whole ATLAS.

Performance and Radiation Tolerance of the ATLAS CSC On-Chamber Electronics

A. Gordeev, V. Gratchev, A. Kandasamy, P. O'Connor, V. Polychronakos, V. Tcherniatine, K. Vetter
Brookhaven National Laboratory

J. Dailing, N. Drego, D. Hawkins, A. Lankford, Y. Li, S. Pier, M. Schernau, D.Stoker, B. Toledano
University of California, Irvine

Abstract:

The on-detector electronics for the ATLAS Cathode Strip Chamber (CSC) performs amplification, analog buffering, and digitization of the charge signals from individual cathode strips. Working in a high-rate environment (strip hit rate up to several hundred kHz) the system requires a signal-to-noise ratio of 200:1 and a dynamic range of 10 bits. Radiation conditions are: ionizing dose of 4.4 krad/yr and neutron flux of 7x10^12 n/cm^2/yr.
The system consists of 320 chamber-mounted ASM boards serving a total of over 61,000 channels. Performance and radiation tolerance of ASM prototypes will be discussed.

Summary:

The ATLAS Cathode Strip Chambers (CSCs) find the muon position by interpolation of the charge collected in 3 - 5- adjacent strips. The performance requirements are:

- position resolution in the r-theta plane: ~ 50 microns (implies a signal:noise > 200:1);
- position resolution in the r-phi plane: ~ 1.4 mm;
- dynamic range of 10 bits;
- overall rate per chamber: ~ 10^7 Hz;
- analog buffering during the L1 trigger latency;
- deadtimeless readout;
- radiation tolerance to 4.4 krad/yr and 7 x 10^12 n/cm^2/yr.

The on-chamber electronics is organized into 192-channel Amplifier-Storage Module (ASM) boards which have charge-sensitive preamplifier/shapers, switched capacitor array analog memories, analog-digital converters, data serializer/deserializers, current and temperature monitors, calibration, and fiber optic links. The ASMs occupy a volume of about 2300 cm^3, dissipate 30W of power, and generate 1.3 Gb/s of data at the expected maximum trigger rate.

The full system consists of 64 chambers having over 61,000 channels. Beam test results indicate that the required performance can be achieved, even in the presence of high background rates. Results of recent radiation tests will also be discussed.

Off-Detector Electronics for a High-Rate CSC Detector

A. Gordeev, V. Gratchev, A. Kandasamy, P. O'Connor, V. Polychronakos, V. Tcherniatine, K. Vetter
Brookhaven National Laboratory

J. Dailing, N. Drego, D. Hawkins, A. Lankford, Y. Li, S. Pier, M. Schernau, D. Stoker, B. Toledano
University of California, Irvine

Abstract:

The off-detector electronics system for a high-rate muon Cathode Strip Chamber (CSC) is described. The CSC's are planned for use in the forward region of the ATLAS muon spectrometer. The electronics system provides control logic for switched-capacitor array analog memories on the chambers and accepts a total of nearly 37 Gbyte/s of raw data from 64 chambers. The architecture of the system is described as are some important signal processing algorithms and hardware implementation details.

Summary:

The described electronics system supports high-rate muon Cathode Strip Chambers (CSC's) planned for use in the forward region of the ATLAS muon spectrometer. Because the chambers are situated in a severe radiation environment, much of the control and data reduction electronics is located off-detector. All 960 channels of each chamber are read out on every level one trigger. With four 12-bit time samples per channel per trigger and a trigger rate of 75 kHz, the 64 chambers of the CSC system output a total of 27.6 Gbyte/s. A planned ATLAS trigger rate upgrade to 100 kHz pushes the data rate to 36.9 Gbyte/s.
The off-detector electronics performs several operations to reduce the CSC data rate. These operations are carried out in two custom-designed VME modules, the Sparsifier and the Readout Driver (ROD). The full system contains a total of 32 Sparsifiers and 8 ROD's.
The Sparsifier performs simple zero suppression and as well as rejection of pulses that are not aligned in time with the arrival of the level one trigger. The Sparsifier is also capable of applying corrections to the data, such as scaling and pedestal subtraction. The Sparsifier transmits reduced data to the ROD via moderate-rate serial connections. The ROD's principal function is to build a single ATLAS-standard event fragment containing data from all eight chambers it services. The ROD also provides extensive data monitoring and is capable of reducing the data rate, for example, by rejecting neutron hits.
Digital signal processors perform most of the data storage, transfer, and processing functions on both the Sparsifier and the ROD. A single DSP module design, containing a DSP, an FPGA, memory, and glue logic, is utilized in a variety of roles on both the ROD and the Sparsifier.

A simplified and accurate front-end electronics chain for timing RPCs

A.Blanco(1), N.Carolino(1), P.Fonte (1,2), R. Ferreira-Marques (1,3), A.Gobbi (4)
(for the ALICE collaboration)

1-LIP, Coimbra, Portugal.
2-ISEC, Quinta da Nora, Coimbra, Portugal.
3-Departamento de Física da Universidade de Coimbra, Coimbra, Portugal.
4-GSI, Darmstadt, Germany.

Abstract :

Recent advances in electronics and construction techniques have pushed the timing resolution of Resistive Plate Chambers below 50 ps sigma with detection efficiencies close to 99% for MIPs. In this paper we describe a new front-end electronics chain for accurate time and charge measurement in these devices, having in view a possible application in ALICE's T0 counter.

The circuit is built solely from commercially available and inexpensive integrated circuits, featuring a reduced number of components. It includes a fast (2 GHz bandwidth) two-stage amplifier that feeds a fixed threshold discriminator followed by an external TDC. The amplified signal is also buffered into an external ADC for charge digitization.

The chain was tested with realistic test signals from an RPC, yielding a timing resolution around 10 ps sigma for signal charges above 100 fC and a charge resolution of 5 fC.

Summary :

The recent development of timing Resistive Plate Chambers (RPCs) opened the possibility to build large, high-resolution, TOF arrays at a low cost per channel. Previous work has shown timing accuracies below 50 ps sigma at 99% efficiency for single four-gap chambers [1] and an average timing accuracy of 88 ps sigma at and average efficiency of 97% for a 32 channel system [2].

In this paper we describe a new, streamlined, front-end electronics chain for accurate time and charge measurement in these devices. The circuit will be used in future developments aimed to extend the detector size, to include a position sensitive readout and to achieve better timing resolution and rate capability.

The circuit is made solely from commercially available and inexpensive integrated circuits, featuring a reduced number of components. It includes a fast (2.5 GHz bandwidth) two-stage amplifier that feeds a fixed threshold discriminator followed by an external TDC. The amplified signal is also buffered into an external ADC for charge digitization. A full schematic and PCB layout will be included in the final report.

The test setup included a single-gap RPC as a realistic signal source, feeding in parallel two front-end circuits. The time difference between both timing signals was measured by a TDC constituted by an ORTEC 286 TAC, followed by a shaping amplifier whose output was digitized by a LeCroy 2249B peak-sensing ADC. The amplifier gain was adjusted to give to the TDC a 3 ps bin width and a 6 ns time range. The measured time resolution of the TDC was 3.5 ps sigma. The analogue outputs of both channels were digitized by a LeCroy 2249w charge-sensitive ADC. The fast (electron) component of the signal was selected by a 40 ns gate width. The system was calibrated by injection of a set of know charges using one of the test inputs, yielding a sensitivity of 3.3 fC per ADC bin, a digitization range of 6 pC and a charge resolution of 5 fC (1.5 bins) sigma.

The timing accuracy of the system was measured by slicing the charge distribution in several regions, applying a linear slewing correction to each slice and doing a gaussian fit to the corrected time distribution of each slice. The results show that the electronic timing accuracy is close to 10 ps for fast signal charges above 100 fC and it is degraded for smaller charges.

Further tests using electronically generated signals injected into single timing channels were performed to compare the present to the previous version of the front-end circuit (used in [1]), based on a pre-amplifier made with discrete components. The results shown an evident advantage of the new design for the smaller charges.

[1] P. Fonte, R. Ferreira Marques, J. Pinhão, N. Carolino, A. Policarpo, "High Resolution RPCs for Large TOF Systems", preprint CERN-EP/99-115, to be published in Nucl. Instr. And Meth. in Phys. Res.

[2] A. Akindinov et al., "A four-gap glass-RPC time-of-flight array with 90 ps time resolution",. preprint CERN-EP/99-166, submited to the IEEE Trans. Nucl. Sci.

The CMS Tracker APV25 0.25µm CMOS readout chip

M. J. French, L. L. Jones, Q. Morrissey, A. Neviani, R. Turchetta
Rutherford Appleton Laboratory, Didcot, OXON, OX11 0QX, United Kingdom

J. Fulcher, G. Hall, E. Noah, M. Raymond
Blackett Laboratory, Imperial College, London SW7 2AZ, United Kingdom

K. Kloukinas, P. Moreira
CERN, 1211 Geneva 23, Switzerland

N. Bacchetta, D. Bisello, G. Marseguerra, J. Wyss
University of Padova, Italy

Abstract:

The APV25 is the 128-channel readout chip for silicon microstrips in the CMS tracker. It is the first major chip for a high energy physics experiment to exploit a modern commercial 0.25µm CMOS technology. Experimental characterisation of the circuit shows full functionality and excellent performance both in pre- and post-irradiation conditions. The measured noise is significantly reduced compared to earlier APV versions. Automated on-wafer testing of many chips has demonstrated a very high yield. A summary of the design and detailed results from measurements will be presented. Operation of the chip in conjunction with other CMS system components will be described.

Summary:

The chip has dimensions 8mm x 7.15mm. Each APV25 channel contains a preamplifier and shaper, with a 50ns peaking time, followed by a 192 deep memory into which samples are written at 40MHz. Locations of data awaiting readout are flagged so they are not overwritten. Following a trigger, three samples from the memory are processed with the APSP deconvolution filter, which re-filters the data with a shorter time constant.
The APV25 contains system features including programmable on-chip analogue bias networks, a remotely controllable internal test pulse generation system and a slow control interface which allows programmable setting of bias currents and voltages in the amplifier and shaper, choice of operation mode, calibration, latency adjustment and error reporting, etc.
The preamplifier is a charge sensitive amplifier with a PMOS input transistor of dimensions 2000µm/0.36µm and current of 400µA. It consumes 0.9mW and is the dominant contribution to the total APV25 power budget of 2.3mW/channel. The power supplies are +1.25 and –1.25V. A switchable unity gain inverter is used to allow signals of either polarity to be measured. The shaper is an effective CR-RC filter with shaping adjustable over a limited range. The total front end gain of the amplifier is approximately 100mV/MIP (25000e).
The pipeline is a 128 by 192 array of switched capacitor cells. Each cell comprises two transistors, to perform the read or write operation, and a storage capacitor. The pipeline is read out by the APSP processor which is an amplifier with a switched capacitor network in the feedback loop. The ratios of capacitors define the weights used by the deconvolution algorithm.
A 128:1 multiplexer drives the analogue output from the chip which emerges at 20MS/s following a digital header sequence in a current form. Data from two APV25 chips are interleaved at the APVMUX chip to arrive at the final transmission speed of 40MS/s.

Results:

The chip functionality was complete after a single design iteration. However, it was noted that the resistance of the input lines to the amplifier could be reduced so the noise performance of the final version, which is now in fabrication, will improve further on this.
The peak mode pulse shape is a very good approximation to ideal 50ns CR-RC pulse shaping. The deconvolution mode data accurately achieve the short pulse shape expected for single bunch crossing timing. Irradiations have taken place using x-rays, 10MeV electrons and reactor neutrons to fluence levels greatly in excess of those expected in CMS; all results are excellent. Very minor changes in performance are seen after high ionising doses.
Automatic wafer testing of each chip will identify “known good die” which will be cut from wafers and assembled onto hybrids. A system is already in operation  and the time required to test each APV die on the wafer is less than 2 minutes. Measurements from several hundred chips show yields of  perfect chips of more than 80%, which is excellent for a complex circuit of 57mm2 in size.
Single Event Upset studies have been carried out in heavy ion beams which will be presented in an accompanying paper to the workshop.

First results from the ALICE1LHCb pixel chip

K. Wyllie1), M. Burns1), M. Campbell1), E. Cantatore1), V. Cencelli2), P. Chochula1), R. Dinapoli3), S. Easo4),
F. Formenti1), T. Grassi1), E. Heijne1), P. Jarron1), K. Kloukinas1), P. Lamanna3), F. Meddi1), M. Morel1), V. O’Shea4),
V. Quiquempoix1), D. San Segundo Bello5), W. Snoeys1), L. Van Koningsveld1)

1) CERN, Geneva, Switzerland
2) INFN Rome, Italy
3) University and INFN Bari, Italy
4) University of Glasgow, Glasgow, UK
5) NIKHEF, Amsterdam, The Netherlands.

Abstract:

ALICE1LHCb is an integrated circuit to read out silicon pixel sensors used for particle tracking in the ALICE Silicon Pixel Detector or for particle identification in the LHCb RICH. It has been fabricated in a commercial 0.25 micron technology, with consideration given to radiation tolerance, testability and system integration.
Results from the first laboratory measurements are presented. These include characterisation of the front-end, with measurements of noise and threshold uniformity. The functionality of the digital circuitry is described whilst operating the chip in both ALICE and LHCb modes. The use of the serial JTAG interface is outlined, in terms of configuring the chip and testing connectivity at the system level.

Summary:

The ALICE1LHCb chip has been designed to read out silicon pixel sensors used for particle tracking in the ALICE Silicon Pixel Detector or for particle identification in the LHCb RICH.
In ALICE, chips will be bump-bonded to thin sensors mounted on staves forming a barrel geometry, and must be sensitive to minimum-ionising particles. In LHCb, single chips will be encapsulated within the vacuum envelopes of hybrid photon detectors, and must be sensitive to photoelectrons of energy ~20keV.
The architecture of the chip has been designed in such a way that it can be operated in one of two different modes to suit the application. This was presented at LEB99 [1].

The chip has been fabricated in a commercial 0.25 micron technology. Tolerance to total-dose radiation effects is enhanced by the use of an enclosed 'edgeless' transistor layout, and guard-rings are used to eliminate inter-component leakage and radiation-induced latch-up. Special circuit designs are used for memory elements to render them immune to single-event upset.

The chip has a total sensitive area of 12.8mm * 13.6mm, sub-divided into pixel cells of 50 microns * 425 microns. Each cell contains an analog front-end followed by a discriminator, two digital delay units, a FIFO memory and readout logic. First measurements are presented on the performance of the front-end, including the noise levels, channel-to-channel threshold variations and timewalk.

The digital functionality has been tested, with data obtained while operating the chip in ALICE mode with a clock frequency of 10MHz and in LHCb mode with a clock frequency of 40MHz.

The use of the JTAG serial interface is described. This is used both to read and write configuration data into the chip, and to test its connectivity by means of boundary-scanning the input/output pads.

[1] "A Pixel Readout Chip for Tracking at ALICE and Particle Identification at LHCb", 5th Workshop on Electronics for LHC Experiments, Snowmass, Colorado, USA, 20-24 September 1999.

HAMAC, a rad-hard high dynamic range analog memory for Atlas calorimetry

E. DELAGNES, P. BORGEAUD
CEA, DSM/DAPNIA SACLAY, 91191 Gif­sur­Yvette, France.

E. AUGE, D. BRETON, G. MARTIN­CHASSARD, V. TOCUT
LABORATOIRE DE L'ACCELERATEUR LINEAIRE, IN2P3­CNRS et Université Paris­Sud, 91405 Orsay Cedex, France.

J. PARSONS, W. SIPPACH
NEVIS LABORATORIES, COLUMBIA UNIVERSITY, IRVINGTON, NY 10533, USA

Abstract:

An 12 channel analog memory dedicated to the readout of the Atlas liquid argon calorimeter has been developed. Its main function is to sample, at a 40 Mhz rate, the data coming from a three gain shaper, to store it, waiting for the level­1 trigger decision, and then to send it more slowly (5MHz) towards a 12 bit ADC. For each trigger, the ADC will digitize 5 samples. As the system is supposed to present minimum dead time, the write operations will be unceasing even during the read phases. The chip can thus be seen as a simultaneous double random access analog memory array. The read and write addresses are generated by a separate controller chip and sent together with other control signals to the analog memory using low­voltage swings.

In the ATLAS calorimetry, the electronics will have to withstand a total ionising dose higher than 20 krad over a 10 year lifetime. For reliability, the circuit may survive to a total dose of 100krad. Thus the chip has been developed in DMILL technology.

The presentation will highlight the amazing level of performance achieved by this circuit whose dynamic range is far in excess of 13 bits even while undergoing simultaneous write and read accesses.

Implementation of a Digital Time Measurement Chip (DTMROC99)in DMILL for the ATLAS TRT

C. Alexander, F. Anghinolfi, R. Van Berg, N. Dressnandt, T. Ekenberg, Ph. Farthouat, P. T. Keener, N. Lam, D. Lamarra, J. Mann, F. M. Newcomer, V. Ryjov, M. Soderberg, R. Szczygiel, H.H. Williams

Abstract:

A 16 channel digital time measurement and readout chip, the DTMROC99, has been designed and built in DMILL, a BI-CMOS rad-hard process. This chip  is designed to accept low level ternary inputs from the ASDBLR99, a companion analog front end chip, to record the time of arrival of avalanche signals from tracks with 1ns precision as well as to record the detection of Transition Radiation photons in a 144 bit data word. Data is stored in a 3.3us pipeline and transferred to a 13 deep buffer if a Level 1 trigger is decoded.  In addition to its main readout function, the chip provides four threshold voltages and two test pulse outputs for the two ASDBLR's it reads out.  Communication utilizes specially designed LVDS compatable, low power differential inputs and outputs.

DESCRIPTION OF CHIP:

The DTMROC99 is a digital time measurement and readout chip for the ATLAS TRT straw tube detector. It receives 16 channels of differential ternary encoded signals from two 8 channel ASDBLR99 chips. The ternary (3-level) signals are a composite of two binary discriminator output pulses: one unit of current indicating the presence of a charged particle track and a two unit pulse indicating that the track amplitude is large enough to be from transition radiation. (i.e. caused by an electron track.)

In the DTMROC99 chip, these ternary signals are decoded back into separate ``tracking" and ``transition" pulses by TERNARY RECEIVERS. The transition pulses' existence or absence is recorded at 25ns intervals timed by the 40MHz system clock (BC). The tracking pulse is essentially digitized by sampling for its presence or absence every 3.125ns and setting a bit accordingly. In this way an 8-bit word is generated defining the leading edge and width of the tracking pulse to a resolution of 3.125ns. Eight 40MHz clocks (BC1 - BC8) each delayed by the appropriate multiple of 3.125ns are derived from the system clock using a Delay-Locked-Loop (DLL).

This 8 bit time sample word plus the transition-radiation bit are formed into 9-bit words. All 16 channels then form 144 bits for each 25ns time period. This data is stored in a PIPELINE for 132 clock cycles during which time the decision whether or not to retain the data is made. If a trigger signal (Level 1 accept) is sent to the DTMROC99 chip, the data is stored in a DERANDOMIZER, and then read out of the chip as a serial 40MHz data stream under the control of the READOUT CONTROLLER.

All this is under the full control of a COMMAND DECODER which accepts an external serial bit stream and issues the appropriate control signals to the chip sub-blocks.

Special LVDS compatable RECEIVERS and DRIVERS are used to communicate with the outside world to avoid generation of noise near the sensitive ASDBLR99 chip inputs.

In addition, the DTMROC99 also provides two TESTPULSE and four THRESHOLDS for the two ASDBLR99 chips. Testpulse outputs provide a shaped signal to generate a current pulse similar the signal produced by the straw sensor when filled with the TRT optimized Xe/Ar/CO2 mixture. Both the amplitude and delay of these testpulses are programmable. Four six bit DACs provide  a tracking and transition radiation threshold for each ASDBLR.

DESIGN METHODOLOGY

The chip is an assembly of analog and digital blocks contributed by five institutions and integrated at the chip level by a private firm. Analog block performance was confirmed using SPICE and digital blocks were confirmed (and in some cases designed) using Verilog.  Subsequent to design, a Verilog representation for each analog block was written to allow a full hierarchical chip level connectivity representation. This verilog representation was  used to perform basic functionality tests prior to submission and to develop test vectors used to drive the chip tester after fabrication.

VERIFICATION OF THE FINAL DESIGN

Verilog models were specified only for nominal process conditions. Derating factors were applied to account for changes due to process, supply voltage, temperature and radiation effects, but differences between SPICE and verilog calculations led to the conservative and time consuming approach of checking the design using SPICE on the extracted netlist. In practice large interconnected sections were simulated together and the internal parts of some blocks such as the the pipeline were carefully reduced in complexity to allow meaninnful simulation results to be available within a one week time frame.  Using this process several several timing errors were identified and fixed prior to submission. In some cases, the timing was unacceptable only when two or more contitions were not nominal.  These were noted and accepted in order to get
actual experience with the design.

CHIP FUNCTIONALITY

PERFORMANCE

The chip is fully functional and its performance is accurately predicted by simulation tools. Overall, the standard deviation of time bin width is measured to be less than 1ns for all working chips. Ternary input signals as short as 4ns have been reliably detected.

* RADIATION TESTS

No performance degradation was observed after exposure to 1E14 neutrons/cm**2. Proton irradiation to 1e14p/cm**2 has been performed and we are awaiting the return of the exposed parts. In addition, we expect to perform SEU tests in the late spring or summer.

* BEAM STUDIES

A board employing four DTMROC99 chips and eight ASDBLR99's has been designed at CERN to be compatible with the TRT wheel prototype. We intend to use this board to instrument a prototype wheel and test the full readout chain at the CERN H8 beamline this summer.

Total Dose irradiation of a 0.25µm process

M. J. French
Rutherford Appleton Laboratory, Didcot, OXON, OX11 0QX, United Kingdom

I. Dindoyal, G. Hall, E. Noah, M. Raymond
Blackett Laboratory, Imperial College, London SW7 2AZ, United Kingdom

D. Bisello
University of Padova, Italy
 

Abstract

A commercial 0.25µm process will be used for various electronic components of the CMS tracker, one of these being the APV25 readout chip for silicon microstrips. Irradiating and measuring individual transistors is important in assessing the radiation tolerance of the chip. Transistors from two different foundries owned by the same company were irradiated up to doses of 50Mrad(SiO2) with a 10keV X-ray source. Threshold voltage shifts of up to 140mV were observed whilst noise measurements showed very little degradation in the white noise region after irradiation and annealing. Detailed results of both static characteristics and noise will be presented.

Summary

High speed, low noise and low power consumption are some of the requirements placed on electronics for the LHC. The electronic components also have to survive the harsh radiation environment with ionising doses of up to 10Mrad being reached in the inner tracker regions of CMS. The readout system for the silicon microstrips adopted by the CMS collaboration is based on the APV chip series. The APV25 is the latest chip in the series and is designed in a commercial 0.25µm CMOS technology. This paper reports on a total dose radiation study of transistors manufactured by two different foundries (referred to as foundry A and foundry B) employing the same 0.25µm process. The static characteristics and noise of the transistors were measured before and after irradiation and annealing.

The largest noise contribution in the APV25 comes from the input PMOS transistor of the preamplifier, which has dimensions of 2000µm/0.36µm. All the PMOS transistors measured had a width of 2000µm and lengths varying from 0.24µm to 0.64µm. The NMOS transistor measured had dimensions of 2000µm/0.36µm.

An X-ray source was used to irradiate the transistors in steps up to a dose of 50Mrad(SiO2), with measurements being made after each step. The X-ray tungsten tube was operated at 50kV. This, along with the aluminium filtering ensured that 80% of the dose was delivered by radiation around 10keV. During irradiation, the transistors were biased so as to be under normal operating conditions. During the annealing stage, the transistors were biased and kept at a temperature of 100oC.

Measurements of the static characteristics showed threshold voltage shifts of up to 140mV for PMOS transistors. Some annealing of these transistors reduced the shifts to around 90mV. In addition, there was no significant degradation of the sub-threshold slope or the transconductance. The shift in the threshold voltage for the NMOS transistor was 15mV after 50Mrad(SiO2), increasing to 75mV after annealing. There was some small degradation of the transconductance and the sub-threshold slope for the NMOS transistor.  The threshold voltage shifts observed would not significantly affect the functionality of a chip such as the APV25.

Noise measurements were made with the transistors in saturation and in the moderate to strong inversion region with a drain current of 500µA and a drain voltage of 0.5V. A comparison of the noise before and after irradiation for PMOS transistors shows very little difference for frequencies above 1MHz (higher than the corner noise frequency), which is the region of interest.

After a total dose of 50Mrad(SiO2), 5 times higher than the predicted total dose in the CMS tracker, all the transistors from both foundries were fully functional, showing very small changes in static characteristics and no significant increase in noise levels. The results suggest a small difference in oxide quality between the two fabrication runs.

Design of the Front-End Driver card for CMS Silicon Microstrip Tracker Readout.

S.A. Baird, K.W. Bell, J.A. Coughlan, R. Halsall, W.J. Haynes, I.R. Tomalin
CLRC Rutherford Appleton Laboratory, Oxon, UK.
E. Corrin
Imperial College, London, UK.

Abstract:

The CMS silicon microstrip tracker has the order of 10 million readout channels. The tracking readout system employs several hundred off-detector Front-End Driver (FED) cards to digitise, sparsify and buffer analogue data arriving via optical links from on-detector pipeline chips (APVs). This paper describes the baseline design of the Front-End Driver card which is implemented as a 96 ADC channel (10 bits) 9U VME board. At typical LHC operating conditions the total input data rate per FED after digitisation of over 3 GBytes/s must be substantially reduced. The required digital data processing is highly parallel and heavily pipelined and is carried out in several large FPGAs. The process of FPGA digital design using VHDL and design optimisaton with board level simulation together with the tools employed are discussed.

Summary:

The CMS silicon microstrip tracker has the order of 10 million readout channels. The tracking readout system employs several hundred off-detector Front-End Driver (FED) cards to digitise, sparsify and buffer analogue data arriving via optical links from on-detector pipeline chips (APVs). The Front-End Driver card is currently in the final stages of design. The baseline FED design is implemented as a 96 ADC channel (10 bits) 9U VME board. Each ADC channel receives multiplexed data from 2 front end analogue pipelined ASICs (APVs). The essential features of data processing are as follows. In the first stage the amplitude modulated optical data is converted to electrical levels by opto-receiver packages containing PIN diodes and a custom amplifier ASIC. The analogue data is digitised at 40 MHz by 10 bit commercial ADCs.
The data from each ADC is then processed in its own independent digital pipelined processing logic. Following the recognition of the header accompanying each data frame from the APV, pedestals are removed and the common mode is calculated and subtracted. The APV strip data must then be re-ordered before applying the cluster finding algorithm. The final sparsified data from all ADC channels is then collected, formatted and buffered locally before transferal to the next layer of the CMS data acquisition system.
The entire digital logic is programmed in VHDL and implemented in several large FPGAs. The latest tools are being employed in the FPGA design. Extensive use has being made of simulation tools to optimise the level of internal data buffering. Monte-Carlo generated tracker data is also used to test possible hit and cluster finding FPGA algorithms. Hardware-software co-simulation allows the software for the control and monitoring of the FED to be developed and tested in parallel with the hardware design. The importance of adopting standards in the design process to facilitate testing and maintenance of such a large system is discussed.
The FED is designed to operate at the CMS level 1 trigger rate of 100 kHz. The resulting input rate per FED after digitisation of over 3 GByte/s will be reduced to an average output rate per FED of approximately 150 MByte/s at the expected average hit rates in the tracker. The baseline design will have a total of 500 FEDs in the tracker readout system and will provide over 70% of the final CMS data volume.

The Detector Control System for the HMPID in ALICE Experiment at LHC

G. De Cataldo for the ALICE collaboration, INFN Bari, Italy
(email: giacinto.de.cataldo@cern.ch)

Abstract:

The Detector Control System (DCS) of ALICE at LHC will allow a hierarchical consolidation of the participating sub-detectors to obtain a fully integrated detector operation.
The High Momentum Particle Identification Detector (HMPID), based on a Ring Imaging Cherenkov, is one of the ALICE sub-detectors. Its DCS has to ensure the detector configuration, operation in standalone mode for maintenance, monitoring, control and integration in the ALICE DCS.
In this paper a status report of the HMPID DCS is presented. Costs and merits of its implementation in function of the chosen HV and LV systems will also be reported.

Summary:

The detector for LHC experiments will be installed in underground caverns. This removes the possibility of local interventions during the operation of the LHC accelerator. Consequently remote access becomes a primary condition, and in order to operate and control such complex detector an efficient DCS will be mandatory.

From the DCS point of view, the HMPID consists of 4 sub-systems, each one with parameters to be set and/or read out. These sub-systems are:
- LV power supply system,
- HV power supply system,
- Gas system for the multiwire proportional chamber,
- Liquid circulating system for the Cherenkov radiators.

The HMPID DCS, is structured in three well defined layers: process layer, control layer and supervisory layer. The first one consist of sensors, actuators and custom hardware (FEE, LV..); the second  consists of digital-analogue modules interfacing the process layer and supervised by control computer equipment of type PLC (Programmable Logic Controller) connected by a dedicated general purpose LAN, i.e. Ethernet and TCP/IP. The third one consists of a software system based on a server/client model. It is finalised to configure, control and operate the HMPID either integrated in the ALICE DCS or in standalone mode for maintenance and upgrading of the detector.
Since the high number of parameters to deal with in the ALICE DCS, according to the JCOP recommendations, the supervisory software should be based on an industrial product (under selection) running on workstation with NT or LINUX O.S.. Consequently the HMPID DCS will be also based on the same product in order to import it easily in the ALICE DCS.

Whilst we are already running DCS prototypes of the liquid and gas systems, at present the crucial sub-system to be integrated in the HMPID DCS is the LV power supply system.
Some reliable commercial solutions with an OPC server, supporting TCP/IP protocol and matching the electronics power consumption are available, but their costs seems to be rather high if compared with a custom solution.
In the last case however, the custom auxiliary electronics to ensure voltage, current sensing and LV channel switching, would require a non-standard maintenance compared to what is ensured on long term operation by companies which supply crates with proper connectivity and LV modules with complete remote control. Therefore after a market survey we are inclined to adopt a commercial solution based on the CAEN SY1527 (or 527) system as HV-LV power supply system.

Design and Characterization of a DAC for the Slow Control of the Pixel Chip

F. Corsi (*), R. Dinapoli (*)(#), P. Lamanna(*), C. Marzocca(*)
* Dipartimento di Elettrotecnica ed Elettronica - Poltecnico di Bari
# INFN - Sezione di Bari

Abstract :

A digital to analog converter for slow control of pixel front end chip has been designed in a 0.35 um standard CMOS technology to prove the effectiveness of the chosen circuit structures for this application. The DAC provides a total output current variation of about 15uA with an accuracy of 8 bits (LSB=60nA).

The DAC is based on a PMOS current bank (an NMOS of a reasonable size would operate in the weak inversion region for these current levels and would hence be unsuitable for accurate current sources). The bit value determines whether the current corresponding to these bit is switched to the output or not.
The occupied area is about 300um x 300um and total power dissipation is 85uW.  The results of the test measurements performed on the 36 fabricated prototypes show that statistical fluctuations of the output current due to mismatch are negligible compared to the desired accuracy for all the input configurations.

Summary :

To ensure uniformity of all channels in a pixel system containing many readout chips, the bias of each chip has to be controlled individually. This is readily done using on-chip DACs for biasing. This also allows to re-optimize the settings for every chip regularly to compensate for radiation induced variations.
The main specifications for this current output digital to analog converter include area occupation and power dissipation, radiation hardness and accuracy which must be guaranteed in presence of device mismatch and significant irradiation dose.
The proposed DAC structure has been implemented in a standard 0.35 um deep-submicron CMOS technology with special layout techniques to obtain radiation tolerance. The core of the circuit is an array of 2^n-1 elementary current sources realized with PMOS transistors suitably biased and dimensioned to deliver the current Ibit corresponding to the least significant bit of the DAC. Starting from the power available, the desired output current variation, expressed as a fraction of the maximum output current, and the needed accuracy set the value of Ibit and the number of bits of the DAC. For a minimum area design, W=Wmin has been chosen.
The value of the length L and, thus, the overdrive Vgst, have been defined considering the matching properties of the transistors employed as a function of W and L.

The variance of the output current has been expressed in terms of the matching parameters of the technology used and, imposing that this variance is less than Ibit, the minimum length of the elementary current source has been derived. Of course the dimensions of the current source array must be compatible with the total area available, otherwise the number of bits must be reduced.

Global variations of the MOS threshold voltage are compensated by means of an all-PMOS bias circuit based on a threshold extractor. The 2^n-1 elementary current sources are suitably summed in order to obtain the n bit currents, scaled as the powers of two. The DAC configuration is set by means of n PMOS deviators, which send the related bit current toground or to the output stage of the circuit. This stage is needed to rescale the current delivered by the source array to the value required by the application, in our case 10uA, and is based on the concept of current reflector.

Up to now measurement tests have been performed on 22 out of the 36 prototypes manufactured of the 8 bit DAC. The results show that the absolute differential non-linearity error is always less than one half of the minimum output step Ilsb, whose average value is 60nA, thus achieving the 8 bit accuracy. The following table summarizes the main measurement results.

Average offset error                            274nA

Gain variance                                   2.2 %

Max Integral Nonlinearity Error                 118nA

Max Differential Nonlinearity Error             27nA

Measurements on the remaining prototypes are still in progress and radiation hardness characterization of the DAC will take place soon after.

The ALICE Silicon Pixel Detector Readout System

Federico ANTINORI (1), Jaroslav BAN (2), Michael BURNS (1), Michael CAMPBELL (1), Peter CHOCHULA (1, 3), Fabio FORMENTI (1), Tullio GRASSI (4), Alexander KLUGE (1), Pierluigi LISCO (5), Franco MEDDI (1, 6), Michel MOREL (1), Giorgio STEFANINI (1), Kennith WYLLIE (1)
for the ALICE collaboration.

(1) CERN, 1211 Geneva 23, Switzerland
(2) Institute of Experimental Physics, 04353 Kosice, Slovakia
(3) Institute of Experimental Physics, 84215 Bratislava, Slovakia
(4) Formerly CERN, 1211 Geneva 23, Switzerland
(5) Universita degli Studi di Bari, I-70126 Bari, Italy
(6) Universita di Roma La Sapienza, I-00185 Roma, Italy

Abstract:

The ALICE SILICON PIXEL DETECTOR (SPD) is located within the Inner Tracking System (ITS) and is the detector with the highest active channel density and closest to the point of interaction.

Approximately 10 million active electronic channels, contained in a volume of 34 litres, have to be read out and controlled.

Such a high density in an inaccessible position has imposed a high degree of multiplexing to reduce the amount of cabling to a minimum.

This paper will describe the proposed architecture of the readout and control paths.

Summary:

The basic building block of the ALICE SPD is the ladder consisting of a Pixel detector matrix flip-chip bonded to five front end readout chips.

Four ladders are aligned in the beam direction, glued and wire bonded onto a bus to form a 33cm long stave. Two pilot chips are located at the extremities of this bus to perform the readout and control functions and transmit the digital data to a remote Router which will assemble the data for transmission to the DAQ.

Six staves, two from the inner layer and four from the outer, are mounted on a carbon fibre support and cooling sector. Ten such sectors are then mounted together around the beam pipe to close the full barrel. In total there will be 60 staves, 240 ladders, 1200 chips, 9.83 * 10^6 cells or active channels of read out.

Each front end readout chip contains a mixture of analogue and digital circuitry for the readout of 8192 detector cells which are arranged in a matrix of 256 rows by 32 columns. Each cell comprises of a preamplifier/shaper, discriminator, trigger latency delay line, a four event de-randomising buffer and an output shift register.

Acquisition and readout are independent activities which are performed in parallel. Both are controlled by the Pilot chip. The front end chips run as slave devices. The Pilot chip, on receipt of a L1 trigger signal will cause the detector hit pattern to be stored in the first free location of the de-randomising buffer buffer of the front end chip. The L2 decision will determine whether the front end chip is read out or not. A L2Y will cause each Pilot chip to initiate a read out cycle by a sequential addressing of its own ten front end chips. The data from the addressed de-randomising buffer are shifted out of the front end chip into the Pilot chip and serialised for transmission over an optical fibre link to the Router module which will be located outside of the ALICE detector. A L2N will cause the data from the de-randomising buffer to be ignored. In each case the de-randomising buffer location is freed for future use.

Each Router will receive the data from six optical fibre links. Each Router input stage will perform, on the fly, zero suppression of the redundant data before formatting for insertion into the DAQ via the ALICE DDL. The controls for the pilot chips and readout chips will be issued by the Router on reception of the trigger system decisions. The Router also monitors the readout chip de-randomising buffer usage and issues the appropriate busy to the DAQ control. Additional memory is contained to provide multi-event buffering. An additional data path has been supplied to enable spying on the event data.

The control, parameter loading and testing of the front end chip is realised by JTAG. A JTAG controller is incorperated in the Router module. Currently two solutions for making the JTAG connection between the Router module and Pilot chip are under evaluation. Either to use a short copper link of <50 metres or employing a second optical fibre link which would not have such a length constraint.

Updated Design for the ALICE Central Trigger

I.J. Bloodworth [1], G. Di Marzo [2], D. Evans [1], P. Jovanovic [1],
A. Jusko [3], J.B. Kinson [1], A. Kirk [1], V. Lenti [4], M. Luptak [3],
L. Sandor [3], P. Vande Vyvre [2] and O. Villalobos Baillie [1]

for the ALICE collaboration.

1. School of Physics and Astronomy, The University of Birmingham, Edgbaston, Birmingham, UK  B15 2TT

2. CERN, European Organization for Nuclear Research, CH-1211 Geneva 23, Switzerland.

3. Dipartimento di Fisica dell' Universita and Sez. INFN, Bari, Italy

4. Institute of Experimental Physics, Slovak Academy of Sciences, Kosice, Slovakia.

Abstract:

The trigger and data acquisition systems in the ALICE experiment have undergone significant changes in the last year.  This is (i) in response to the incorporation of new detectors, (ii) the result of the use of front-end buffering schemes in the ALICE sub-detectors, and (iii) because of new more pessimistic estimates of the data volume generated by the Time Projection Chamber (TPC). In this report, we review the specification for the updated ALICE Central Trigger and examine how it might be implemented using currently available electronics components.
The User Requirement Document and the Technical Specification for this system are being discussed by the ALICE collaboration.

Summary:

The original trigger concept for the ALICE experiment, as described in the ALICE Technical Proposal, has undergone substantial modifications over the last year as a result of new requirements.  These include the addition of new detectors, the decision by the sub-detector groups to use front-end buffering as a means of reducing peak data flow rates to the data-acquisition system, and new, more pessimistic estimates of the data volume from the TPC.

The first step towards a new description of the trigger system came in 1999 with the definition of the signal sequence for communication between the Central Trigger and the sub-detectors.   Since then, a much more detailed description of the logical operation of the trigger system has been prepared.  Triggers are defined in terms of trigger "classes", the function of which can be explained with a few examples.  A trigger class is identified by a given pattern of trigger inputs, and specified that, if it is activated, a trigger should be sent to a specified set of sub-detectors.

The trigger system in ALICE includes a provision for past-future protection for each sub-detector, to avoid event pile-up.  Each sub-detector has a specific time window inside which past-future protection should be applied.  Past-future protection can be applied uniformly to a trigger class, since the failure of any detector in a class
invalidates the whole class.

The ALICE trigger is based on three trigger levels: L0, L1 and L2.  The L0 trigger is the earliest, and is issued so as to arrive at the front-end electronics for each sub-detector at the latest 1.2 microseconds after the interaction has taken place.  The latency is fixed. It is sent by the quickest possible method, namely a dedicated coaxial cable.  The L1 and L2 decisions are sent using the RD-12 TTC system;  L1 uses channel "A", again with a fixed latency, and L2 is sent as a broadcast using channel "B".  The normal operation of the TTC allows for the transmission of a trigger number following a channel "A" trigger pulse. In ALICE, this is set to be the orbit number and the bunch crossing number, in order to have an event identifier which is
common for all sub-detectors.

Calibration triggers are also being considered.  In most cases, calibrations which cannot be performed outside normal physics runs must nonetheless take place when there can be no collision.  The simplest way to ensure this is to schedule them to take place in the large gap in the LHC bunch structure, when no collisions take place. Calibration requests can be made, which define a special trigger class, typically consisting of just one detector, and the triggers can be flagged so as to allow  the front-end electronics to perform special tasks, e.g. to suspend zero suppression. The method for communicating a calibration request to the Central Trigger is under discussion.

Readout Unit Prototype for CMS DAQ System

G. Antchev, E. Cano, S. Cittolin, S. Erhan,
B. Faure, D.Gigi, J. Gutleber , C.Jacobs, F. Meijers,
E. Meschi, A. Ninane, L.Orsini, L. Pollet, A.Racz,
D. Samyn, N. Sinanis, W. Schleifer, P. Sphicas

CERN Div.EP/CMD, Switzerland

Abstract :

In the CMS data acquisition system, the Readout Unit (RU) is a major element of the Readout Column and it is placed between Front-end Devices (FED) and Builder Data Network (BDN). The RU is intelligent fast buffer for intermediate storage of data before transferring between the levels of the DAQ system. Readout Unit prototype is developed to achieve the CMS DAQ requirement for data input bandwidth of 400MB/sec and data output bandwidth of 400 MB/sec. The new RU prototype based on reconfigurable hardware structure and high-speed standard busses is presented in this paper.

Summary :

The RU prototype is implemented in two physical units called Readout Unit Input Output (RUIO) and Readout Unit Memory (RUM) interconnect together via fast PCI busses. Those are long size 64bit at 33/66MHz PCI boards. The RUM unit contains dual-port memory (up to 512 Mbytes on DIMM's) where data events will be stored. The memory can be accessed through two on-board PCI busses. Those busses can receive an extension board to accept one additional PMC/PCI board. The RUIO unit is also connected to them. A Memory Management Unit (MMU) on board operates with memory as a hard disk. A third PCI bus on RUM and RUIO is used to configure and control the units. This allows both units to be plugged in a standard PCI bus environment as (PC, SUN Stations or Macintosh). The interconnection between the busses is done by on-board 4 way PCI Bridge.

In this sense the three PCI busses can work independently from each other at the maximum bandwidth of 533MB/s each. Using FPGA's components latest generation provide possibilities to implement different functions in RU.

Performance of a new MCM-D technology front­end digital readout

P. Cluzel 1 , R. Della­Negra 1 , M. Goyot 1 , M. Miguet 1 , A. Savoy­Navarro 2
1 IPNL­Universit’e Louis Bernard de Lyon/IN2P3­CNRS, France
2 LPNHE­Universit’es de Paris 6 et 7/IN2P3­CNRS, France

Abstract

A CEE ESPRIT project developed a new MCM­D packaging technology with a view to industrial, biomedical and HEP applications. The objective was to establish a cost­efficient, commercial manufacturing base in silicium­ based MCMs, with active substracts and ball­grid array interconnects. Among the main features are the integration of active and passive components in the substrate and the use of a flip­chip technique and wafer rerouting. The demonstrator built with this new technology is a prototype of a fast digital readout front­end electronics, mixing analogue and digital components. The tests show very high functioning performances.

Summary:

A CEE ESPRIT project developed a new MCM-D technology with a view to industrial, biomedical, and H.E.P. applications. The objective of the overall project was to establish a cost­efficient, commercial manufacturing base in silicium­based MCMs, with active substrates and ball grid array interconnects. The new feature of this technology is the integration of passive and active components in the substrate, which would otherwise be connected to an MCM via wire­bonding. The first level of connection of the standard ICs to the substrate is done using a flip­chip interconnect. The development of a commercial source for wafer rerouting to facilitate flip­chip interconnects also constitutes a major goal.

This MCM-D technology presents several advantages due to the use of an active substrate, the flip­chip technique with wafer rerouting and the BGA as interconnects. The active substrate offers as benefits that there is no need to have chips for single active functions, less discrete components for biasing, loading, decoupling and filtering. Moreover it improves the testability thanks to the integrated test structures. All this reduces the lower layers of the substrate are those of the CMOS process and include the active CMOS cells. The upper layers are those of a complementary process and include up to four aluminium interconnect levels and thin­film passive elements such as tantalum­silicon resistors and silicon nitride capacitors.

The use of a flip­chip technique and wafer rerouting gives a size reduction with the reduction of the length of the interconnects and also a reduction of the power consumption. For the interconnects the use of BGA provides self-aligning properties thus leading to a better production yield, it also makes this technology compatible with standard SMD assembly processes and it permits a large number of I/O's.

A demonstrator was built in order to test most of the properties and potentiality of the developed technology. This MCM­based circuit contains the basic components of a fast digital readout front­end electronics for HEP detectors. The two basic components of this fast digital readout are a low noise preamplifier followed by a 12 bit fast analog­to­digital converter, mixing analogue and digital components. It also includes a PLL and boundary scan cells for the testability of some integrated digital functions associated with the ADC, integrated and SMD passive components.

A VME and LABVIEW based test bench allowed to test the performances of each component separately (analogue and digital) and of the overall readout chain. The results of detailed tests on the functioning of this device, show very high performances in terms of noise, stability, imaging properties and signal processing.

Software developments for the Readout Unit Prototypes for CMS DAQ System

M.Bellato (INFN Sezione di Padova)
G.Antchev, E.Cano, S. Cittolin, B.Faure, D.Gigi, J.Gutleber, C.Jacobs, F. Meijers, E. Meschi, L.Orsini,
L. Pollet, A.Racz,D. Samyn, N. Sinanis,W. Schleifer, P. Sphicas (CERN)
A.Ninane (Université Catholique de Louvain)

Abstract :

In the CMS data acquisition system, the readout unit is a fast buffering device for short term storage of event fragments. It interfaces front end devices and builder data network.

The current Readout Unit prototypes are based on two homegrown hardware boards, the Readout Unit Memory (RUM) and the Readout Unit I/O (RUIO). These boards are equipped with an IOP. Several OS environments for this processor are developed. The software running on those boards will have to setup and control the input and output processes. Fast IOP to host communications are experimented. A software test environment is specifically designed for test and validation of the complex memory management of the RUM.

Summary :

The RUIO and RUM prototypes both include a PLX IOP480, with a PowerPC core. Thoses IOPs are connected to the host (any PCI workstation) through a PCI bridge. The PCI bridge also allows communication from IOP to IOP.

The IOP processor needed an operating system. Therefore, VxWorks is ported to the RUIO environment, and to the RUM environment. An experimental Linux port is also in progress.

The purpose of the IOP is to setup and control the RUM board, and the link elements. In prototyping environments, the IOP on RUIO or RUM can simulate part of the data acquisition system, in order to test individual parts of the RU or event builder. In this context, the host can have a role, and therefore, fast communication between host and RUIO is tested thanks to the hardware FIFOs in the PCI part of the RUIO.

The test software is based on a generic pci board framework. This framework provides cross plateform development capabilities, with very little porting effort from plateform to plateform. An additional GUI is developed with Labview. The supported plateforms are, from now, MacOS, Linux and VxWorks

Impact of Reliability Specification on Electrical System Design
Stan Jaroslawski

Abstract:

Advantages of addressing Reliability issues very early in any electrical system design is emphasised. An example of an impact of the Reliability specification on the design of a power subsystem is described.  The power subsystem is part of  High Resolution Limb Sounder (HIRDLS) instrument which is to be flown in space as part of Chem1 mission. The main component of the subsystem is a power supply designated Power Converter Unit (PCU). The PCU has to meet HIRDLS instrument system a very tight Reliability requirement of 0.99. The PCU must also meet HIRDLS instrument power requirement (220Watts total), be compliant with spacecraft requirements, and NASA specifications.

Summary:

Reliability issue is a very important factor in the design of any electrical system and equally applies to products destined for consumer market and to scientific apparatus. Instrumentation for LHC will comprise vast electronic front end and data readout systems that will need to work with very high operational efficiencies. Prediction of failures will allow preventive maintenance to be done during shutdowns and will be instrumental in maintaining operational functionality of experiments. Reliability analysis will also very valuable in selection of electrical system configurations in critical areas. Reliability of systems is routinely studied in space satellite projects and the authors hope that the experience gained from building space instruments could be applied to LHC electronic systems in critical areas.
In engineering, and in mathematical statistics, reliability has a real meaning but is very dependent on the quality of manufacturing and assembly processes. In space programmes this is addressed by Quality Assurance (QA) based on extensive Product Assurance (PA) plans. PA plans comprise a wide range of manufacturing procedures that ensure a very high quality of workmanship. PA plans also define the strategy for procurement components, components’ quality, and components’ screening levels. The plans also lay down rules for levels of testing of the end products. The design to the reliability specification of the power supply described in this paper was baselined on such premises.
This paper gives an example of the actual completed design of a power supply and emphasises the impact that the reliability specification. The power supply was designed for the instrument called High Resolution Limb Sounder (HIRDLS) which is to be flown in the space mission designated CHEM1. Design of the power supply was based on DC-DC converters. The power supply converts d.c. power provided by the spacecraft at 29Volts (primary power) into power rails at +5Volts, +/-15Volts and +30Volts rails (secondary power). Secondary power is supplied independently to seven HIRDLS subsystems. The power supply’s operational life in space is  five years and its design theoretical reliability is specified at 0.99 . The reliability specification was achieved after investigating a number of the on board DC-DC converter configurations; a single set of converters parallel redundancy, and standby redundancy. Reliability was analysed in each case and the best result was achieved by a configuration based on the standby redundancy. In the analyses the overall mean time between failures of all EEE parts was calculated and applied to formulae derived form Poisson density function f(t) =  lambda e - lambda t. (All converter configurations are to be shown in separate diagrams).
In conclusion the paper hopes to leave a message that electronics systems that are buried in the depth of complicated LHC detectors are just inaccessible as are instruments flying in space. One could argue that the LHC front-end electronics would be exposed to even more hazardous conditions than instrument flown in space (ionising radiation, for instance). It is therefore prudent to include in the design of exciting electronics a measure of reliability analysis in order to extend its life.

Electronic Design Automation tools for high-speed electronic systems

B.J. Evans
E. Calvo Giraldo
T. Motos Lopez

CERN, IT/CE

Abstract:

The LHC detectors will produce a large amount of data that will need to be moved very quickly.  The signal-speeds and interconnect-density involved lead to difficult electrical design problems, particularly regarding signal-integrity issues.

Various commercial Electronic Design Automation programs are now available to address these problems. These include 3-D full-wave electromagnetic-field solvers, SPICE-based circuit-simulation programs and printed circuit board signal-integrity point products. We will show how these seemingly disparate tools can be used in a complementary fashion to provide detailed studies of detector-electronic design. Two case studies will be presented from LHC experiments.

Summary:

This report shows how various EDA tools can be used for high-speed digital design. These will be classified into three main groups: electromagnetic field calculation, circuit simulation and PCB analysis. We will highlight how each is best suited for a particular class of problem.

Field calculation programs are used when a very detailed behaviour of the system is needed. These can be applied to several critical aspects of high-speed electronics design - connectors, cables and packaging - and will provide the most comprehensive model information.  The tools directly solve Maxwells equations for a given 3D (or uniform 2D) structure and a set of boundary conditions.  Two distinct methods are used to solve these problems.  Pseudo-static codes are used to solve structures whose dimensions are much larger than the wavelength considered.  When the structure dimensions are comparable to, or less than the considered wavelength, a full-wave code has to be used with a corresponding increased simulation time.   CERN has available the set of Ansoft tools (Maxwell 2D/3D Field Simulator and HFSS) and LC from Cray Research.

The output from the field-solver tools can be used as models for SPICE-based circuit-simulation programs which allows much faster analyses in the time and frequency domains.  We have made extensive use of the PSpice simulator during our investigations.

Signal-integrity analysis for a PCB presents a different kind of problem.  Here, possibly thousands of signals have to be examined and a full 3D-analysis would lead to impracticably long simulation times. However, simplified models still provide extremely useful what-if analysis in the pre-layout phase as well as the possibility of highlighting possible signal integrity violations at the post-layout stage.  This approach has the advantage that these programs can be very well integrated with traditional design tools. All calculations are made from the board layout itself and automatically include effects due to track widths, dielectrics and board stackup.  The PCB layout itself can also be driven by a set of design constraint rules.  CERN has available the SpecctraQuest programs which are fully integrated with our Cadence PCB tools.

Two case studies will be presented in this paper.  The first examines the ALICE Pixel Backplane where it has been proposed (ref) to use a meshed power and ground plane for the detector PCB.  This has been analysed while considering two opposing constraints - the PCB has to be as transparent as possible to the beam while still retaining sufficient signal and power-supply integrity.

The second example considers a cable design for ALICE's Time Projection Chamber (ref ). Here, crosstalk calculations were made while respecting the required cable mechanical properties.

Minimizing crosstalk in a high-speed cable-connector assembly

B.J. Evans
E. Calvo Giraldo
T. Motos Lopez

CERN, IT/CE

Abstract

This paper presents the detailed signal-integrity analysis results of a connector-cable assembly linking the ALICE Time Projection Chamber (TPC) to its Front-End Electronics.

The goal was to minimize the crosstalk (electromagnetic coupling) between signal lines for a given line to ground capacitance. Both mechanical (cable flexibility and strength) and electrical (fast signal rise-times) design constraints were considered.

The design was analysed using Finite Element Method software tools to extract equivalent circuit models for the connector and cable. We will show how these programs helped us to quickly investigate different cable configurations. The resulting PSpice simulations will be presented.

Digital Implementation of a Tail Cancellation Filter for the Time Projection Chamber of the ALICE Experiment

R.E.Bosch, B. Mota, L. Musa
CERN, Geneva (Switzerland)

FOR THE ALICE COLLABORATION

Abstract:

In the ALICE TPC, the readout chambers are conventional multiwire proportional chambers with cathode pad readout. The pad signal has a rather complex shape, which depends on the details of the chamber and the pad geometry, characterized by a long tail due to the motion of the positive ions. Since the zero suppression has to be done before the data transfer, the high channel occupancy calls for a very precise tail suppression. In order to be compatible with the required dE/dx resolution, a suppression to 0.1% or better of the maximum pulse height, is required. We present a digital implementation of a shortening filter based on the approximation of the tail by the sum of exponential functions.The hardware implementation of the filter is described and the results analyzed.

Summary:

The ALICE TPC, of cylindrical shape, will be 500cm long, subdivided into two drift spaces of 250cm by a central plane, and extends in the radial direction from 84cm radius out to 247cm. The image charge is detected by 570 000 pads located on two readout planes at the cylinder end-caps. The readout planes are based on conventional multiwire proportional chambers with cathode pad readout. The chambers deliver on their pads a current signal with a fast rise time (less than 1ns), and a long tail due to the motion of the positive ions. For every pad, the current is integrated and subsequently shaped by a shaping amplifier. The pulse-height spectrum covering a maximal drift time of 88us is sampled at about 6MHz. The large granularity of the ALICE TPC (about 3 x 10^8 pixels) leads to a large event size (300MByte) and a data volume in the front-end that, at a trigger rate of 200Hz required for the ALICE physics program, is far beyond the limit of the present data handling techniques. Therefore, the zero suppression has to be done in the front-end electronics before the data is transferred to the DAQ system. Moreover, the ALICE TPC will cope with an extremely high charged particle multiplicity. A typical central Pb-Pb event, for instance, will produce about 3x10^4 tracks in the detector acceptance, which correspond to an occupancy of 40% in the inner most regions of the TPC. Therefore, in order to perform effectively the zero suppression, the pile-up effects have to be minimized and, consequently, the long signal tail has to be suppressed very precisely. In order to be compatible with the required dE/dx resolution, a suppression of 0.1% of the maximum pulse height, is required.

The pad signal has a rather complex shape that depends on the details of the chamber and the pad geometry. The 1/t tail behavior from a closed proportional tube is replaced by a bipolar signal due to the particular motion of the positive ions relative to the pad and wire planes. The negative undershoot reaches several per mille of the peak pulse height and falls into the normal drift time regime of a TPC. The measured TPC signal can be fitted, with the required accuracy, by the sum of N exponential functions. The latter can be expressed as the convolution of the initial impulse charge and a signal transfer function corresponding to the sum of the exponential terms. The cancellation of the tail is then realized by deconvolution filtering technique.

The accuracy of the filter realized as analog network is limited by the tolerance of its components. Owing to the poor precision in the matching of the passive elements, provided by the actual integrated circuit technologies, an analog implementation of the filter cannot reach an accuracy of 0.1% if the use of external tunable components has to be avoided. On the other hand, a digital system allows much better control of the accuracy requirements by choosing the word length and type of arithmetic (fixed point versus floating point). Furthermore, a digital system allows flexibility in reconfiguring the digital signal processing operations by changing programmable coefficients. This is indeed extremely important, considering that the exact shape of the signal is known with high accuracy only when the detector is operated. Moreover, this allows some flexibility in the choice of the gas composition and drift field depending on first running experiences. A N-1 order digital filter can be deduced in a way that N-1 of the poles of the signal transfer function are cancelled. The remaining exponential is the fastest and it allows the output to reach 0.1% of the maximum pulse height after 1 to 2 microseconds. Since the digital filter is part of the front-end electronics, it has to be fast, in order to process a new sample each 6MHz clock cycle, and sufficiently small for cost and power consumption reasons. A 16-bit words and fixed-point arithmetic is consistent with the 0.1% accuracy. Preliminary synthesis of a 2nd order filter with the standard cells library of a 0.35um CMOS process leads to a circuit of about 1500 gates, and a propagation delay below 100ns.
This circuit showed the required accuracy on measured detector signals

A front end ASIC for the Dimuon arm trigger of the ALICE experiment

Laurent Royer, Gerard Bohner, Jacques Lecoq
For the ALICE collaboration
LPC Clermont-Ferrand
 

A first prototype of the front-end ASIC dedicated to the trigger detector of the dimuon arm of ALICE has been designed and tested in the Laboratoire de Physique Corpusculaire of Clermont-Ferrand.

This setup is based on the Resistive Plate Chamber (RPC), a gaseous detector which can be operated either in streamer or avalanche mode. The streamer mode has the advantage of providing large signals that can be discriminated without amplification whereas the avalanche mode presents a better rate capability and time resolution with conventional discrimination techniques.

Since we proposed to operate the RPCs in streamer mode in ALICE, we have studied a new discrimination technique in order to obtain a time resolution better than 2ns in this mode. The method used in this dedicated circuit is described, performances and tests results are given, as well as the evaluation done in the test beam of summer 2000.

Summary:

The trigger system of the dimuon arm of the ALICE/LHC detector has to select events containing two muons from the decay of heavy resonances like J/Y or ¡, amongst all background sources. The setup is composed of 72 Resistive Plate Chambers (RPC), a gaseous detector where the electrical charge produced by the crossing of a charged particle is collected on 1-4 cm wide, 35-70 cm long,  strip lines. Almost 21 000 readout channels are necessary to cover the whole detector area.

RPCs are operated in streamer mode in ALICE and  no amplification of the analog signal is needed.  The analog signal picked up on the strips has to be discriminated and then shaped with a width of about 20 ns.  The output signals of all readout channels are sent in parallel through 20 m long cables to the trigger electronics. A sampling at the LHC clock frequency (40 MHz) is performed at this level before the dimuon trigger decision is issued.

Using conventional discrimination techniques, the time resolution is better when using RPC in avalanche mode (commonly 1ns), unless the RPC is operated in streamer mode at quite high running voltages that is not suitable. In order to improve the time resolution in streamer mode, a new discrimination technique called "ADULT" has been studied.

The observation of RPC pulse shapes in streamer mode shows that the streamer signal itself is preceded by a smaller signal, called "avalanche precursor". The streamer signal exhibits important time fluctuations while the avalanche precursor is almost stable.

The ADULT technique exploit this good timing property of the avalanche precursor with the validation by the large streamer signal which is well above any source of noise.  The technique makes use of  two discriminators, with a low threshold (typically 10 mV/50 ohms) at the level of the avalanche precursor and a high threshold (typically 80 mV/50 ohms) at the level of the streamer. It is followed by a coincidence of the two outcoming signals with the time reference given by the low threshold one.

This dedicated discrimination technique has been implemented in a front end chip developed in the "Laboratoire de Physique Corpusculaire" of Clermont-Ferrand. The chosen technology is AMS BiCMOS 0.8mm.

The chip prototype is composed of one channel including the "ADULT" discrimination technique and additional functions :
-an "one-shot" system which prevents the chip from re-triggering during 100ns,
-a remote delay with a range of 50ns,
-a shaper to obtain a 20 ns logical output signal,
-an ECL buffer to drive a 20 m twisted pair cable.

Five packaged chips were delivered in middle of May 2000. The tests in laboratory have shown that each stage of the chip works perfectly. The power consumption is still a little bit high (140mW per channel) but will be decreased by replacing the ECL driver by a LVDS one.
The low threshold discriminator gives the time reference until the delay between the avalanche precursor and the streamer signals reaches 11 ns, which is enough regarding the actual detector pulses.
The 20 ns ECL output signal can be delayed in a range of about 60 ns and the one-shot protection is a little bit longer (138 ns ) than the designed value.

A RPC equipped with 8 of these chips has been tested at the CERN/PS beam area at the beginning of July 2000. First results are presented in this paper, as well as possible improvements and foreseen developments of the chip.

Analogue Read-Out Chip for Si Strip Detector Modules for LHC Experiments
E. Chesi1, J. A. Clark2, V. Cindro3, W. Dabrowski4, D. Ferrere2, G. Kramberger3, J. Kaplon1, C. Lacasta5, J. Lozano1, M. Mikuz3, C. Morone2 S. Roe1, A. Rudge1, R. Szczygiel6, M.Tadel3, P. Weilhammer1, A. Zsenei2
1CERN, 1211 Geneva 23, Switzerland
2University of Geneva, Switzerland
3Jozef Stefan Institute, Ljubljana, Slovenia
4Faculty of Physics and Nuclear Techniques, UMM, Krakow, Poland
5IFIC, Valencia, Spain
6Institute of Nuclear Physics, Krakow, Poland

Abstract

We present a 128-channel analogue front-end chip SCT128A for readout of silicon strip detectors employed in the inner tracking detectors of LHC experiment. The architecture of the chip and critical design issues are discussed. The performance of the chip has been evaluated in detail in the bench test and is presented in the paper. The chip is used to read out prototype analogue modules compatible in size, functionality and performance with the ATLAS SCT base line modules. Several full size detector modules equipped with SCT128A chips has been built and tested successfully in the lab with b particles as well as in the beam test.

Summary:

The LHC operating conditions present a very big challenge to the front-end electronics of Si trackers for experiments designed for high luminosity physics. Historically most collider experiments have so far used full analogue readout front-ends for Si trackers and vertex detectors. This method allows individual treatment of data in each channel with optimised and adaptable software and thereby the most detailed control and monitoring of the whole system. Analogue readout is to a large extent immune to external electromagnetic pickup (common mode) since common mode noise can be fully eliminated with software. The price to pay for this safety is a heavier load on data transmission off the detector over optical links, both in bit rate and in the required number and quality of the links.

The ATLAS Semiconductor Tracker has adopted a binary scheme for the readout of silicon strip detectors as the baseline. The binary architecture allows a more compact design and has the advantage of a much reduced data transfer rate with more chips using a single optical link. This architecture is, however, not immune at all to the common mode noise and so it is very sensitive to the external electromagnetic interference.

In this paper the ATLAS back-up solution, the SCT128A chip will be presented. The SCT128A chip is an example of the analogue readout architecture for silicon strip detectors, which meets all basic requirements of the LHC experiments. It comprises five basic blocks: front-end amplifiers, analogue pipeline (ADB), control logic including derandomizing FIFO, command decoder and output multiplexer. The chip has been manufactured in the DMILL process, the same as used for the binary chip ABCD. The front-end is a fast transimpedance amplifier, using a bipolar input transistor and providing pulse shaping with peaking time of 25 ns.

The design and the performance of the chip will be presented. The basic chip performance have been evaluated in the test bench.  Analogue prototype module consisting of two 6.4 cm x 6.3 cm ATLAS baseline detectors read out by 6 SCT128A chips has been built. The chips are mounted on a ceramic hybrid connected to the sensors in the end-tap configuration. The pitch adapter needed to match the strip pitch of  80 mm and the pitch of input pads on the chip, which is 60 mm, is integrated on the hybrid. The performance of the module, which has been tested with a Ru b- source and in a 100 GeV pion beam, will be discussed.

An optical link for transmission of data from the SCT128A chip using VCSELs is under development. Performance of the prototype analogue optical link used for read out of the analogue module will be presented and discussed.

The CMS Pixel Detector

Danek Kotlinski, Paul Scherrer Institute, Switzerland

Abstract:

In the presentation the readout architecture of the CMS pixel detector will be discussed.
The data rate and volume expected at the full LHC luminosity and it's implication on the readout chip will be presented. The overall pixel readout system  and the integration with the CMS data acquisition system will be emphasized.
The first pixel detector layer will be placed at 4cm from the beam in a very high radiation environment. Some aspects of the radiation hardness and its impact on the readout design will be discussed.

Summary:

The CMS pixel detector consists of 3 barrel layers located at 4.3 cm, 7.2 cm and 11.0 cm. The barrel is 52 cm long and is supplemented by two endcap disks on each side. The detector is equipped with sensor modules which are 1.6 cm wide and 6.4 cm long. Each detector module is readout by 16 chips. The readout chips are organized in 26 double-columns, each consisting of 106 square 150*150 microns pixels.

When pixels in a double-column are hit by a charged particle the time-stamp of the event is recorded in the column time-stamp buffer. For all hit pixels the pixel address and the analog signal are transferred to the column periphery. There the data waits for the arrival of the 1st level trigger. Groups of 8 or 16 readout chips are connected to one readout link. In order to synchronize the data transmission a "token-bit" manager chip is used. This chip, through a token mechanism, controls the access of each double-column to the readout link. It formats data packets by sending a packet header and trailer and also monitors the system and signals errors. Pixel hits confirmed by the trigger are send through the readout link to the readout electronics (FEDs) 100 m away from the detector. For each hit pixel 6 analog signals are send, they include the analog amplitude, chip identification and column and row pixel addresses, with the digital information being analog coded. About 1000 links are used to readout the whole CMS pixel detector.

The clock, trigger and the reset/synchronization signals are send down to the detector from the control modules (FECs). A separate set of links is used for this purpose. These are also used to download various setup parameters (e.g. pixel thresholds) and to communicate slow control messages.

The finite space available on the readout and token-bit chips means that the size of all data buffers must be optimized for the LHC requirements. Extensive Monte Carlo simulations have been performed to select the right buffer sizes and to estimate the data losses. With out present design the total data loss at full LHC luminosity for the pixel barrel detector at 7 cm is about 4%. This includes the data lost due to buffer overflows in the readout chip, lost data packets due to too high trigger burst rates and the 2-clock column dead time. More details will be given during the presentation.

The pixel readout is integrated with the CMS DAQ through the readout unit (RU). The RU module has a detector specific part (FED) with 48 readout links connected to it. About 26 of such units are needed for the whole pixel detector. At the LHC high luminosity about 10000 pixels are hit every 25ns. The average pixel events size is about 50 Kbytes, which at 100 kHz trigger rate corresponds to a 5 Gbytes/s data flow.

The pixel hits can be used in a standalone pixel track finding and primary vertex finding algorithms. Such algorithms could be used in the CMS 2nd and 3rd level triggers.
 

Front-End electronics for ATLAS Pixel detector

Abstract:

The electronics subgroup of the ATLAS pixel detector has pursued an iterative programme of design development over the last 3 years. The initial phase of this demonstrator programme was aimed at realizing ATLAS specification front-end chips using radiation-soft technologies, the designs of which could then easily be adapted for fabrication at rad-hard foundries. First realistic prototypes were designed in 2 parallel efforts (Europe and US) in 97/98, producing a rad-soft AMS prototype (FE-A/FE-C) and a rad-soft HP prototype (FE-B). Throughout 98/99, more than 60 single chip assemblies and 10 electrically functional modules were produced and have been studied extensively in lab and during 7 testbeam periods at SPS. All of the ATLAS requirement issues (except for the radiation hardness) were addressed in detail such as noise, threshold dispersion, timewalk, digital/analog crosstalk, power supply rejection...with very encouraging results. These measurements on both single chip assembly and module are presented. A unified design approach has been adopted for rad-hard front-end chips, i.e. all working on the same design to be implemented in 2 rad-hard processes. The rad-hard designs, namely FE-D for the DMILL process and FE-H for the Honeywell process, maintain the spirit of the demonstrator programme (i.e. pin compatibility, same pixel pitches...) and combine features of both FE-A/C and FE-B. FE-D has been received in Oct. 99 and FE-H will be submitted during summer 2000.

RADIATION TOLERANCE EVALUATION OF THE ATLAS RPC COINCIDENCE MATRIX SUBMICRON TECHNOLOGY

E.Gennari, E.Petrolo, A.Salamon, R.Vari, S.Veneziano
INFN - Sezione di Roma
P.le Aldo Moro 2 - Rome - Italy

ABSTRACT:

The Coincidence Matrix ASIC is the central part of the ATLAS Level-1 Muon Trigger in the barrel region; it performs the trigger algorithm and data read-out. The ASIC will be mounted on dedicated boards on the Resistive Plate Chamber detectors. The chosen technology has to guarantee complete functionality in the ATLAS RPC radiation environment. Radiation tests have to satisfy the radiation tolerance criteria proposed by the ATLAS Policy on Radiation Tolerant Electronics. The ATLAS standard test methods has to be followed in order to guarantee both total dose and single event effects tolerance.
A frequency multiplier ASIC was used for technology evaluation and radiation tests. The chip is a low jitter programmable clock multiplier, realised in 0.25 micron CMOS technology. This frequency multiplier is intended to be used in the Coincidence Matrix ASIC as a macro, to perform the internal clock frequency multiplication. Radiation test results will be presented.

SUMMARY:

The ATLAS level-1 muon trigger in the barrel region makes use of the Resistive Plate Chamber dedicated detector (RPC). The triggering procedure is accomplished through a Low Pt and a High Pt trigger. The Low Pt trigger uses the information generated in the two Barrel Middle RPC stations, while the High Pt trigger uses the result of the Low Pt trigger and the information of the RPC Barrel Outer station. RPC data readout and level-1 triggering are performed by a dedicated chip, the Coincidence Matrix ASIC (CMA). About 4000 CMA chips will be installed on dedicated boards, that will be mounted on the RPC detectors. This chip performs almost all the most relevant functions needed for the barrel trigger algorithm and for the readout of the RPC strips. It makes the right timing settings of the signals, the coincidence and majority operations, the Pt cut on three different thresholds and it acts as level-1 latency memory and derandomizing buffer.
Electronics complete functionality has to be guaranteed in the ATLAS RPC radiation environment. The ATLAS Policy on Radiation Tolerant Electronics defines the minimum dose and fluences which must be tolerated by the electronics, and the maximum rate of soft, hard or destructive Single Event Effects acceptable for the electronics. This level of reliability must be maintained during 10 years of LHC operation. ATLAS standard radiation test methods have to be followed in order to compare test results with the calculated Radiation Tolerance Criteria defined in the ATLAS Policy, so as to qualify the ASIC technology, architecture and design.
A frequency multiplier ASIC was used for CMA technology evaluation and radiation tests. A chip containing the frequency multiplier was released by Fujitsu for test use. The CMA chip will make use of this frequency multiplier as a macro, for generating an internal 320 MHz clock from the external 40 MHz ATLAS clock. The frequency multiplier uses a low jitter Delay Locked Loop (DLL) to provide the output clock, which range is 40-400 MHz (a multiplying factor between 2 and 32 can be programmed). The chip is realised in 0.25 micron CMOS technology, and has a 2.5 V power supply.
Cobalt 60 gamma source and proton source were used for radiation tests. The chip showed a correct functionality during gamma irradiation up to a total dose of 300 kRad (lower then calculated RTC value). No hard or destructive errors were detected during proton irradiation. Only soft Single Event Upset errors were detected. The extrapolated foreseen rate of soft SEU in the RPC detectors is lower then the calculated RTC.
Test results will be presented, as well as radiation test strategies and comparison between different radiation facilities.

APVMUX, An analogue multiplexing chip for the CMS Tracker
M. French, P. Murray, L. Jone (Rutherford Appleton Laboratory)
M. Raymond (Imperial College)

Abstract:

A chip for multiplexing pairs of APV25 chip outputs onto differential analogue cable has been designed. The chip includes SEU tolerant logic to detect and control the APV signal phasing and termination resistors required by the APV25 chip. The termination impedance and switching phase are programmable by I2C and bond control respectively. The design and implementation is outlined and test results presented.

Summary:

The APV25 chip designed for the CMS tracker provides a differential analogue current signal. This must be terminated to ground and in order to match the numbers of optical inks in CMS, pairs of APV25s are required to multiplex onto individual fibres. The fibres are driven by separate driver chips that require a differential voltage input.
The purpose of the APVMUX chip is to provide this function. Each multiplexer chip can take up to eight APV25 signal inputs (the maximum for any hybrid in CMS) and multiplex them in pairs onto four differential lines that communicate to a separate laser driver module where the fibres are driven.
The phasing of the multiplexing function is derived from the trigger and 40MHz clock that drive the APV25s, this ensures the multiplexer is synchronous with the APV25 output signal. The relative phase is also controlled by two bond pads that either reverse the APV order or adjust the skew by half a clock cycle, this ensures that optimal timing may be achieved on the FE modules.
The termination impedance present in the MUX chips is programmable via the I2C interface on the APV module and allows trimming to control the voltage conversion for link gain optimisation.
In order to facilitate efficient use of the APV25 wafers the size of the MUX die was constrained in one dimension. This led to the inclusion of the PLL circuit, formerly presented as a separate chip, included in the same die. This reduced the number of different chips on each FE hybrid by integrating both functions together.
The design was submitted on the April2000 wafer run and results showing pairs of APV25 chips multiplexed together and the function of the phase and polarity control will also be presented.

Id: 106
Corresponding Author: Nancy MARINELLI
Experiment: CMS
Sub-system: Tracker
Topic: Electronics for Trackers

The CMS Tracker  front-end and  control electronics in an LHC like beam test

W.Beaumont(b), M.Bozzo(f), C.Civinini(e), J.Coughlan(k), F.Drouhin(h), P.Figueiredo(d), L.Fiore(c), A.Giassi(j), K.Gill (d), J.Gutleber(d), G.Hall(g), L.Latronico(f), C.Ljuslin(d), M.Loreti(i), C.Maazouzi(l), S.Marchioro(d), N.Marinelli(g), C. Paillard(d), T.Parthipan(k), P.Siegrist(d), L.Silvestris(c,d), I.Tomalin(k), A.Tsirou(d), P.G.Verdini(j), P.Walsham(g),
B.Wittmer(a), A.Zghiche(l,d), F.Vasey (d)

(a) RWTH, I. Physikalisches Institut, Aachen, Germany,
(b) Universitaire Instelling Antwerpen, Antwerpen, Belgium
(c) INFN, Sezione di Bari, Bari,  Italy
(d) CERN, 1211 Geneva 23, Switzerland
(e) INFN, Sezione di Firenze, Firenze,  Italy
(f) INFN, Sezione di Genova, Genova,  Italy
(g) Blackett Laboratory, Imperial College, London SW7 2AZ, United Kingdom
(h) Universite de l’Haute Alsace, Mulhouse, France
(i) INFN, Sezione di Padova, Padova,  Italy
(j) INFN, Sezione di Pisa, Pisa,  Italy
(k) Rutherford Appleton Laboratory, Didcot, OXON, OX11 0QX, United Kingdom
(l) Institut de Recherches Subatomiques, IN2PS-CNRS Strasbourg, France

Abstract:

A complete prototype of the CMS tracker read-out and control system has been built using components that are very close to the final design. The system is based on analogue amplifier and pipeline memory chips (APV), analogue optical links transmitting at 40Mbps and a VME digitisation and data handling board (FED), supplemented by a control system which sets and monitors the components of the system. This system has been successfully operated for the first time under LHC like beam conditions,  in a 25ns structured beam provided by the SPS at CERN,  mainly aiming  to  test the synchronisation of the system and pile-up effects in a high trigger rate environment.
Preliminary results are presented in this paper

Summary:

The CMS Tracker front-end electronics has been designed to operate at the 40MHz LHC machine frequency with low noise level while ensuring adequate bunch-crossing identification.  A first test in an LHC like beam has been successfully performed in order to check the system synchronisation and the effect on the data quality due to the high trigger rate
Four silicon strip detectors of the "standard" Tracker design have been put on the beam line equipped with a total  of 16 APV6 chips. Readout data have been transmitted through analogue optical link to the DAQ interface (two FED-PMC  8 channels ADC)  and data have then been stored in a high performance  objectivity database system
The fast control information (clock and trigger) provided by the global Timing, Trigger and Command system have been distributed by digital optical fibres from the VME mezzanine Front End Controller (FEC).  Local PLL ASICs  (one per silicone module)  allowed the  recovering of the encoded clock and trigger information and the synchronization of all modules, compensating for different cable lengths.  A local ring of controller  ASICs (CCUs) have been used to handle the transitions from high speed optical link to a number of industry standard I2C buses allowing the  decoding of slow control information hence the setting, control and monitoring of  all the parameters required for the proper operation of the front-end ASICs and their ancillary electronics.

Results
The synchronization of  12 APV6  out of  16 was successfully achieved by tuning the PLLs delays.  Synchronicity can be checked by looking online at the address of  the APV pipeline memory cells where data are stored in. When the APVs are synchronous they all show the same address. Four APV6, sitting on different detectors, turned out to be out of synchronization probably because of glitches on the clock or on the trigger line. Further details will  be available after completing the on-going offline data analysis.
Detailed measurements on each analogue optical link have been performed in order to determine the correct settings for the gain on the laser drivers.
The behavior of the APV6  with  triggers close in time has been checked. The APV6 has been designed to accept two consecutive triggers separated by at least two empty 25 ns buckets, commonly labeled "1001" trigger type, ie the minimal separation in time of two consecutive acceptable triggers is 75 ns. Such sequences, which have been measured to be present in 16% of the beam triggers, were selected, using fast logic triggering algorithm, and successfully read and recorded. The readout response of the APV6 to 2 consecutive triggers 75ns apart has been obtained and measured. This is the first observation of this very satisfactory response of electronic channels under the severe LHC like timing conditions.