ID: 5
Corresponding Author: Bruce TAYLOR
Experiment: General Interest
Sub-system: Trigger
Topic: Trigger Electronics
LHC machine timing distribution for the experiments
B.G. Taylor, CERN for the RD12 Collaboration
Abstract:
At the LHC the 40.079 MHz bunch crossing clock and 11.246 kHz machine orbit signal must be distributed from the Prevessin Control Room (PCR) to the TTC systems of the 4 LHC experiments, to the test beam facilities in the West and North areas and to beam instrumentation around the ring.
To achieve this, a single high-power laser transmitter with optical fanout to all the destinations has been installed at the PCR. A standard TTC machine interface (TTCmi) has been developed which receives the signals and can deliver very low jitter timing signals to LHC experiment TTC distribution systems with multiple trigger partitions.
Summary:
At the LHC the 40.079 MHz bunch clock and 11.246 kHz machine orbit signal must be distributed from the Prevessin Control Room (PCR) to the TTC systems of the 4 LHC experiments and to beam instrumentation located at 24 points around the ring. Also, during LHC-structured SPS beam tests, the bunch clock and 43.375 kHz SPS orbit signal must be broadcast to the test beam facilities in the West and North areas.
To achieve this, a single high-power 1310 nm laser transmitter has been installed at the PCR. The bunch clock and the LHC and SPS orbit signals are received from the BA3 Faraday Cage by coaxial cables with galvanic isolation. A VCXO-PLL in the laser transmitter reduces the clock jitter and a synchronizer prevents metastability of the SPS orbit signal, whose frequency swings 29 Hz during acceleration. The 40.079 MHz clock has a constant frequency and before each slow extraction the SPS is rephased to it, just as it will be before each transfer to the LHC when it is used as injector.
The encoded laser transmitter signal is fanned out by a passive optical tree coupler and distributed to all the destinations by singlemode fibres. These distribution fibres are largely underground and preliminary tests over a 13 km link have shown that the diurnal variation in the phase of the received 40.079 MHz clock is very small.
A standard TTC machine interface (TTCmi) has been developed which receives the optical signals at the LHC experiments, decodes the composite signal and reduces the bunch clock jitter to less than 10 ps rms (about 6% of the rms bunch collision length). To compensate for the phase differences in the orbit signal received at different locations around the LHC ring, the TTCmi provides for the phase of the signal to be adjusted throughout the 88.924 µs period in 3564 steps of the bunch-crossing interval of about 25 ns.
The TTCmi incorporates an optical signal monitor and a biphase mark encoder for local TTCtx laser transmitters, which can broadcast the TTC signals to up to 8960 destinations per crate. It can also deliver the low-jitter clocks electrically to multiple TTCex encoder/transmitters at LHC experiments with up to 40 independent trigger partitions.
A TTCmi has been constructed for each of the LHC experiments and units have been installed at the X5 and X7 test beam facilities in the West Area and at H2, H4 and H8 in the North Area. As with the TTC systems at the experiments, the use of a single CERN-wide system for the distribution of the LHC machine timing signals is expected to result in cost savings and operational and maintenance advantages.
ID:7
Corresponding Author: Mikhail MATVEEV
Experiment: CMS
Sub-system: Trigger
Topic: Trigger Electronics
Implementation of Sorting Schemes in a Programmable Logic
Mikhail Matveev (Rice University, Houston, TX 77005)
Abstract:
Trigger systems of each CMS muon subdetector (Cathode Strip Chambers, Drift Tubes, Resistive Plate Chambers) will have a muon sorter unit in their upper parts. We report on a design and simulation results for the following sorting schemes: "3 objects out of 18", "4 objects out of 8", "4 objects out of 24" and "4 objects out of 36". All designs are targeted to a single chip implementation based on Altera 20KE Programmable Logic Devices (PLD). The PLD internal sorting latency varies between 1 and 3 cycles of 40MHz clock frequency. Proposed schemes can be used for the fast sorting at the CMS Muon subsystems as well as other trigger systems at LHC experiments.
Summary:
All experiments proposed at the Large Hadron Collider at CERN require a fast and sophisticated multi-level trigger system for data selection. For example, the main task of Level 1 Trigger System at the Compact Muon Solenoid (CMS) Experiment is to reduce the frequency of events from 40MHz down to 100kHz. Level 1 decision should be made in about 3 us after the interaction in the collision area. There are three major muon subsystems at the CMS: Cathode Strip Chambers (CSC), Drift Tubes (DT), and Resistive Plate Chambers (RPC). Currently it is decided that only four best candidates from each subsystem will be passed to the Level 1 Global Muon Trigger. It is considered that there will be a sorter module at the upper part of each muon trigger subsystem which selects four best candidates from several tens of incoming. We propose a fast and flexible solution which would allow to implement such a sorters. Four sorting schemes are discussed: "3 objects out of 18", targeted to Muon Port Card at the CSC Trigger system, "4 objects out of 8" intended for the RPC Sorting Processor, "4 objects out of 24" for the DT Muon Sorter, and "4 objects out of 36" for the CSC Muon Sorter.
We assume that sorting is based on the value of input patterns: higher ranks correspond to "better" patterns for the purpose of sorting. All schemes are targeted to a single chip implementation in order to reduce the overall sorting latency. Each chip receives 8, 18, 24 or 36 7- or 8-bit input patterns and outputs three or four best along with their 5- or 6-bit addresses. We also assume that all patterns come to sorter chip in parallel being synchronized with the main master clock. Input, output and in some cases intermediate latches provide a reliable synchronous operation and predictable timing. Our task was to provide a reliable operation at 40+Mhz with the minimum latency. Finally we assume that all inputs are not pre-selected (or ranked), but all outputs of the sorter chip should be ranked, or present on the outputs of the sorter chip in descending order.
We focus on the implementation of all sorting schemes in Programmable Logic Devices (PLD) rather than in ASIC. The important advantages of using PLD are low non-recurring fees, reprogrammable features as well as a shorten design cycle. Our designs are targeted to Altera 20KE PLD family. All timing parameters are obtained for the fastest available devices.
All sorting schemes are based on multiple comparisons and data multiplexing. We perform as much comparisons as possible (taking into account the architecture of particular PLD) in parallel at the beginning of sorting in order to reduce the number of steps in sorting tree. In case of (n) input patterns the total number of all comparisons between them in N=n(n-1)/2. N results of comparisons would allow us to obtain (4n) combinatorial signals indicating that the particular pattern is the first, second, third, or fourth best. Further these (4n) signals are used for pattern multiplexing onto chip outputs.
Results of simulation using Altera Quartus software are presented. Sorting "3 out of 18", "4 out of 8", "4 out of 24" and "4 out of 36" can be done inside PLD in one, one, two and three clock cycles of 40Mhz clock frequency respectively.
ID: 17
Corresponding Author: Peter ALFKE
Experiment: General Interest
Sub-system: Trigger
Topic: Trigger Electronics
Recent Progress in Field-Programmable Logic
Peter Alfke, Director, Applications Engineering, Xilinx, Inc
Abstract:
1. Programmable logic for ultra-low power applications. CPLDs operating with a few microamps of supply current, and FPGAs retaining configuration and register content with less than 100 microamps of supply current. An autoranging 400 MHz six-digit frequency counter consumes <2 mA in idle, <40 mA at 400 MHz input frequency.
2. FPGAs with > 1 Mbit of dual-ported on-chip RAM. FIFOs up to 1024 deep, 64 bits wide ( or wider), clocked at >150 MHz with independent read and write clocks
3. LVDS and LVPECL interfaces running at 622 MHz data rate, and recent developments at GHz serial data I/O.
4. Recent and ongoing experiments with radiation-hardened FPGA.
ID: 18
Corresponding Author: Song Ming WANG
Experiment: CMS
Sub-system: Trigger
Topic: Trigger Electronics
Performance of a Prototype Track-Finding Processor for the Level-1 Trigger of the CMS Endcap Muon System
D. Acosta, A. Madorsky, B. Scurlock, S.M. Wang,
University of Florida
A. Atamanchuk, V. Golovtsov, B. Razmyslovich,
St. Petersberg Nuclear Physics Institute
Abstract:
We report on the development and performance of a prototype track-finding processor for the Level-1 trigger of the CMS endcap muon system. The processor links track segments identified in the cathode-strip chambers of the endcap muon system into complete three-dimensional tracks. It then measures the transverse momentum of the best track candidates from the sagitta induced by the magnetic bending. The processor logic for the prototype is implemented in high-density FPGAs and SRAM memory. It receives approximately 3 gigabytes of data every second from a custom backplane operating at 280 MHz. Test results of the prototype are consistent with expectation.
Summary:
The prototype track-finding processor links track segments from individual cathode-strip chambers in the overlap and endcap regions of the CMS muon system into complete tracks. The overlap region is the region that the barrel and endcap muon systems overlap. The processor calculates the transverse momentum (Pt) of the track from the sagitta induced by the magnetic bending, and reports the highest quality tracks to the Level-1 Global Muon Trigger. Each processor handles information from a 60-degree sector in azimuth only.
The processor is pipelined at the LHC bunch crossing rate of 40 MHz. Approximately 500 bits of information from the track segments are sent into the processor every crossing, and the overall latency is 400 ns. The processor consists of a Bunch Crossing Analyser, Extrapolation units, Track Assembly units, a Final Selection unit, and an Assignment unit.
The Bunch Crossing Analyzer (BCA) gathers tracks segments in a window of at least two bunch crossings for the processor to analyze. This feature is important because the barrel muon trigger sends two muons from each chamber in the overlap region to the endcap muon track-finder over consecutive bunch crossings, and the bunch crossing assignment to the track segments of both muon systems is not 100% accurate.
An Extrapolation unit (EU) takes the three-dimensional spatial information from two track segments in different stations, and tests if they are compatible with a muon originating from the nominal collision vertex with a curvature consistent with the magnetic bending in that region. All possible extrapolation categories are performed in parallel to minimize trigger latency. Intermediate results on the extrapolations are shared amongst some EUs to resolve the ambiguity in the association of the azimuth and polar hits when there are two track segments in a same chamber.
A Track Assembly unit (TAU) links successful extrapolations into complete tracks. One TAU performs the linkings for the overlap region, and two TAUs for the endcap region. The Final Selection Unit (FSU) gathers the information from the TAUs, cancels redundant tracks, and forwards the three best distinct tracks to the Assignment Unit (AU).
The AU determines the azimuth and polar coordinates, Pt, sign, and the overall quality for each of the identified muon tracks. The muon Pt is measured using the azimuth angles of the track segments measured in two or three stations. A more accurate Pt measurement for low Pt muons is achieved with the three-station measurement.
Each processor delivers up to three best muon candidates to the Endcap Muon Sorter, which forwards the four best muon candidates to the Level-1 Global Muon Trigger.
The track-finding processor is implemented on a 13-layer 9U VME board. The trigger algorithms of the processor are fully programmable as the BCA, EU, and FSU logic is implemented in high-density Field-Programmable-Gate-Arrays (FPGA) from the Xilinx Virtex family. The TAU and AU are implemented in static RAM (SRAM) memory.
Some tests were performed on the prototype. The measured latency agrees with our estimation. The output from the logic algorithms are consistent with those from our simulation of the prototype. We have also measured the maximum clock rate that the processor can be driven.
ID: 19
Corresponding Author: Kazumi HASUKO
Experiment: ATLAS
Sub-system: Trigger
Topic: Trigger Electronics
First-Level End-Cap Muon Trigger System for ATLAS
K. Hasuko, T. Kobayashi, T. Niki, D. Toya,
Y. Katori (University of Tokyo)
O. Sasaki, M. Ikeno, T.K. Ohska (High Energy
Accelerator Research Organization KEK),
C. Fukunaga, H. Kano (Tokyo Metropolitan University),
H. Sakamoto, S. Nishida (Kyoto University),
H. Kurashige and R. Ichimiya (Kobe University)
Abstract:
We present the first-level end-cap muon trigger system for ATLAS. The system has the main tasks which are to identify bunch crossings and to make trigger decisions for high transverse-momentum muon candidates. It is being developed under requirements on trigger electronics: e.g. trigger rate, latency, acceptable number of tracks, etc. Such the requirements, trigger scheme, and overview of trigger logic are shown in this presentation. Details of the logic are given in the following presentation.
Summary:
The first-level (LVL1) muon trigger system consists of synchronous pipelined processors running at the bunch-crossing rate of 40 MHz. Its main tasks are to identify bunch crossings and to make trigger decisions for high transverse-momentum (Pt) muon candidates. It has to be operated with Pt threshold in the rage of 6-35 GeV. The trigger rate is required to be limited up to 100 kHz at a high luminosity. The latency of trigger decisions at front-end electronics is required to be less than 2.5 us, including 0.5 us for contingency.
High-Pt muons are identified from Resistive Plate Chambers (RPCs) and Thin Gap Chambers (TGCs) in the barrel and end-caps respectively. The ATLAS has air-core toroidal magnets creating magnetic fields for muon detection. A muon is bent in the fields and the information on its charge and momentum is extracted from the deviation of the bending path with respect to the non-bending projection toward the interaction point.
The TGCs with totally about 320K channels are arranged in seven layers (one triplet and two doublets) in each side. A hit signal is read out in r and phi independently. A muon track is identified by requiring coincidence criteria for hits in layers. A track satisfying 3-out-of-4 coincidence in both doublets is labeled as a low-Pt track. If the track also satisfies 2-out-of-3 (1-out-of-2) in a triplet for r (phi), it is labeled as a high-Pt track. The end-cap region is divided into totally 144 trigger sectors. The two highest-Pt tracks should be selected in each trigger sector.
This trigger system consists of four parts, which we call Patch Panel (PP), Low Pt (or Slave Board; SLB), High Pt and Sector Logic (SL).
At first, PPs receive digitized TGC signals to identify the bunch crossing, adjust signal timing and construct trigger segmentation. SLBs follow the PPs to perform coincidence operations for low-Pt tracks.
The results of SLBs are sent to High-Pt Boards (HPBs) to be combined for high-Pt tracks for r and phi separately. The information on r and phi is sent to SL performing r-phi coincidence and final track selection. The results are sent to the rest of LVL1 trigger system to be combined with the information on barrel muon and calorimeter systems. A trigger signal is finally generated and distributed to the front-end readout electronics. All chamber hits are read out from pipeline-clocked buffers on SLBs with event information.
This system also has functionalities to set up various parameters on detectors and trigger logic. These functionalities are totally controlled from outside.
The core logics in PP, SLB and HPB are implemented with full-custom ASICs. SL is implemented with FPGAs so that the r-phi coincidence is fully programmable. This provides the required range of Pt thresholds. The total latency of the end-cap system is less than 2 us, satisfying the requirement.
We will explain the system overview in this presentation and details of the ASICs are given in the other. These two presentations will complete the explanation of the muon end-cap trigger system.
ID: 21
Corresponding Author: Per Gunnar GÄLLNÖ
Experiment: ATLAS
Sub-system: Trigger
Topic: Trigger Electronics
Timing, Trigger and Control distribution and dead-time control in ATLAS
Abstract:
The RD12 TTC system is the backbone for the timing, trigger and control distribution in ATLAS. The last developments of TTC modules as well as their use in ATLAS will be presented.
The strategy for the dead-time control of the experiment will also be presented.
Summary:
The ATLAS readout elements, such as the front-end electronics, the readout drivers (ROD) and possibly the readout buffers (ROB), need the bunch crossing signal (BC) and the level-1 accept signal (L1A). The Timing, Trigger and Control (TTC) system allows the timing and trigger signals to be distributed to the readout electronics elements. The timing signals comprise the LHC clock (BC) and the synchronisation signals (BCR, ECR). The trigger signals include the L1A, test and calibration triggers. The TTC allows the timing of these signals to be adjusted.
The ATLAS TTC system is based on the optical fan-out system developed within the framework of RD12 which allows signals to be distributed from one source to up to 1024 destinations. The system is partitionable and subdetectors can be running with the central ATLAS timing and trigger signals, or independently, with their specific timing and trigger signals. The TTC system receives the LHC 40 MHz clock (BC) and the ORBIT signal from the LHC, the L1A signal from the central trigger processor (CTP), and commands and data from either the CTP or subdetector-specific electronics. A proper encoding allows this information to be transmitted on a single optical link which is fanned out to up to 1024 destinations. At the receiving end, an ASIC decodes the incoming signal and makes available the BC clock, the L1A signal, the ECR and BCR signals, the L1ID and BCID and the user commands and data. Provision is made to adjust the timing of all the signals. The way the TTC system will be used in different subdetectors depends on the specific requirements of each of them. Most of the sub-systems will use more than one partition to allow concurrent running of different parts of the detector in different trigger modes during commissioning or calibration periods.
In ATLAS, the TTC system will be used in different ways:
- In normal running, each TTC partition receives its clock from the LHC and the L1A from the CTP. The BCR is derived from the LHC ORBIT signal. After each L1A, an 8-bit trigger type is forwarded to the destinations as well as (optionally) a 24-bit event ID. The trigger type is formed in the CTP and contains information on what gave rise to an L1A, while the 24-bit event ID is formed in the TTC VME interface (TTCvi). The TTC system can also transmit specific subdetector data and commands without introducing dead time, e.g. test pulses when there are no bunches (LHC gap), front-end parameters (e.g. delay values).
- During commissioning and for test and calibration runs, triggers can be injected locally in each TTC partition.
The ATLAS front-end electronics and readout systems contain many levels of buffering. Information may be lost at any of a number stages of the readout chain if buffers become saturated. Different strategies can be adopted to handle this situation, the two extreme ones being:
- introduce deadtime to avoid uncontrolled information loss;
- accept information loss and build a readout system able to accept incomplete events and possible loss of synchronization.
The first of these strategies has been chosen and it has been decided to introduce deadtime in the Central Trigger Processor in order to:
- easily control and monitor the deadtime of the experiment;
- have a relatively simple and safe readout system relying on the presence of data for every event;
- simplify the front-end electronics systems by imposing an upper limit on the event rate and a minimum time between consecutive events.
ID: 22
Corresponding Author: Hiroyuki KANO
Experiment: ATLAS
Sub-system: Trigger
Topic: Trigger Electronics
Custom chips developed for the trigger/readout system of the ATLAS end-cap muon chambers
H.Kano, C.Fukunaga, Tokyo Metropolitan University,
M.Ikeno, O.Sasaki, T.K.Ohska, KEK (National
Organization for high energy accelerator physics),
R.Ichimiya, H.Kurashige, Kobe University,
S.Nishida, H.Sakamoto, Kyoto University,
K.Hasuko, Y.Katori, T.Kobayashi, T.Niki, and
D.Toya, University of Tokyo
Abstract:
Three custom ASICs are now being developed for the trigger/readout system of the ATLAS end-cap muon chambers. Each chip is the master component in three out of four subparts of the system. Beside the standard circuitry as an ATLAS subsystem, several implementations have been devised in each chip, which are required from various physical and boundary conditions as an electronics system for the end-cap muon chambers. We discuss the implementation of the level-1 muon identification logic as well as these customarily developed data handling technology
Summary:
The trigger/data acquisition (TDAQ) system for the muon end-cap chamber of ATLAS (TGC) is required to be divided into several partitions. This requirement comes from the structure and characteristics of the TGC as a sub-detector of ATLAS. The partitions are installed just on either the detector surface or top of it. All signals are passed through these partitions of so-called Patch-panel, Low-Pt and Hi-Pt in turn to an upper stream.
We have developed three custom ASICs, each of which contains almost all functionality of a partition. By making ASICs for these partitions, we intended to simplify and lighten the overall electronics system. In this system TGC output is used to produce the ATLAS level-1 muon trigger, we must make a trigger generation logic with minimum latency. Thus we also expect to shorten the latency by implementing the trigger logic into ASICs.
The TGC trigger logic uses signals from three sets of total seven TGC layers, which are called triplet, middle-doublet and pivot-doublet from inside to outside. We identify a muon track with these three layers. In the first step we try to find muon with hit signals of both doublets of the pivot and middle. If a signal sequence passes this check, it is labeled as a low-Pt muon track. A check for Hi-Pt is followed using signals of the triplet and the Low-Pt output.
The TGC signals are input at first to the patch panel in which the patch panel ASIC converts the level from LVDS to TTL and adjusts the signal timing in sub-nanosecond precision with a variable delay accomplished by a DLL circuit. The chip also makes synchronization of the TGC signal with own bunch crossing signal.
TGC signals processed in the patch panel are relayed to the Low-Pt. The hit information of signals for relevant TGC layers are made matching with a coincidence matrix embedded in the ASIC. This ASIC contains also the readout system of the TGC data beside the trigger logic that consists of the standard pipeline and derandomizer buffer.
The Hi-Pt system accepts trigger signals produced by the Low-Pt and makes own muon identification with more-or-less the same algorithm with the Low-Pt ASICs. Each Hi-Pt chip recognizes up to six high-Pt tracks. Contrary to the Low-Pt system, the output signal of the Hi-Pt must be transferred over 80 m for further processes. The transfer is done with an optical link with the high speed serial transmission protocol (G-link). In order to reduce data volume to be transferred, we applied a zero suppression mechanism and send the information of max. two highest Pt tracks for the next trigger processing. In principle we can achieve this with two consecutive primary encoding logic clock by clock. Instead we have developed a quick method to select two highest track within a clock. This encoding logic contributes to both reduction of latency and data volume on the G-link.
In the presentation we explain in detail the functionality and necessity of each chip from physical volume, space and latency point of view. The evaluation of the chips must be presented through analyses of both simulation and actual measurement.
Id: 23
Corresponding Author: Ignacy Maciej KUDLA
Experiment: CMS
Sub-system: Trigger
Topic: Trigger Electronics
Readout system for the CMS RPC Muon Trigger
Krzysztof Kierzkowski a), Ignacy M. Kudla a),
Esko Pietarinen b), Michal Pietrusilski a), Krzysztof Pozniak c)
a) Warsaw University, Institute of Experimental
Physics,
b) Univ.of Helsinki Fac.of Science, Helsinki
Institute of Physics HIP,
c) Warsaw University of Technology, Institute
of Electronics Systems
Abstract:
The CMS detector will have a dedicated subdetector (RPC chambers) to identify muons, measure their transverse momenta pt, and determine the bunch crossing from which they originate. Trigger algorithm is based on muon track search and classification in raw data from the RPC chambers. Trigger system can be built in the control room (far away from detector) where all trigger data are concentrated. Dedicated synchronous compression/decompression algorithm is used to sent all data for each bunch crossing via optical links. Readout system uses the same data as Trigger system and will be placed in Trigger Rack. The idea of readout system and its limitations are discussed. Paper includes description of prototype boards and test results on synchronous CERN test beam.
Summary:
Very low rate of the RPC chamber data enables to use a synchronous compression/decompression data algorithm to transfer only the non zero RPC data from the detector to the control room. Original structure of the data is restored from the string of frames received through data link with additional latency on the control room side. Zero suppression included in synchronous compression scheme is the base of RPC readout system.
Structure of readout system is based on results of theoretical analysis performed for station ME1/1( highest level of rate) with regard of own noise 100Hz/cm2 and zero suppression algorithm realized by LMUXes. Assumed, that 48 links are read and losses of trigger efficiency can not exceed 1%.
All electronic boards of readout system are placed in trigger crates and joint from oneself by local bus. Single module of readout system serves 40 optical links and cooperates with one RDPM. Maximum size of event sent to RDPM reaches about 1kB, instead average prospective size of event attains about 300 bytes. Both sizes are considerably less than 2kB page size fixed for CMS experiment and large margin of safety is warranted. Large number of links forced division of system on two functional parts:
- Slave Readout Board ( SRB): compressed data stream from optical links derandomizes synchronously to trigger experiment ( L1Accept). One SRB serves 8 optical links. All SRB work simultaneously,
- Master Readout Board (MRB): in two stages passes concentration of data stored in buffer memories of SLBs: within crates in first phase and for both crates in second phase. First phase is passed by both MRBs simultaneously, instead in second phase MRB possessing DDU interface executes of final data concentration and make these data available to RDPM.
Prototype of the readout system has been realized in Altera CPLD device (10K series) in 1999 and will be (was) tested on synchronous test beam at CERN.
Description of the Slave Readout (SR) and Master Readout (MR) algorithms were realized in AHDL. Slave Readout test board covers two SR modules working in parallel. The input signals of compressed data stream may be fed by two ways (electrically, by front connectors or optically, through the interface of fibre optic link). The Master Readout test board may work autonomously (has internal clock and requires external trigger signal) or co-operates with TTC circuit (additionally stores event number and bunch crossing number). The event packet, stored in event data buffer, is accessible via VME interface (for computer reading system) and standardized DDU interface (via PCI). The Readout test system assumes nominal parameters for CMS RPC trigger and works with a nominal clock 40 MHz (data transmission from Slave boards to Master board via internal bus is performed with 20 MHz).
Id: 24
Corresponding Auhtor: Tony GILLMAN
Experiment: ATLAS
Sub-system: Trigger
Topic: Trigger Electronics
Study of LVDS Serial Links for the ATLAS Level-1 Calorimeter Trigger
G.Anagnostou, P.Bright-Thomas, J.Garvey, R.Staley,
W.Stokes, S.Talbot, P.Watkins, A.Watson
University of Birmingham, Birmingham, UK
R.Achenbach, P.Hanke, D.Husmann, M.Keller,
E.-E.Kluge, J.Krause, K.Mahboubi, R.Megele, K.Meier, U.Pfeiffer, V.Schatz,
K.Schmitt, C.Schumacher, B.Stelzer, O.Stelzer, P.Stock, E.Ulses
University of Heidelberg, Heidelberg, Germany
B.Bauss, K.Jakobs, U.Schaefer, J.Thomas
University of Mainz, Mainz, Germany
E.Eisenhandler, W.R.Gibson, M.P.J.Landon
Queen Mary and Westfield College, London,
UK
B.M.Barnett, I.P.Brawn, J.Edwards, C.N.P.Gee,
A.R.Gillman, R.Hatley, K.Jayananda, V.J.O.Perera, A.A.Shah, T.P.Shah
Rutherford Appleton Laboratory, Chilton, Didcot,
UK
C.Bohm, M.Engstrom, S.Hellman, S.B.Silverstein
University of Stockholm, Stockholm, Sweden
Abstract:
This paper presents an evaluation of the proposed LVDS serial data transmission scheme for the ATLAS level-1 calorimeter trigger. Approximately 7000 high-bandwidth links are required to carry data into the level-1 processors from the preprocessor crates. National Semiconductor's Bus LVDS serialiser/deserialiser chipsets offer low power consumption at low cost and synchronous data transmission with minimal latency. Test systems have been built to measure real-time bit error rates using pseudo-random binary sequences. Results show that acceptable error rates better than 10^-13 per link can be achieved through compact cable connector assemblies over distances up to 20m.
Summary:
The ATLAS level-1 calorimeter trigger requires approximately 7000 high-bandwidth serial links to transfer data from the preprocessor into the algorithmic processor systems. Each processor module must receive data in excess of 4 Gbyte/s over these links, with minimal latency and a bit error rate (BER) better than 10^-10 for each link.
It was originally proposed to use HP G-link chipsets, which have performed well in tests, but do lead to a very high power density on the processor modules. This high power dissipation would require serious attention to module and crate cooling. LVDS links offer much lower power consumption, and the National Bus LVDS serialiser/deserialiser chipsets DS92LV1021/DSLV1210 etc. are easily interfaced to the trigger system while transmitting data synchronously with minimal latency.
Three separate test systems were produced. These involved up to eight channels in parallel, and measured BERs over electrical links using various cable types with lengths from 10m to 20m. Test systems were designed to transmit and check pseudo-random and repetitive data patterns in real-time in order to achieve the statistics required for measurements of very low BERs.
Several types of cable and connector were also evaluated for use within the ATLAS environment. The processor modules will share data via a high-speed backplane, and the LVDS links will be connected through this backplane in order to allow easy installation and replacement of modules. Compact cable assemblies are needed because of the high channel count per module: up to 96 LVDS channels per module are required and each 9U processor module requires up to 830 backplane pins.
The final installation within ATLAS requires inter-crate links over distances of 10m to 15m, and a low BER is crucial for these links in order to minimise false triggers. For minimum latency, only error detection, not correction, is possible. To minimise the error rates, the cable assemblies being considered require some form of equalisation for the attenuation at high frequencies, as the raw data rate on each link is 480 Mbit/s. Both active and passive pre-compensation techniques at the transmitter have been investigated. BERs better than 10^-13 per link have been achieved with cable lengths from 10m to 20m even with simple and straightforward L-R equalisation.
Experience showed that use of these parts was not straightforward, operating as they are at the limit of their specified data rate. The causes of power supply noise must be kept to the minimum, and board layout is critical. In particular, it is important to ensure that the transmitter clock has a low level of jitter. However the problems encountered have been understood and solutions found.
In conclusion, the LVDS links form a viable scheme for transfer of large volumes of data, having the advantages of low latency, low power and low cost. They also offer high-density connectivity, which is essential for compact cable plant. Prototype processors are now being designed that will incorporate a large number of such links.
Id: 28
Corresponding Author: Ralf SPIWOKS
Experiment: ATLAS
Sub-system: Trigger
Topic: Trigger Electronics
A Demonstrator for the ATLAS Level-1 Muon Trigger Interface to the Central Trigger Processor
A. Corre, N. Ellis, P. Farthouat, Y. Hasegawa,
G. Schuler, C. Schwick, R. Spiwoks
CERN
Abstract:
The Level-1 Muon Trigger Interface (MUCTPI) to the Central Trigger Processor (CTP) receives trigger information from the detector- specific logic of the muon trigger. This information contains up to two muon-track candidates per sector. The MUCTPI combines the information of all sectors and calculates total multiplicity values for each of six pT thresholds. It avoids double counting of single muons by taking into account that some of the trigger sectors overlap. The MUCTPI sends the multiplicity values to the CTP which takes the final Level-1 decision. For every Level-1 Accept the MUCTPI sends region-of-interest information to the Level-2 trigger and event data to the data acquisition system. A demonstrator of the MUCTPI has been built which has the performance of the final system but uses a simplified algorithm for calculating the overlap. The functionality and the performance of the demonstrator are presented.
Id: 29
Corresponding Author: Ralf SPIWOKS
Experiment: ATLAS
Sub-system: Trigger
Topic: Trigger Electronics
The Trigger Menu Handler for the ATLAS Level-1 Central Trigger Processor
N. Ellis, P. Farthouat, G. Schuler, R. Spiwoks
CERN
Abstract:
The role of the Central Trigger Processor (CTP) in the ATLAS Level-1 trigger is to combine information from the calorimeter and muon trigger processors, as well as from other sources, e.g. calibration triggers, and to make the final Level-1 decision. The information sent to the CTP consists of multiplicity values for a variety of pT thresholds, and of flags for ET thresholds. The algorithm used by the CTP to combine the different trigger inputs allows events to be selected on the basis of menus. Different trigger menus for different run conditions have to be considered. In order to provide sufficient flexibility and to fulfil the required low latency, the CTP will be implemented with look-up tables and programmable logic devices. The trigger menu handler is the tool that translates the human-readable trigger menu into the configuration files necessary for the hardware, stores several prepared configurations and down-loads them into the hardware on request. An automatic compiler for the trigger menu and a prototype of the trigger menu handler have been implemented.
Id: 30
Corresponding Author: Vladimir POPOV
Experiment: General Interest
Sub-system: Trigger
Topic: Trigger Electronics
Development of HERA-B high-pT level-0 trigger logic system
H.Riege, J.Schutt, R.van Staa
II Institut fur Experimentalphysik Universitat
Hamburg, Germany
V.Popov
Institute for Theoretical and Experimental
Physics, Moscow, Russia
Abstract:
High-pt trigger has been developed for the HERA-B fixed target experiment as complementary option to the basic trigger. It increases considerably the number of B mesons decay channels detectable by the experiment. The high-pt trigger performs fast and effective selection of particles with high transverse momenta. Trigger system includes three layers of gaseous chambers placed in the magnetic field with 19000 readout channels. Hit information is being transfered from the chambers to the trigger logic via high-speed optical link lines. Selection algorithm is performed by the dedicated logic electronics which allows to select O(107) events out of 1012combinations per second. Pretrigger logic consists of a number of sections. Selection capability of the pretrigger logic is on average 16 events from 192000 combinations each 96 ns (time interval between two consequent bunches). Various tests of hardware prototypes have been done. The commissioning of the high-pt trigger logic system is on-going.
Summary:
High-p t trigger has been proposed for the HERA-B fixed target experiment as complementary option to the basic trigger [1]. It increases considerably the number of B mesons decay channels detectable by the experiment and thus the physics program. The high-p t trigger performs fast and effective selection of charged particles with high transverse momenta.
The high-p t trigger provides preliminary selection ('pretrigger') of events and initiates Kalman filter procedure of the first level trigger. The selection procedure based on triple coincidences between signals coming from gaseous chambers. The high-p t pretrigger system organized using approximately 19000 detecting pads of different sizes distributed among three superlayers of chambers mounted in the magnet.
Challenging design of front-end electronics is done. Special low-mass twisted pairs cable has been developed to carry signals from the signal wires to the front-end cards. In order to reduce total amount of material in the fiducial volume of the detector these cables have no additional shield.
The front-end preamplifier cards are mounted on the edge of the detector fiducial area. They based upon the ASD-8 amplifier-shaper-discriminator ASIC [2].
A charged particle traversing the detector fires projective pads in three layers. Logical signals from front-end electronics is being transfered to the pretrigger logic system in serial form via high-speed optical link lines with data rate 800 Mbits/s. Dedicated logic electronics performes selection of 0(10 7 ) events out of a few 10 12 combinations per second. Several predefined coincidence combinations of fired pads are used to produce the pretrigger signal. The result is being transformed into a data stream of initial track parameters and transmitted to the appropriate first level trigger processors.
The high-p t trigger logic electronics is implemented in VME standard. The logic system has sectional structure and is composed of boards of two types - the Pretrigger Board and the Master Card. Each section consists of one Master Card and a number of pretrigger boards. Two processes are running asynchronously in every section - incoming data filtering procedure and serialization-encoding process. Output of the first process is the input for the second one. A pretrigger board fulfils filter procedure for raw input data in order to diminish the data rate to the level acceptable by the next process. Only that information which passed the test for coincidences is being passed to the next, serialization and encoding, procedure.
The master card acquires data from a group of pretrigger boards, completes pretrigger logic task, defines track parameters and sends messages to the appropriate FLT processors.
A pretrigger board accepts signals from 576 pads of six entire rows. Since the board serves entire rows of pads no readout overlapping occurs and no additional 're-mapping' modules are needed.
Selection capability of the pretrigger logic is on average 16 events from 192000 combinations each 96 ns (time interval between two consequent bunches).
The high-p t pretrigger latency is not more than 0:5 mu s.
The trigger logic has flexibility to the selection criteria - coincidence combinations can be easily reprogrammed.
In order to reduce pretrigger rate further optimization of selection algorithm is forseen in the master card. Important additional facilities for monitoring and testing are implemented in the pretrigger logic.
The high-p t trigger prototype has been developed and intensively tested in the HERA-B experiment environment. The first half of pretrigger logic system has been installed. The commissioning of the high-p t trigger system is going on. Some results obtained are presented. The perfomances of the system are discussed.
References
[1] E.Hartouni et al., DESY-PRC 95/01 (January 1995).
[2] F.M.Newcomer, IEEE Trans.Nucl.Sci, 40(1993) 630.
Id: 40
Corresponding Author: Cornelius SCHUMACHER
Experiment: ATLAS
Sub-system: Trigger
Topic: Trigger Electronics
HDMC: An object-oriented approach to hardware diagnostics
V.Schatz, C.Schumacher University of Heidelberg,
Heidelberg, Germany
M.P.J.Landon Queen Mary and Westfield College,
London, UK
Abstract:
A software package has been developed, which provides direct access to hardware components for testing, diagnostics or monitoring purposes. It provides a library of C++ classes for hardware access and a corresponding graphical user interface. Special care has been taken to make this package convenient to use, flexible and extensible. The software has been successfully used in development of components for the pre-processor system of the ATLAS level-1 calorimeter trigger, but it could be useful for any system requiring direct diagnostic access to VME based hardware.
Summary:
Developing electronics involves a fair amount of testing, where direct access to hardware via a computer is required. In addition to low-level test tools like oscilloscopes or logic analysers higher level diagnostic facilties are essential for more complex tests. This includes software to access the developed hardware in an extensive and easy-to-use way to perform diagnostics and monitoring of individual or complete groups of components. Similar functionality is required for later integration in extended hardware and software frameworks.
The presented software package, called HDMC (Hardware Diagnostics, Monitoring and Control), addresses these needs. It provides a library of components for accessing hardware objects like registers, memories or FPGAs on VME modules or within devices not directly accessible to VME, but located on a VME module. It's also possible to access a VME bus via a network connection in a client/server configuration. A graphical user interface based on this library provides hardware access without requiring special knowledge about software development. The library can also be used for more direct access based on compiled or scripting programming languages for testing or integration into other software environments.
HDMC is implemented as a set of C++ classes, representing hardware components in a common framework. This is used to provide common ways to access similar components, to transmit data between components and to handle them in a uniform way. A simple and clean interface for direct hardware access is provided as well as a more abstract one for access through a graphical user interface. Register descriptions are loaded from human-readable configuration files in such a way that a lot of hardware development can be made without the necessity to recompile the software.
The graphical user interface allows construction, manipulation and access to VME modules and other components in a convenient and uniform way. Access to hardware configurations can be built using the interface and changed at run-time. There is also a plot and histogram component and facilities to present special views of hardware configurations like modules and crates.
HDMC supports a variety of UNIX platforms like Linux, Solaris and HP-UX, For VME access several VME single-board computer are supported, running Linux or LynxOS. Platform support could be extended to Windows without major rewrite and addition of other bus systems like CompactPCI is possible without change in the remaining framework or components.
For development of HDMC an open-source process is used. Source code and documentation is publicly available in the internet and it is open for contributions of any interested party.
The software package has proven to be a useful and reliable tool for diagnosing hardware. It has been used for the pre-processor system of the ATLAS level-1 calorimeter system, whose current development activities are based on a flexible VME test system, but other systems in need for a software tool for hardware diagnostic could also benefit from the HDMC software.
Id: 41
Corresponding Author: Giovanna Di MARZO
SERUGENDO
Experiment: ALICE
Sub-system: Trigger
Topic: Trigger Electronics
Specification and Simulation of ALICE DAQ System
Giovanna Di Marzo Serugendo, CERN / Predrag
Jovanovic, School of Physics and Astronomy, University of Birmingham /
Pierre Vande Vyvre, CERN / Orlando Villalobos Baillie, School of Physics
and Astronomy, University of Birmingham
for the ALICE Collaboration.
Abstract:
The Trigger and Data Acquisition System of the ALICE experiment has been designed to support the high bandwidth expected during the LHC heavy ion run. A model of this system has been developed. The goal of this model is twofold. First, it allows to verify that the system-level design is consistent and behaves according to the requirements. Second, it is used to evaluate the theoretical system performances using the measurements done on sub-systems prototypes. This paper presents the specification and simulation of a model of the ALICE DAQ system using a commercial tool (Foresight). This specification is then executed to simulate the system behaviour.
Summary:
The ALICE Trigger and Data Acquisition System (DAQ) system is required to support an aggregate event building bandwidth of up to 2.5 GByte/s and a storage capability of up to 1.25 GByte/s to mass storage. The system must also be able to combine different types of physics events: a slow rate of central triggers generating the largest fraction of the total data volume, together with faster rates of dielectron and dimuon events.
The ALICE DAQ system has been decomposed in a set of hardware and software components. The detailed system design is going on in parallel with the development of prototypes of these components. We wish to verify this design in order to check that it can reach the expected behaviour and the target performances.
However, such a complex system happens to be difficult to verify manually, since there is no corresponding mathematical description. A tool that enables to define a model of the system, and to perform its verification is therefore an extremely valuable help.
This paper presents the formal specification and simulation of the DAQ of the ALICE experiment. The tool used is a modelling and simulation tool, called Foresight. It allows to specify the system by successive decomposition. It enables to describe the system in an abstract manner in order to focus on the functionality and also to refine it by adding the details of its implementation.
The Foresight specification is made of hierarchical data flow diagrams, finite state diagrams, and pieces of a procedural modelling language. The specification provides a unambiguous description of the system. The semantics of the specification provides a model of the system whose behaviour is very close to the behaviour of the system. The verification process is performed during the simulation. It demonstrates the functional correctness of the system.
The Foresight simulation consists of the execution of the specification.
It offers debugging functions like animation of diagrams, breakpoints, and monitor windows. The simulation is used to evaluate the theoretical system performances using the measurements done on sub-systems prototypes. It also enables to perform some analysis such as the system sensitivity to some key parameters. One can also explore other algorithms, and new architectures. This is useful when he final architecture has not yet been defined (as it is the case for ALICE), since it helps to compare architectures or implementation choices.
The current ALICE specification describes the functionality of the whole experiment and of the major sub-systems: Trigger, Trigger Detectors, Tracking Detectors, DAQ, Permanent Data Storage.
Till now focus has been given to the trigger system. The trigger system performance (trigger types rates) has been simulated under different conditions (different buffer sizes for the detectors, and different bandwidth to the DAQ). This has shown the upper limit of each trigger type rate.
Future work will focus on the DAQ performances and the investigation of different architectural choices. The model will be enriched with a more detailed specification of some existing DAQ components such as the ALICE Detector Data Link (DDL) or the DAQ software framework (DATE).
Id: 46
Corresponding Author: Ulrich PFEIFFER
Experiment: ATLAS
Sub-system: Trigger
Topic: Trigger Electronics
The performance of a Pre-Processor Multi-Chip Module for the ATLAS Level-1 Trigger
R.Achenbach, P.Hanke, D.Husmann, M.Keller,
E.-E.Kluge, J.Krause, K.Mahboubi, R.Megele, K.Meier, U.Pfeiffer, V.Schatz,
K.Schmitt, C.Schumacher, B.Stelzer, O.Stelzer, P.Stock, E.Ulses
University of Heidelberg, Heidelberg, Germany
Abstract:
We have built and tested a mixed signal Multi-Chip Module (MCM) to be used in the Pre-Processor of the ATLAS Level-1 Calorimeter Trigger. The MCM performs high speed digital signal processing on four analogue trigger input signals. Results are transmitted serially at a serial data rate of 800 MBd. Nine chips of different technologies are mounted on a four layer copper substrate. Analogue-to-digital converters and serialiser chips are the major consumers of electrical power on the MCM, which amounts to 7.5 Watts for all dies. Special cut-out areas are used to dissipate heat directly to the copper substrate. In this paper we report on design criteria, chosen MCM technology for substrate and die mounting, experiences with the MCM operation and measurement results.
Summary: The ATLAS experiment requires a highly selective trigger system with optimal efficiency. The event selection at ATLAS will be achieved by a three level trigger system. The first level trigger (Level-1) is a fast pipelined system for the selection of rare physics processes. It achieves a rate reduction from the 40 MHz LHC bunch crossing rate down to the Level-1 accept rate of 75 kHz (100 kHz upgrade). This is done by searching for trigger objects within a total Level-1 trigger latency of 2.0 us. The number of presummed analogue calorimeter signals which are used as input to the Level-1 trigger is about 7200.
Regarding the timing constraints and the large number of analogue signals, the Level-1 trigger needs a hard-wired front-end to perform fast signal processing on all analogue input signals in parallel. This system, which is referred to as Pre-Processor system, provides the input data for the Level-1 trigger algorithms and it performs the readout of data on which the Level-1 trigger has based its decision.
The motivation behind the usage of a Multi-Chip Module (MCM) technology inside the Pre-Processor system is the high number of channels, which must be processed by each Pre-Processor board (64 signals), and the high number of semiconductor devices per printed circuit board. Hence, a MCM technology is essential for the Pre-Processor system to realize a compact system architecture. MCMs represent a technique whereby bare dies and their interconnections are combined inside a single package. The MCM contains both analogue and digital devices. In total it comprises nine dies: two dual FADCs, four Front-End ASICs performing the pre-processing, one multipurpose level conversion ASIC (Finco), and two high speed gigabit transmitter dies from Hewlett Packard (Glink) running at 1.6 GBd.
The design process of the MCM multi-layer structure is based on an industrial available production technique for high density printed circuit boards. This process, called TwinFlex, is characterized by its usage of plasma drilled Micro-Vias for interconnection between layers and its combination of small feature sizes and prices.
One of the most challenging tasks in the MCM design is the thermal management. The increasing of the packaging density and the use of high power dies leads to the exponential nature of component failure rates with temperature. Therefore the dies on the MCM need different thermal resistance from the chip to the case. This difference has been achieved by using a thermal cutout for the gigabit serial transmitter and thermal vias for the FADCs. The total power consumption of the MCM is about 7.5 W.
We will present design criteria, chosen MCM technology for substrate and die mounting and experiences with the MCM operation. System measurements will demonstrate the performance of the Pre-Processor relying on this Multi-Chip Module technology.
Id: 52
Corresponding Author: Holger SINGPIEL
Experiment: ATLAS
Sub-system: DAQ
Topic: Trigger Electronics
ATLANTIS - a modular, hybrid FPGA/CPU processor for the ATLAS Readout Systems
Christian Hinkelbein - Institute of Computer Science V, University of Mannheim, Germany Andreas Kugel - Institute of Computer Science V, University of Mannheim, Germany Reinhard Maenner - Institute of Computer Science V, University of Mannheim, Germany Matthias Mueller - Institute of Computer Science V, University of Mannheim, Germany Harald Simmler - Institute of Computer Science V, University of Mannheim, Germany Holger Singpiel - Institute of Computer Science V, University of Mannheim, Germany Lorne Levinson - Weizmann Institute of Science, Rehovot, Israel
Abstract:
ATLANTIS realizes a hybrid architecture comprising a standard PC platform plus different FPGA based modules for high performance I/O (AIB) and computing (ACB). CompactPCI provides the basic communication mechanism enhanced by a private bus. The system can be tailored to a specific application by selecting an appropriate combination of modules. Acceleration of computing intensive ATLAS LVL2 trigger tasks has been demonstrated with an ACB based system. The ATLAS RoD and RoB systems profit from the flexible and highly efficient AIB I/O architecture. Various high speed interface modules (S-Link/M-Link) are supported, allowing up to 28 links per CompactPCI crate.
Summary:
This paper introduces the hybrid FPGA/CPU based system ATLANTIS. Its utilization as a prototype system for investigating further ATLAS Readout Systems is described. The basic concept of ATLANTIS is to support flexibility and scalability on different levels. Due to this ATLANTIS is a modular system based on CompactPCI. Dedicated FPGA boards for computing (ACB) and I/O (AIB) plus a private backplane bus (AAB) for a data rate of up to 1 GB/s are part of the system. Programming of the FPGAs is done either with commercial VHDL tools or the C++ based HDL developed at Mannheim University. For a specific application a certain number and combination of ATLANTIS boards form the desired system. For investigating ATLAS Readout Systems one commercial host CPU along with up to 7 AIBs are used within a CompactPCI crate. Every AIB is able to carry up to four mezzanine I/O daughterboards. Two Xilinx VIRTEX(-E) FPGAs control the I/O ports. The nominal capacity of any of the four channels is 264 MB/s. Each AIB is equipped with 16 MByte SRAM controlled by the FPGAs. The two FPGAs of each AIB are connected both to the host CPU via the PCI bus and to every other AIB within one crate using the private bus. In the context of the ATLAS LVL2 trigger ATLANTIS has already shown its versatility and potential based on the ACB modules. Two further, high performance I/O applications in conjunction with the ATLAS Readout Systems utilizing the new AIB modules are presented in this paper: The use as a Readout Driver (RoD) and as a Readout Buffer (Rob Complex) prototype system. Both applications profit from the flexible and highly efficient ATLANTIS I/O architecture. The RoD acts as interface between detector and RoB. AIBs equipped with 2 SLinks/GLinks perform the I/O task with up to 160 MByte/s per link. Format conversion and zero-suppression is done "on the fly" by the FPGAs, prior to transmission. The AAB private bus is used for concentrating event data from different AIBs to one output port. The RoB Complex tasks are similar to the RoD tasks but more complex. Data fragments from a variable number of input links have to be assembled, temporarily stored and transmitted via a network interface upon request. A high speed buffer management is essential for this application and implemented on the AIB boards. The host CPU is used to steer the AIBs and to handle requests from the network. It may also provide additional computing power. To achieve a high density of links up to 4 M-Link interfaces can be used per AIB. Local control of the 4 input channels and collection of fragments per AIB help to decrease the frequency of control messages and data packets which significantly improves PCI bandwidth. Two ATLANTIS systems comprising ACB(s) and AAB modules plus a PC-compatible host CPU are available since autumn 1999. Also 4 M-Link modules are ready for use. Four AIBs are in manufacturing phase and expected to be available in June 2000.
Id: 55
Corresponding Author: Bjorn SCHWENNINGER
Experiment: General Interest
Sub-system: General Interest
Topic: Trigger Electronics
The Muon Pretrigger System of the HERA-B Experiment
M.Adams (Universitaet Dortmund), P.Bechtle (Universitaet Dortmund), P.Buchholz (Universitaet Dortmund), C.Cruse (Universitaet Dortmund), U.Husemann (Universitaet Dortmund), E.Klaus (Universitaet Dortmund), N.Koch (Universitaet Dortmund), M.Kolander (Universitaet Dortmund), I.Kolotaev (ITEP Moscow and Universitaet Dortmund), H.Riege (Universitaet Hamburg), J.Schuett (Universitaet Hamburg), B.Schwenninger (Universitaet Dortmund), R.van Staa (Universitaet Hamburg), D.Wegener (Universitaet Dortmund)
Abstract:
The muon pretrigger system of the HERA-B experiment is used to find muon track candidates as one of the inputs of the first level trigger. Due to the interaction rate of 40 MHz required to achieve an accuracy of 0.17 on sin(2beta) the total input of the muon pretrigger system is about 10 GBytes/s. The latency to define muon track candidates should not exceed 1 microsecond. Therefore the muon pretrigger is implemented as about 100 large size VME modules in a highly parallelized architecture.
We will present the system as well as performance studies and first physics results.
Summary:
The HERA-B experiment at the proton electron collider HERA at DESY, Germany, is designed to study the properties of B mesons with the main emphasis on CP violation. The B mesons are produced by hadronic interactions of protons with an energy of 920 GeV in a fixed wire target. An interaction rate of 40 MHz at an effective bunch crossing rate of 8.5 MHz is required to achieve an accuracy of 0.17 on sin(2beta). This leads to about 200 charged tracks per event in the detector and occupancies up to 20%. Therefore a highly selective and efficient trigger system is needed to suppress the background. It consists of four levels, the first level being a hardware trigger while the higher levels are software based using computer farms. The first level trigger (FLT) including the pretrigger systems must not exceed a latency of 10 microseconds and give a reduction of the input rate by a factor of 200 without causing deadtime. To meet these requirements it performs a track search algorithm either for high pT hadron, electron, or muon tracks, followed by a momentum and charge determination. Then the di-lepton invariant masses are calculated and adjustable cuts are applied.
The track searching of the FLT is being initiated by three distinct pretrigger systems, one of which is the muon pretrigger. It uses the hit information of two adjacent layers of muon chambers to define muon track candidates by means of a coincidence scheme. The building blocks of the muon pretrigger system are approximately 100 VME modules of three different types.
The pretrigger link boards (PLB) transfer the data used by the coincidence algorithm from the data buffers near the detector to the processing units of the muon pretrigger over a distance of 50m. The PLB also adds information to tag the detector data with an identifier to allow for an asynchronous data processing in the trigger system. The data are serialized and transferred via 800 MBit/s optical links to the pretrigger coincidence units (PCU). The main task of the PCU is to execute the coincidence algorithm. Therefore the input data from the PLB boards - amounting to about 20 GBytes/s in total - have to be partially duplicated and distributed to CPLDs which perform the main parts of the algorithm. The processing on the PCU takes place at a rate of 25 MHz. After serializing the coincidence data a pretrigger message generator (PMG) board translates it by means of look-up tables into messages for the FLT processors. These messages contain the track parameters and event identifiers used as starting points for the FLT tracking algorithm.
All muon pretrigger hardware is being operated in HERA-B since end of 1999 and used for triggering. We will present the system as well as results on its performance, which are achieved both from monitoring functions accessing the hardware and from archived event data. Also measurements of the efficiency and inefficiency will be shown, as well as first physics results using the muon pretrigger system.
Id: 57
Corresponding Author: Max URBAN
Experiment: General Interest
Sub-system: Trigger
Topic: Trigger Electronics
First Level Trigger for H1, using the latest FPGA generation
M. Urban, A. Rausch, U. Straumann Physikalisches Institut Universitaet Heidelberg
Abstract:
To cope with the higher luminosities after the HERA upgrade, H1 builds a set of new MWPCs, which provide information to distinguish between beam background and true ep interactions. The first level trigger uses the latest 20K400 APEX FPGAs with 500 user IO pins to find tracks in 10000 digital pad signals. It allows to reconstruct the vertex and cut on its position. The system works deadtime free in a pipelined manner using 40 MHz clock frequency. The pipelines needed for data acquisition are also programmed into the same FPGAs. Test results including timing stability will be shown.
Id: 59
Corresponding Author: Dave NEWBOLD
Experiment: CMS
Sub-system: Trigger
Topic: Trigger Electronics
An FPGA-based implementation of the CMS Global Calorimeter Trigger
J. Brooke (University of Bristol) D. Cussans (University of Bristol) G. Heath (University of Bristol) A. J. Maddox (Rutherford Appleton Laboratory) D. Newbold (University of Bristol, Corresponding Author) P. Rabbetts (Rutherford Appleton Laboratory)
Abstract:
We present a new design for the CMS Level-1 Global Calorimeter Trigger, based upon FPGA and commodity serial link technologies. For each LHC bunch-crossing, the GCT identifies the highest pt electron, photon and jet candidates; calculates scalar and vector total transverse energies; performs jet-counting, and provides real-time luminosity estimates. The pipelined system logic is implemented using 0.18um Xilinx FPGAs. The traditional system backplane is replaced by fast serial links for trigger data, and Ethernet for control. These technologies allow an improvement in system flexibility and a considerable reduction in cost, complexity and design time compared to an ASIC/VME-based solution.
Summary:
The CMS Level-1 Global Calorimeter Trigger is the final component in the CMS calorimeter trigger chain. It reduces the data flow to the Level-1 Global Trigger by sorting the various categories of calorimeter trigger objects to find those with the highest transverse momentum. It calculates the scalar and vector total transverse energy for each LHC bunch-crossing to allow missing-energy triggers, and provides an indication of jet multiplicity to the Global Trigger to allow multi-jet triggers. The GCT will also perform luminosity monitoring in real time on a bunch-by-bunch basis, based on high-pt jet multiplicities, global energy flow measurements, and other signals.
The system design has recently been reviewed, and a new approach based upon high-performance commodity technologies has been proposed. The custom ASICs previously used for the sort, energy calculation, and other functions, are replaced by 0.18um Xilinx Virtex-E FPGAs. The system backplane is replaced by fast inter-board serial links based on a National Semiconductor Channel Link chipset, along with ethernet for system control and monitoring. The VME crate controllers are replaced by embedded processors on every trigger board, running the Linux operating system. The new system includes improved self-test capability, including JTAG for chip-level diagnosis. Taken together, these technologies allow an extremely flexible and modular system design; the entire range of trigger processing functions are implemented using seven identical boards, differentiated only by the FPGA programs. The cost and design time advantages of such an approach are highly significant. There are also benefits for the software creation and hardware and software debugging tasks. The system is at an advanced stage of prototyping, and the GCT generic trigger processor boards are also being considered as part of an upgrade to the ZEUS Level-1 trigger.
Id: 61
Corresponding Author: Wesley SMITH
Experiment: CMS
Sub-system: Trigger
Topic: Trigger Electronics
CMS REGIONAL CALORIMETER TRIGGER HIGH SPEED ASICs
P. Chumney, S. Dasu, M. Jaworski, J. Lackey, W.H. Smith
University of Wisconsin - Madison
Abstract:
The CMS regional calorimeter trigger system detects signatures of electrons/photons, taus, jets, and missing and total transverse energy in a deadtimeless pipelined architecture. This system contains 19 crates of custom-built electronics. Much of the processing in this system is performed by five types of 160 MHz digital ASICs. These ASICs have been designed in the Vitesse submicron high-integration gallium arsenide gate array technology. The five ASICs perform data synchronization and error checking, implement board level boundary scan, sort ranked trigger objects, identify electron/photon candidates and sum trigger energies. The design and simulation of these ASICs and prototyping results are presented.
Summary:
The CMS Regional Calorimeter Trigger receives compressed data from the calorimeter readout electronics on 1.2 GBbaud copper links, each carrying data for two HCAL or ECAL trigger towers accompanied by error detection codes. 19 total crates (18 for the barrel/endcap and one for both forward calorimeters) each contain seven rear mounted Receiver cards, seven front mounted Electron Isolation cards, and one front mounted Jet Summary card plugged into a custom point-to-point 160 MHz differential ECL backplane. Each crate transmits to the global calorimeter trigger processor its sum Et, missing energy vector, 4 highest-ranked isolated and non-isolated electrons, and 4 highest energy jets and 4 tau-tagged jets along with their locations.
The five digital ASICs developed for the regional calorimeter trigger are the Adder ASIC, Phase ASIC, Boundary Scan ASIC, Sort ASIC and Electron Isolation ASIC. They were produced in the Vitesse FX(TM) and GLX(TM) gate arrays utilizing their submicron high integration gallium arsenide MESFET technology. Except for the 120 MHz TTL input to the Phase ASIC, all ASIC I/O is at 160 MHz ECL.
The Phase ASIC deskews the 120 MHz TTL data from the input 1.2 GBaud copper receiving and deserializing circuitry. It performs error detection and multiplexes the output at 160 MHz ECL. The Phase ASIC also provides test vectors for board and system diagnostics.
The Boundary Scan ASIC implements board-level Boundary Scan and backplane drivers.
The Adder ASIC provides a 4-stage pipeline with eight input operands and 1 output operand. There are three stages of adder tree, with an extra level of storage added to ensure chip processing is isolated from the I/O. The ASIC uses 4-bit adder macro cells to implement twelve bit wide adders.
The Electron Isolation ASIC, processes a total of 36 towers through three separate blocks. The Input Staging block places each reference tower and its neighbors in the same time frame. The Add/Compare block forms four sums between a reference tower and its top, bottom, left and right neighbors. The Find Max block places the single maximum from the original four sums in a register. The HAC Veto, neighbor HAC Veto, and neighbor EM Veto are stored with each of these sums. A final stage of logic sorts through all 16 maxima generated over a bunch crossing time and places that value, along with its Vetos, on the outputs.
The Sort ASIC reads in 4 sets of 4 operands every 25 ns. Each set of 8 operands is divided into two groups of four. The operands are compared in pairs between the two groups, with the larger of the two taking over the position of the left hand member of the pair. This comparison is performed in four stages with a rotation of compared pairs occurring between each stage. By the end of the fourth stage a sufficient number of comparisons have been made to ensure the four largest values of the 16 inputs are in the left-hand group.
Id: 92
Corresponding Author: Orlando VILLALOBOS
BAILLIE
Experiment: ALICE
Sub-system: Trigger
Topic: Trigger Electronics
Updated Design for the ALICE Central Trigger
I.J. Bloodworth [1], G. Di Marzo [2], D. Evans
[1], P. Jovanovic [1],
A. Jusko [3], J.B. Kinson [1], A. Kirk [1],
V. Lenti [4], M. Luptak [3],
L. Sandor [3], P. Vande Vyvre [2] and O. Villalobos
Baillie [1]
for the ALICE collaboration.
1. School of Physics and Astronomy, The University of Birmingham, Edgbaston, Birmingham, UK B15 2TT
2. CERN, European Organization for Nuclear Research, CH-1211 Geneva 23, Switzerland.
3. Dipartimento di Fisica dell' Universita and Sez. INFN, Bari, Italy
4. Institute of Experimental Physics, Slovak Academy of Sciences, Kosice, Slovakia.
Abstract:
The trigger and data acquisition systems in
the ALICE experiment have undergone significant changes in the last year.
This is (i) in response to the incorporation of new detectors, (ii) the
result of the use of front-end buffering schemes in the ALICE sub-detectors,
and (iii) because of new more pessimistic estimates of the data volume
generated by the Time Projection Chamber (TPC). In this report, we review
the specification for the updated ALICE Central Trigger and examine how
it might be implemented using currently available electronics components.
The User Requirement Document and the Technical
Specification for this system are being discussed by the ALICE collaboration.
Summary:
The original trigger concept for the ALICE experiment, as described in the ALICE Technical Proposal, has undergone substantial modifications over the last year as a result of new requirements. These include the addition of new detectors, the decision by the sub-detector groups to use front-end buffering as a means of reducing peak data flow rates to the data-acquisition system, and new, more pessimistic estimates of the data volume from the TPC.
The first step towards a new description of the trigger system came in 1999 with the definition of the signal sequence for communication between the Central Trigger and the sub-detectors. Since then, a much more detailed description of the logical operation of the trigger system has been prepared. Triggers are defined in terms of trigger "classes", the function of which can be explained with a few examples. A trigger class is identified by a given pattern of trigger inputs, and specified that, if it is activated, a trigger should be sent to a specified set of sub-detectors.
The trigger system in ALICE includes a provision
for past-future protection for each sub-detector, to avoid event pile-up.
Each sub-detector has a specific time window inside which past-future protection
should be applied. Past-future protection can be applied uniformly
to a trigger class, since the failure of any detector in a class
invalidates the whole class.
The ALICE trigger is based on three trigger
levels: L0, L1 and L2. The L0 trigger is the earliest, and is issued
so as to arrive at the front-end electronics for each sub-detector at the
latest 1.2 microseconds after the interaction has taken place. The
latency is fixed. It is sent by the quickest possible method, namely a
dedicated coaxial cable. The L1 and L2 decisions are sent using the
RD-12 TTC system; L1 uses channel "A", again with a fixed latency,
and L2 is sent as a broadcast using channel "B". The normal operation
of the TTC allows for the transmission of a trigger number following a
channel "A" trigger pulse. In ALICE, this is set to be the orbit number
and the bunch crossing number, in order to have an event identifier which
is
common for all sub-detectors.
Calibration triggers are also being considered. In most cases, calibrations which cannot be performed outside normal physics runs must nonetheless take place when there can be no collision. The simplest way to ensure this is to schedule them to take place in the large gap in the LHC bunch structure, when no collisions take place. Calibration requests can be made, which define a special trigger class, typically consisting of just one detector, and the triggers can be flagged so as to allow the front-end electronics to perform special tasks, e.g. to suspend zero suppression. The method for communicating a calibration request to the Central Trigger is under discussion.
Id: 100
Corresponding Author: Jacques LECOQ
Experiment: ALICE
Sub-system: Trigger
Topic: Trigger Electronics
A front end ASIC for the Dimuon arm trigger of the ALICE experiment
Laurent Royer, Gerard Bohner, Jacques
Lecoq
For the ALICE collaboration
LPC Clermont-Ferrand
A first prototype of the front-end ASIC dedicated to the trigger detector of the dimuon arm of ALICE has been designed and tested in the Laboratoire de Physique Corpusculaire of Clermont-Ferrand.
This setup is based on the Resistive Plate Chamber (RPC), a gaseous detector which can be operated either in streamer or avalanche mode. The streamer mode has the advantage of providing large signals that can be discriminated without amplification whereas the avalanche mode presents a better rate capability and time resolution with conventional discrimination techniques.
Since we proposed to operate the RPCs in streamer mode in ALICE, we have studied a new discrimination technique in order to obtain a time resolution better than 2ns in this mode. The method used in this dedicated circuit is described, performances and tests results are given, as well as the evaluation done in the test beam of summer 2000.
Summary:
The trigger system of the dimuon arm of the ALICE/LHC detector has to select events containing two muons from the decay of heavy resonances like J/Y or ¡, amongst all background sources. The setup is composed of 72 Resistive Plate Chambers (RPC), a gaseous detector where the electrical charge produced by the crossing of a charged particle is collected on 1-4 cm wide, 35-70 cm long, strip lines. Almost 21 000 readout channels are necessary to cover the whole detector area.
RPCs are operated in streamer mode in ALICE and no amplification of the analog signal is needed. The analog signal picked up on the strips has to be discriminated and then shaped with a width of about 20 ns. The output signals of all readout channels are sent in parallel through 20 m long cables to the trigger electronics. A sampling at the LHC clock frequency (40 MHz) is performed at this level before the dimuon trigger decision is issued.
Using conventional discrimination techniques, the time resolution is better when using RPC in avalanche mode (commonly 1ns), unless the RPC is operated in streamer mode at quite high running voltages that is not suitable. In order to improve the time resolution in streamer mode, a new discrimination technique called "ADULT" has been studied.
The observation of RPC pulse shapes in streamer mode shows that the streamer signal itself is preceded by a smaller signal, called "avalanche precursor". The streamer signal exhibits important time fluctuations while the avalanche precursor is almost stable.
The ADULT technique exploit this good timing property of the avalanche precursor with the validation by the large streamer signal which is well above any source of noise. The technique makes use of two discriminators, with a low threshold (typically 10 mV/50 ohms) at the level of the avalanche precursor and a high threshold (typically 80 mV/50 ohms) at the level of the streamer. It is followed by a coincidence of the two outcoming signals with the time reference given by the low threshold one.
This dedicated discrimination technique has been implemented in a front end chip developed in the "Laboratoire de Physique Corpusculaire" of Clermont-Ferrand. The chosen technology is AMS BiCMOS 0.8mm.
The chip prototype is composed of one
channel including the "ADULT" discrimination technique and additional functions
:
-an "one-shot" system which prevents
the chip from re-triggering during 100ns,
-a remote delay with a range of 50ns,
-a shaper to obtain a 20 ns logical
output signal,
-an ECL buffer to drive a 20 m twisted
pair cable.
Five packaged chips were delivered
in middle of May 2000. The tests in laboratory have shown that each stage
of the chip works perfectly. The power consumption is still a little bit
high (140mW per channel) but will be decreased by replacing the ECL driver
by a LVDS one.
The low threshold discriminator gives
the time reference until the delay between the avalanche precursor and
the streamer signals reaches 11 ns, which is enough regarding the actual
detector pulses.
The 20 ns ECL output signal can be
delayed in a range of about 60 ns and the one-shot protection is a little
bit longer (138 ns ) than the designed value.
A RPC equipped with 8 of these chips has been tested at the CERN/PS beam area at the beginning of July 2000. First results are presented in this paper, as well as possible improvements and foreseen developments of the chip.
Id: 104
Corresponding Author: Riccardo VARI
Experiment: ATLAS
Sub-system: Muon
Topic: Radiation and magnetic field tolerant
electronics systems
RADIATION TOLERANCE EVALUATION OF THE ATLAS RPC COINCIDENCE MATRIX SUBMICRON TECHNOLOGY
E.Gennari, E.Petrolo, A.Salamon, R.Vari,
S.Veneziano
INFN - Sezione di Roma
P.le Aldo Moro 2 - Rome - Italy
ABSTRACT:
The Coincidence Matrix ASIC is the
central part of the ATLAS Level-1 Muon Trigger in the barrel region; it
performs the trigger algorithm and data read-out. The ASIC will be mounted
on dedicated boards on the Resistive Plate Chamber detectors. The chosen
technology has to guarantee complete functionality in the ATLAS RPC radiation
environment. Radiation tests have to satisfy the radiation tolerance criteria
proposed by the ATLAS Policy on Radiation Tolerant Electronics. The ATLAS
standard test methods has to be followed in order to guarantee both total
dose and single event effects tolerance.
A frequency multiplier ASIC was used
for technology evaluation and radiation tests. The chip is a low jitter
programmable clock multiplier, realised in 0.25 micron CMOS technology.
This frequency multiplier is intended to be used in the Coincidence Matrix
ASIC as a macro, to perform the internal clock frequency multiplication.
Radiation test results will be presented.
SUMMARY:
The ATLAS level-1 muon trigger in the
barrel region makes use of the Resistive Plate Chamber dedicated detector
(RPC). The triggering procedure is accomplished through a Low Pt and a
High Pt trigger. The Low Pt trigger uses the information generated in the
two Barrel Middle RPC stations, while the High Pt trigger uses the result
of the Low Pt trigger and the information of the RPC Barrel Outer station.
RPC data readout and level-1 triggering are performed by a dedicated chip,
the Coincidence Matrix ASIC (CMA). About 4000 CMA chips will be installed
on dedicated boards, that will be mounted on the RPC detectors. This chip
performs almost all the most relevant functions needed for the barrel trigger
algorithm and for the readout of the RPC strips. It makes the right timing
settings of the signals, the coincidence and majority operations, the Pt
cut on three different thresholds and it acts as level-1 latency memory
and derandomizing buffer.
Electronics complete functionality
has to be guaranteed in the ATLAS RPC radiation environment. The ATLAS
Policy on Radiation Tolerant Electronics defines the minimum dose and fluences
which must be tolerated by the electronics, and the maximum rate of soft,
hard or destructive Single Event Effects acceptable for the electronics.
This level of reliability must be maintained during 10 years of LHC operation.
ATLAS standard radiation test methods have to be followed in order to compare
test results with the calculated Radiation Tolerance Criteria defined in
the ATLAS Policy, so as to qualify the ASIC technology, architecture and
design.
A frequency multiplier ASIC was used
for CMA technology evaluation and radiation tests. A chip containing the
frequency multiplier was released by Fujitsu for test use. The CMA chip
will make use of this frequency multiplier as a macro, for generating an
internal 320 MHz clock from the external 40 MHz ATLAS clock. The frequency
multiplier uses a low jitter Delay Locked Loop (DLL) to provide the output
clock, which range is 40-400 MHz (a multiplying factor between 2 and 32
can be programmed). The chip is realised in 0.25 micron CMOS technology,
and has a 2.5 V power supply.
Cobalt 60 gamma source and proton
source were used for radiation tests. The chip showed a correct functionality
during gamma irradiation up to a total dose of 300 kRad (lower then calculated
RTC value). No hard or destructive errors were detected during proton irradiation.
Only soft Single Event Upset errors were detected. The extrapolated foreseen
rate of soft SEU in the RPC detectors is lower then the calculated RTC.
Test results will be presented, as
well as radiation test strategies and comparison between different radiation
facilities.