Id: 25
Corresponding Author: Giovanni MAZZA
Experiment: ALICE
Sub-system: Tracker
Topic: Electronics for Trackers

Test results of the ALICE SDD electronic readout prototypes

G. Mazza[INFNTo], G. Alberici[INFNTo], G. Anelli[CERN], G.C Bonazzola[UniTo],
D. Cavagnino[UniTo], P.G. Cerello[INFNTo], P. De Remigis[INFNTo],
D. Falchieri[INFNBo], A. Gabrielli[INFNBo], E. Gandolfi[INFNBo],
P. Giubellino[INFNTo], M. Masetti[INFNBo], L.M. Montano[INFNTo],
D. Nouais[INFNTo], A. Rivetti[CERN][UniTo], F. Tosello[INFNTo],
A. Werbrouck[UniTo], R. Wheadon[INFNTo]
for the ALICE collaboration

Institutes :
[INFNTo]        INFN sezione di Torino, Italy
[INFNBo]        INFN sezione di Bologna, Italy
[UniTo]         Universita` di Torino, Italy
[CERN]          CERN, Geneve, Switzerland

Abstract:

The first prototypes of the front-end electronic of the ALICE silicon drift detectors has been designed and tested. The integrated circuits have been designed using state-of-the-art technolgies and, for the analog parts, with radiation-tolerant design techiniques. In this paper the test results of the building blocks of the PASCAL chip and the first prototype of the AMBRA chip are presented. The prototypes fully respect the ALICE requirements; owing to the use of deep-submicron technologies togheter with radiation-tolerant layout techniques, the prototypes have shown a tolerance to a radiation dose much higher than the one foreseen for the ALICE environment.

Summary:

The design of the readout electronic for the ALICE silicon drift detector is a very challenging task, due on one side to the huge amount of data produced by those detectors ( 256 10-bit words for each detector anode, in the case of the ALICE SDDs ) and on the other hand to the stringent constraints in term of space, power consumption and radiation hardeness. The chosen architecture is based on 2 integrated circuit, PASCAL and AMBRA. It works in two different phases : during the acquisition phase the detector signal is amplified and stored into a fast analogue memory; when the trigger signal validates the data, the readout phase starts and the analogue informations in the memory are converted by an A/D converter and transferred into a digital multi-event buffer. All the analogue functions ( amplification, storage and conversion ) are embedded in a single chip ( PASCAL ) while the digital event buffer plus most of the control logic are on a separate chip ( AMBRA ). The analogue memory is of the write-voltage read-voltage type; it uses MOS capacitors as storage elements in order to save space. The intrinsec MOS capacitor non-linearity limits the dynamic range to about 1.5 volts over a 2.5 power supply. The A/D converter is of the switched-capacitor, successive approximation type; the 10 bit resolution is obtained by an 8 bit main DAC followed by a 2 bit secondary DAC with direct coupling. Prototypes of the analogue memory and the A/D converter in a commercial 0.25 um technology with radiation tolerant design techniques have been designed and tested. The results show that both prototypes fully satisfy the ALICE requirements in terms of performances and power consumption. Owing to the adopted radiation tolerant technique, the prototypes does not show any significant degradation after a total dose up to 10 Mrads. The first prototype of the PASCAL chip is currently under production. The first prototype of the AMBRA chip has been designed and tested in a 0.35 um technology. The chip fully satisfy the ALICE requirements; radiation test are ongoing in order to check the radiation tolerance of a fully digital deep submicron technology without radiation tolerant layout techniques.
 

Id: 26
Corresponding Author: Jan David SCHIPPER
Experiment: LHCB
Sub-system: General Interest
Topic: Electronics For Trackers

Low Noise Amplifier

J.D. Schipper, NIKHEF R. Kluit,NIKHEF

Abstract:

As a design study for the LHC experiments a 'Low Noise Amplifier Shaper' for capacitive detectors is developed. This amplifier is designed in 0.6 um technology from AMS. The goal was to design an amplifier with a noise contribution of 250 electrons, a 12 electrons per pF contribution from the input capacitor and a relative high gain. A test chip with two versions of the amplifier, a 'radiation tolerant' (gate-around FET's) and a 'normal' version has been fabricated and is now under test. These designs and there characteristics, simulated and measured, will be compared and discussed.

Summary:

For the LHC experiments at CERN a 'Low Noise Amplifier Shaper' for the readout of Silicon Micro Strip detectors is developed. The goal for this 'Low Noise Amplifier Shaper' is to study an amplifier design with a relative high gain and an equivalent noise charge of 250 electrons, plus 12 electrons / pF detector capacity at the input. These noise requirements are based on a 150 u Silicon strip detector (12000/MIP). The design of the amplifier is based on the amplifier in the HELIX-128 chip developed for HERA-B. The principle of the circuit is a folded cascode. This scheme is used for two reasons: Speed and power supply (dynamic range). A test chip with two versions of the amplifier, a 'radiation tolerant' (gate-around FET's) and a 'normal' version has been fabricated and is now under test. The both versions are a not equal, caused by the size limitations of the 'gate around' N-FET's. In the 'normal' version of the circuit the input P-FET is connected with the source to ground. In the 'gate around' version the feedback FET must be a P-type FET. The fact that the gate for an N-FET must be a closed figure makes it impossible to realise a W/L ratio smaller then about 4. This has been implemented by redefining the DC levels of the amplifier. During the design phase the design has been simulated intensively to verify the functionality and the predicted noise figure.

Version            Simulated         Measured                  Tpeak                                  Gain Noise     Gain   Noise
Gate around     57 mV        1741 el.                         56 mV                                                    3235el.                22 nsec
Normal            29 mV        1956 el.                         38 mV                                                        2305el.                25 nsec

In the table above some preliminary results are given. The Gain and bandwidth are as expected, but the noise is higher as expected.

Id: 34
Corresponding Author: Daniel BAUMEISTER
Experiment: LHCB
Sub-system: Tracker
Topic: Electronics For Trackers

Design and test of a readout chip for LHCb

Niels van Bakel, Jo van den Brand, Hans Verkooijen (Free University of Amsterdam / NIKHEF Amsterdam)

Daniel Baumeister, Werner Hofmann, Karl-Tasso Knoepfle, Sven Loechner, Michael Schmelling, Edgar Sexauer (Max-Planck-Institute for Nuclear Physics, Heidelberg)

Martin Feuerstack-Raible (University of Heidelberg)

Neville Harnew, Nigel Smale (University of Oxford)

Abstract:

For the LHCb experiment a first prototype of a 128 channel analogue pipeline chip, named Beetle, has been developed and submitted in a standard 0.25 um CMOS process.

It integrates 128 channels with charge sensitive preamplifiers and shapers, whose outputs are sampled with 40 MHz into an analogue pipeline with a maximum latency of 160 sampling intervalls. A comparator behind the shaper provides a binary signal. The 128 channels can be multiplexed on either 4, 2 or 1 outputs. The bias settings are programmable and monitorable via a standard I2C-interface. The architecture of the chip is described as well as simulation and test results are presented.

Summary:

For the LHCb experiment a first prototype of a 128 channel analogue pipeline chip, named Beetle, has been developed and submitted. This readout chip will be made in a standard 0.25 um CMOS process.

It integrates 128 channels with low-noise charge-sensitive preamplifiers and shapers. The risetime of the shaped pulse is 25 ns wih a 25% remainder of the peak voltage after 25 ns. A comparator with configurable polarity and threshold level behind the shaper provides a binary signal. Four neighbouring comparator channels are being ORed and brought off chip via LVDS ports. Either the shaper or comparator output is sampled with the LHC-bunch-crossing frequency of 40 MHz into an analogue pipeline with a programmable maximum latency of 160 sampling intervalls and an integrated derandomizing buffer of 16 stages. The pipeline cells are realized as nmos gate-capacitances. The stored charge is read out via a charge-sensitive amplifier and multiplexed with 40 MHz onto 4 or 1 ports. In binary readout multiplexing runs at 80 MHz on two ports. Current drivers bring the serialized data off chip.

The chip works with a trigger rate of 1 MHz and performs readout deadtimeless in 900 ns. For testability and calibration purposes a charge injector with adjustable pulse height has been implemented. The bias settings and various other parameters are programmable and monitorable via a standard I2C-interface. The chip contains only synthesized logic which has been placed and routed automatically. The architecture of the chip is described in detail as well as simulation and test results are presented.

Id: 36
Corresponding Author: Angelo RIVETTI
Experiment: ALICE
Sub-system: Tracker
Topic: Electronics For Trackers

A MIXED SIGNAL ASIC FOR THE SILICON DRIFT DETECTORS OF THE ALICE EXPERIMENT IN A 0.25 UM CMOS

A. Rivetti (1,2), G. Anelli(1), F. Anghinolfi(1), G. Mazza,(2) P. Jarron(1)
(1)CERN, CH-1211 Geneva 23, Switzerland
(2)INFN, Sezione di Torino, Via Pietro Giuria 1, 10125, Torino, Italy

Abstract:

A mixed signal integrated circuit developed for the read-out of Silicon Drift Detectors (SDDs)is presented.

The chip contains 32 channels and 16 ADCs. Each channel is made of an amplifier and an analog pipeline with 256 cells. One ADC is shared by two adjacent channels. The circuit is optimized to match the specifications of the SDDs of the ALICE experiment, where large dynamic range and low power consumption are key issues. The input noise is calculated to be 200 e- rms for an input capacitance of 3pF and a detector dark current of 10nA. The power consumption is 5mW/channel.

Summary:

Silicon Drift Detectors offer the advantage of a two-dimensional position measurement while requiring a very low amount of processing electronics. These detectors are well suited for experiments in which a very high particle density is coupled with a relatively low event rate, as is the case of heavy-ion experiments. For example, SDDs are used in the two intermediate layers of the Internal Tracking System (ITS) of the ALICE experiment. The constraints on material budget, power consumption and noise make the design of the front-end electronics for the SDDs in ALICE particularly challenging. In fact, in order to reach the required resolution (30 um in both coordinates) the noise should be limited below 250 e- rms. The maximum power consumption (including also the digitization of the data) must be kept below 5mW/channel. The electronics is DC coupled to the sensor and the baseline has to be stabilized against variations of the detector leakage current. Input signals up to 8 mips have to be correctly processed by the front-end.

We have developed an ASIC which is able to meet all of the previous requirements. The chip provides amplification of the input signal, temporary storage of the analog data in a 256 cells pipeline and a 10 bit analog-to-digital conversion.

All the operations are controlled by a digital unit implemented on chip. The chip has been implemented in a commercial 0.25 um CMOS technology, using radiation tolerant layout approach. This should guarantee immunity to radiation damage at least up to a total dose of 10 Mrad (SiO2).

The amplifier uses a charge integrating scheme, with pole-zero cancellation and CR-RC^2 shaping. The coupling between the preamplifier and the shaper is made with the help of an error amplifier. In this way, the value of the baseline can be regulated via an external voltage and is completely insensitive to the variations of the detector leakage current. The power consumption of the amplifier (including the output buffer) is 1.7mW/channel and the maximum signal swing is 1.4 Volt. The gain of the amplifier for a delta input signal is 170mV/mip.

In the analog memory gate capacitors are used in order to reach a satisfactory circuit density. A voltage-write voltage-read scheme has been selected to minimize the effect of the voltage dependence of these capacitors.

The 10 bits analog-to-digital converters is implemented using a switched capacitor charge redistribution scheme. Since in this circuit the capacitor linearity is crucial metal to metal capacitor are used. The ADC is able to perform a full conversion cycle (sampling +digitization) in 500 ns. Due to layout constraints one ADC is used to convert the data of two adjacent channels.

For the analog memory and the ADC we used preliminary circuits developed as analogue demonstrators in the framework of the CERN RD49 program. The tests performed on these building blocks have shown very satisfactory results; on both parts a resolution of 10 bits with very low power consumption (3.5mW/channel for the memory and 1mW/channelfor the ADC) has been measured.

Id: 56
Corresponding Author: Piotr MALECKI
Experiment: ATLAS
Sub-system: Tracker
Topic: Electronics For Trackers

Multichannel system of fully isolated HV power supplies for silicon strip detectors

Edward Gornicki (Institute of Nuclear Physics, Cracow, Poland) Stefan Koperny (Faculty of Physics and Nuclear Techniques of UMM, Cracow} Piotr Malecki (Institute of Nuclear Physics, Cracow)

Abstract:

A multichannel system of power supplies providing a bias voltage in the range of 0 - 410 V for silicon micro-strip detectors is presented. All channels are fully isolated allowing for flexible detector segmentation. A wide range of functions including e.g. a programmable current trip limit as well as a ramp-up and rump-down control independent for each channel are also described.

Summary:

The system consists of cards each of which contains several single isolated channels.The system is build in two similar versions. The full VME version for laboratory applications in small centers testing modules of silicon strip detectors. In this version a standard 6U card consists of four independent power supplies. The version for the final detector system of the ATLAS experiment uses standards of VME mechanics but a custom backup plane and crate control. In this version 8 channels are packed on each card.

The system provides digitally controlled stable bias voltage in 0 - 410 V range and a precise measurement of the output current. A maximum load of each channel is 5 mA. A current trip limit can be set independently for every channel in the range from hundreds of nA to the maximum of 5 mA. Another parameter which can be selected individually for each channel is the ramping speed with which the nominal voltage change is to be executed. Ramping speeds can be selected from the range of 10 - 100 V/s.

Single channel functions are controlled by programmable microprocessor which communicates with a programmable card controller via fast serial link. Communication with the crate controller for the VME version uses standard addressing mode. In the final production version this communication is realized with a fast custom parallel link. Mutual reaction times of processors to various conditions like requirement of a new setting, over-current and over-voltage trips etc are well below 1 ms.

Id: 58
Corresponding Author: Horst FISCHER
Experiment: General Interest
Sub-system: Tracker
Topic: Electronics For Trackers

TDC based Readout for High-Rate Drift Tubes and Wire Chambers

H. Fischer*, J. Franz, A. Grunemaier, F.H. Heinsius, L. Hennig, K. Konigsmann, M. Niebuhr, T. Schmidt, H. Schmitt, H.J. Urban Fakultat fur Physik, Universitat Freiburg, 79104 Freiburg, Germany

Abstract:

The tracking system for the COMPASS experiment at CERN will consist of about 40000 drift tubes. In our report we discuss the design of and the practical experience with the drift-tube readout system which we set up during the year 2000 detector commissioning run.

The front-end board for the electronic processing of the signals produced by the drift tubes contains 64 preamplifiers, shapers, discriminators and time-to-digital converters. For the analog processing of the signals the ASD8b chip has been selected. For the COMPASS experiment we have developed a new TDC (F1) which comprises an asymmetric ring oscillator controlled by a phase locked loop. The digitised signals are transmitted via serial links to readout-driver modules. This 9U VME unit interfaces up to 16 front-end data-links to one optical S-LINK. Besides local event building the FPGA-based module covers front-end board initialisation, trigger distribution and data flow surveillance

Summary:

The tracking system for the COMPASS experiment at CERN will consist of about 40000 drift tubes. In our report we will discuss the design of and the practical experience with the digital readout system which we begin to set up during the year 2000 detector commissioning run.

The overall size of the experiment (6x4x40m^3), the expandability and the upgradability requirements of the experiment prerequisites a scalable and distributed readout system. The paradigm of the COMPASS readout foresees digitisation immediately at the detector. Data are stored on the front-end boards in random access memory or pipelines until trigger decisions have been taken. On-chip zero suppression, sparsification and signal over background extraction is accomplished by time correlation of hits with the trigger time.

The front-end board for the electronic processing of the signals produced by the drift tubes contains 64 preamplifiers, shapers, discriminators and time-to-digital converters. For the analog processing of the signals the ASD8b chip has been selected. The ASD8b has been originally designed for the drift tube readout of the SDC detector. Attractive attributes like short measurement time, good double pulse resolution and low operational threshold makes it the first choice for our application.

To ensure that the position resolution of the drift tubes is not spoiled by the electronics, the digitisation chain is required to have sub-nanosecond timing accuracy. In particular possible interference between the highly sensitive analog input and the high speed digital readout requires careful design and layout of the front-end board.

For the COMPASS experiment we have developed a new TDC chip (F1) which comprises an asymmetric ring oscillator controlled by a phase locked loop. A chain of 19 delay elements is used to tap time digitisation in steps of 120ps to 150ps (programmable). In a different mode, provided for multi-wire proportional chamber readout, 32 input lines are latched in groups of four to the eight TDC channels. In this case the resolution is 5~ns, and the last four bits of the time stamps are used to flag hits on the four connected lines. The F1 is based on a 0.6 micron sea-of-gates CMOS process. Excellent time resolution, high rate capability, low power consumption and wide flexibility due to in-system programmable setup registers let the chip appear as an ideal candidate for many applications not only in drift tube readout.

Further a common readout-driver module for all different detector front-ends has been developed. This 9U VME unit interfaces up to 16 front-end data-links to one optical S-LINK. Besides local event building the FPGA-based module covers front-end board initialisation, trigger distribution and data flow surveillance.

Id: 62
Corresponding Author: Hans VERKOOIEN
Experiment: LHCB
Sub-system: Tracker
Topic: Electronics For Trackers

Design of a comparator in a 0.25µm CMOS technology

Niels van Bakel, Jo van den Brand (Free University of Amsterdam / NIKHEF Amsterdam), Hans Verkooijen (NIKHEF Amsterdam), Daniel Baumeister, Werner Hofmann, Karl-Tasso Knoepfle, Sven Loechner, Michael Schmelling, Edgar Sexauer (Max-Planck-Institute for Nuclear Physics, Heidelberg) Martin Feuerstack-Raible (University of Heidelberg), Neville Harnew, Nigel Smale (University of Oxford)

Abstract:

A comparator for the LHC-B vertex detector front-end chip, the Beetle, has been designed in a 0.25µm CMOS technology and is sent for fabrication. To improve threshold uniformity, each comparator has a 3 bits DAC. The comparator can handle positive and negative inputsignals. A polarity signal changes the polarity of the threshold voltage and makes the outputsignal always positive when active. The outputsignal is latched by a 40MHz clock and is selectable between time-over-threshold (in 25ns bins) or active for one clockcycle. Simulation- and measurement results will be discussed.

Summary:

For fast primary vertex reconstruction and pile-up rejection binary hit information is needed from the LHC-B vertex detector front-end electronics. Therefore a comparator for the Beetle chip has been designed. The Beetle is a 128 channel analog pipeline chip for the LHC-B experiment and, like the comparator, implemented in a 0.25µm CMOS technology, using rad-tolerant layout rules. To make the comparator insensitive for low frequency inputsignals, e.g. temperature drift and different offsets, one of the inputs of the comparator has a low-pass filter to obtain the DC-voltage of the incoming signal. This voltage is summed to the threshold voltage. The threshold voltage is the combination of a controllable voltage used for all comparators and a individual voltage for each comparator controlled by a 3 bits DAC. The comparator operates in a 40MHz system. The outputsignal of the compared time-over-threshold voltage is latched at a well defined time by a 40MHz clock, which is related to the beam timing. The width of the analog inputsignals is roughly 25ns and therefore the time-over-threshold can be longer than one period. By means of a "output mode selection" the outputsignal can be time-over-threshold (in 25ns bins) or one pulse of 25ns once the inputsignal went over threshold. The comparator can deal with positive and negative inputsignals. A polarity signal switches the polarity of the threshold voltage and controlles the output stage so that the outputsignal is always a positive pulse. In addition a multiplexer to store hits as binary information has been designed. This multiplexer selects the signal to the analog pipeline between the shaper output or the comparator output and converts the digital signal from the comparator in 0 or 10 MIP signal. Specifications -The timewalk of the outputsignal is 10ns for signals between 5mV to 100mV above threshold. -The inputsignal should be between GND + 0.8V and VDD - 0.8V. -The powerconsumption is expected to be 350µW.

Id: 63
Corresponding Author: Jean-Robert LUTZ
Experiment: ALICE
Sub-system: Tracker
Topic: Electronics For Trackers

FEE tracker module developments for ALICE and STAR

Abstract:

Assessments of the front-end module developments in the frame of ALICE and STAR trackers in relation with the radiation effects on detectors and chips. Production of similar modules for the STAR SVT.

Id: 64
Corresponding Author: Florent VAUTRIN
Experiment: LHCB
Sub-system: Tracker
Topic: Electronics For Trackers

Comparative study of current-mode versus voltage-mode analog memory in a 0.25um CMOS technology

F.VAUTRIN, J.MICHEL, F.BRAUN

Abstract:

The aim of this work is the study of switched-current and voltage-mode memory cells in order to develop a model including non-ideal effects such as charge injections,non-linear capacitance and readout system influence. These models will allow non-linearity control regard to surface, speed and power criteria in digital dedicated submicronic technology. Such models lead to a memory cell optimization in order to include it in an analog memory for LHC experiments.

Summary:

By definition, an analog memory consists of several thousands of channels of several hundreds of depth cells. The study of these memories goes through memory cells performances identification The cells have to be faithfully reproducible, low noise, of minimum area and power. Power per cell and area per cell are critical points. A state of the art on analog memories works show that the balance between power and area can be achieved by using submicronic technologies. Moreover, such technologies can be used in radiative environment. It is important to study second generation switched-current structures as an alternative to voltage mode structures. These structures are fully compatibles with the new CMOS submicronic technologies dedicated to digital circuits. Indeed, there are not limited (first approximation) by linearity and hysteresis of storage capacitors, like in voltage-mode. The goal of this study is to identify accuracy limits that can be reached with minimum size architectures in a deep submicronic technology (0.25 um) for both types of cells: voltage mode and current mode. By comparison to a typical N bits acquisition system, accuracy error should be less than half a quantum. By studying operating phases of each cell, we have developed theoretical models that include non-linear effects such as charge injections, readout system influence for both types of cells, finite output conductance for current-mode cell, and non-linear capacitance for voltage mode cell. These models are polynomials of output signal as a function of input signal. Accuracy is divided in two parts: static and a dynamic accuracy. In fact, dynamic error is over-evaluated and final precision is only conditioned by static precision that is to say non-linearity error. In such a cell with a 40 MHz acquisition frequency, dynamic error is limited to a half quantum of 9 bits for an 8 bits final precision. This analysis highlights predominant factors that influence non-linearity error: memory capacitance value, output impedance, memory transistor size (switched-current). For both cell types, final accuracy, acquisition frequency and power dissipation are fixed constraints. Freedom degrees are full-scale, area and errors repartition. For voltage-mode cell, the full-scale is fixed by technology constraints. The model predicts an 8 bits non-linearity error for a 300fF capacitance value and a 60 um2 area. A comparison with current-mode cell shows an 8 bits non-linearity error for an 800 fF capacitance value and a 140 um2 area. The paper is focused on polynomials development and exploitation. Such models allow the optimization of a memory cell for LHC experiments. In current-mode cells, full-scale and bias current are variables. By exploiting these models, the designer is able to do compromises between accuracy, power dissipation and area in order to obtain the same accuracy than a voltage mode cell. Finally, two optimal cells are presented.

Id: 67
Corresponding Author: Mitch NEWCOMER
Experiment: ATLAS
Sub-system: Tracker
Topic: Electronics For Trackers

Experience with DMILL technology in the Development of the ASDBLR ASIC

N. Dressnandt, N. Lam, F.M. Newcomer*, R.P. VanBerg, H.H. Williams
University of Pennsylvania, Philadelphia Pa.

Abstract:

An engineering prototype of the ASDBLR ASIC has been fabricated in the rad hard, BICMOS, DMILL process offered by Temic. This ASIC integrates eight channels of high speed low power and low noise straw tube readout on a single substrate. Bi-level signal detection for ionizing tracks and TR photons at rates as high as 20MHz is accomplished utilizing six hundred custom sized components per channel. A previous DMILL prototype showed strong sensitivity to hookup conditions manifested as unexpected harmonics. Steps taken to eliminate these harmonics, including improvement of the device models appear to have been successful. Measured performance of the recent prototype nearly exactly matches SPICE calculations. Results from neutron and proton exposures, beam tests with the companion DTMROC readout chip and plans to include custom devices that have been fabbed for us by TEMIC will be discussed.

Summary:

The ASDBLR ASIC is intended to provide the full signal processing chain, input to tri-level discriminator output for the 430,000 straw ATLAS TRT detector. Measurements of a first version of this ASIC fabricated in a bulk analog bipolar process served to qualify the circuit technique for use in the ATLAS TRT. We have since decided to develop a version in DMILL, a rad hard SOI, BICMOS process recently commercialized by Temic. A six channel ASIC was designed in DMILL and submitted for fabrication in the summer of 1997. Our first tests with packaged chips indicated a sensitivity to hookup which was ultimately traced to on chip crosstalk through the SOI substrate. A more complete discussion can be found in the LEB99 proceedings.

In August 1999 we submitted a revised version of the ASDBLR and it's companion timing and readout ASIC, the DTMROC, for an engineering run. Both chips are fully functional and match well with pre submission simulations. Harmonic oscillation in the ASDBLR specific to the DMILL design was addressed with the following modifications that appear to have successfully resolved the problem: 1) Use of CEA developed shielded input pads. 2) Addition of a differential stage prior to tail cancellation to reduce single ended capacitor driven cross talk to the back substrate. 3) Addition of global substrate grounding rings around all sensitive devices to fix the potential of unused areas of silicon above the SOI substrate. 4) Addition of a small preamp supply R-C filter network on each channel.

The following circuit embellishments were added to improve the general performance: 1) Addition of dynamic current sources on the buffer transistors that drive the baseline restorer to reduce quiescent current. 2) Addition of a fixed 4ns delay in the output of the low level discriminator to align the output of low and high outputs for a clean ternary sum. 3) Programmable tuning of the ion tail cancellation.

Test Devices -

Significant stray, to the substrate underlying the insulator in DMILL devices combined with the relatively high gain and bandwidth required for the ASDBLR amplifier and shaper circuit make it desirable to minimize stray capacitance of on chip devices at the input. Large area devices at the input include, input pads, input protection, and transistors. A shielded input pad designed by a CEA group has been approved for use by TEMIC and was incorporated successfully in the ASDBLR. In December 1998 TEMIC fabbed several custom test structures for us including two types of multi-striped NPN transistors for use as input transistors and an input protection structure consisting of a large number of parallel connected NPN transistors. Multi-striped NPN transistors offer the advantage of lower base resistance and lower stray capacitance for the same collector current density compared to single emitter stripe devices. Expanded geometry single stripe NPNs with collector and base shorted to a supply were used for input protection. In this configuration the collector acts as a shield to the back substrate and is shorted to the base which becomes the anode of the input protection structure. The emitter acts as the cathode and has the desirable benefit of a comparatively low stray capacitance. The reverse bias of this base emitter junction is well controlled under ordinary conditions by the single Vibe drop of the ASDBLR common emitter input configuration.

Test Structure Measurements - Two transistors on the input protection test structure were wired in common emitter configuration to mimic the ASDBLR input and a repetitive pulse was amplified and observed while the input protection was tested by discharging repeatedly a capacitor charged by a variable voltage through 24 ohms at the input. Reliable protection to 1500uJ was provided by this structure.

ASDBLR Measurements - The peaking time appears to be about 15% faster than the desired 7.5ns value while the absolute threshold is within 5% of the SPICE calculated value for both high (TR photon sensitive) and low (tracking) discriminators. The functional yield is ~75% but after applying channel to channel threshold matching requirements the yield is only 35%, about half of that of a design of similar complexity fabbed by us in a bulk process. Resistor matching results reported by the foundry indicate a larger than expected variation which can be responsible for the lower yield. We have carefully examined the circuit and find no other plausible explanation at this time.

Radiation tests - Unbiased ASDBLR's from this run were exposed to 10^14 neutrons/cm^2 at Prospero and no change in performance is observed. On chip resistors were tested and changes were less than 1%. Both multi-stripe and single stripe NPN devices from the test structures were also exposed and found to have a beta of ~60 at a current density of 3.3uA/um of emitter. Pre-rad beta was ~280.

Future Measurements ASDBLR's and their companion chips (DTMROC's) have been exposed under power to 10^14protons/cm^2 at CERN and are awaiting the return of these devices for post rad characterization. Beam tests using prototype modules and a high density readout with ASDBLR and DTMROC ASICS are planned to take place at the H8 beam line at CERN over the summer. Results of these tests should be available for the September LEB meeting.

Id: 70
Corresponding Author: Ulrich GOERLACH
Experiment: CMS
Sub-system: Tracker
Topic: Electronics for Tracker

CHARACTERISATION OF THE APVD READ-OUT CIRCUIT FOR DC-COUPLED SILICON DETECTORS (Final report)

J.D. Berst, C.Colledani, Y.Hu, R.Turchetta, LEPSI, IN2P3/ULP,
23 rue du Loess, BP20, F-67037 Strasbourg, France

G.Deptuch, U.Goerlach, C. Hu-Guo, P.Schmitt, IReS, IN2P3/ULP,
23 rue du Loess, BP20, F-67037 Strasbourg, France

M.Dupanloup, S.Gardien, IPNL IN2P3/CNRS, F-69622 Villeurbanne, France

Abstract:

The APVD integrated circuit for the front-end electronics of DC-coupled silicon detectors for CMS has been developed and produced in the radiation-hard process DMILL.The APVD_DC contains, like other members of the APV family 128 identical analog channels, each composed of a low noise preamplifier, a CR-RC shaper, an analog pipeline of 160 cells and a signal processing stage. A current compensation circuit is added in every preamplifier to sink the leakage current coming from the detector.

We report on the final test results: the complete circuit has been tested and measured also in the presence of significant leakage currents up to 11 microampere which do not deteriorate the analog performance of the circuit like pulse shape dynamic range and adding about 300 ENC to the noise.

Previous APVD circuits suffered from an instability problem in the analog stage of the circuit occurring at nominal bias values. The analog baseline of the new modified circuit is absolutely stable also under extreme operation conditions, like high bias currents demonstrating that the implemented solution stops indeed the oscillation of the circuit as we previously claimed based on extensive simulations of the circuit.

Id: 71
Corresponding Author: Ulrich GOERLACH
Experiment: General Interest
Sub-system: Tracker
Topic: Electronics for Tracker

A Novel Monolithic Active Pixel Sensor for Charged Particle Tracking and Imaging using Standard VLSI CMOS Technology

J.D. Berst, B.Casadei, G.Claus, C.Colledani, W.Dulinski, Y.Hu, D.Husson,
J.P.Le Normand, R.Turchetta, J.L.Riester LEPSI, IN2P3/ULP,
23 rue du Loess, BP20, F-67037 Strasbourg, France

G.Deptuch, U.Goerlach, S.Higueret, G.Orazi, M.Winter IReS, IN2P3/ULP,
23 rue du Loess, BP20, F-67037 Strasbourg, France

Abstract:

A novel Monolithic Active Pixel Sensor (MAPS) for charged particle tracking made in a standard CMOS technology is proposed. The sensor is a photodiode with a special structure, which allows the high detection efficiency required for tracking applications. The partially depleted thin epitaxial silicon layer is used as a sensitive detector volume. A first prototype has been designed and fabricated using a standard sub-micron 0.6 um CMOS process. It is made of four arrays each containing 64 times 64 pixels, with a readout pitch of 20 um in both directions. Extensive tests made with soft X-ray source ( 55 Fe) and minimum ionising particles (15 GeV/c pions) fully demonstrate the predicted performances, with the individual pixel noise below 20 electrons(ENC) and the Signal-to-Noise ratio of the order of 40, both for 5.9 keV X-rays and Minimum Ionising Particles (MIP). A new version of the circuit has been submitted to the 0.35 um Alcatel-Mietec process. This novel device opens new perspectives in high precision vertex detectors as well as in other applications.

Summary:

A novel Monolithic Active Pixel Sensor (MAPS) for charged particle tracking made in a standard CMOS technology is proposed. The sensor is a photodiode, which is readily available in a CMOS technology. The diode has a special structure, which allows the high detection efficiency required for tracking applications. The partially depleted thin epitaxial silicon layer is used as a sensitive detector volume. Semiconductor device simulations, using either ToSCA based or 3-D ISE-TCAD software packages show that the charge collection is efficient and reasonably fast (order of 100 ns), and the charge spreading limited to a few pixels only. A first prototype has been designed, fabricated and tested. It is made of four arrays each containing 64 times 64 pixels, with a readout pitch of 20 um in both directions. The device is fabricated using standard sub-micron 0.6 um CMOS process, which features twin-tub implanted in a p-type epitaxial layer, a characteristic common feature to many modern CMOS VLSI processes. Extensive tests made with soft X-ray source ( 55 Fe) and minimum ionising particles (15 GeV/c pions) fully demonstrate the predicted performances, with the individual pixel noise below 20 electrons(ENC) and the Signal-to-Noise ratio of the order of 40, both for 5.9 keV X-rays and Minimum Ionising Particles (MIP). A new version of the circuit has been submitted to the 0.35 um Alcatel-Mietec process to improve radiation hardness and to explore the performance of deep-sub-micron technologies with thinner epitaxial layers and thus less primary exploitable ionization.

This novel device opens new perspectives in high precision vertex detectors in particle physics experiments at future colliders, as well as in other applications, like low energy beta particle imaging, visible light single photon imaging (using the Hybrid Photon Detector approach) and high precision slow neutron imaging.

Id: 75
Corresponding Author: Peter LICHARD
Experiment: ATLAS
Sub-system: Tracker
Topic: Electronics for Tracker

The new ATLAS TRT read-out system

Peter Lichard CERN-EP

Abstract:

The ATLAS TRT detector is very demanding in terms of electronics performance because of the high occupancy of the detector. A new version of the full read-out system, including two new ASICs and the new back-end modules, has been designed and tested successfully at 40 MHz clock rate and high trigger rate on a detector prototype. A description of this system will be given, as well as test results and plan for future scaling.

Summary:

The ATLAS TRT is  a gaseous detector consisting of 420000 straws covering the barrel and end cap regions. It aims at providing tracking information with a good resolution and electron identification. The large occupancy of the detector requires special care on the analogue signal processing to cancel the ion tail signal, data compression and use of high speed digital links. The drift time measurement performed on the front-end electronics is indispensable  for good tracking resolution.
A new prototype of the read-out chain working at 40 MHz has been developed, constructed and tested. The on-detector electronics consists of an 8 channel analogue front end chip containing a fast preamplifier, a tail cancellation circuitry, base line restorer and two discriminators, followed by a 16 channel read-out chips including a 3ns time to digital converter, the level1 trigger pipeline and the readout protocol to extract the data corresponding to a level 1 trigger signal.  The off-detector electronics consists of a new prototype of a scaled down ROD module, which concentrates the data from 832 channels, format the data and apply the zero suppression scheme and make the data available to the data acquisition system through S-LINK; and the new version of a TTC module with a new protocol for controlling the front-end electronics implemented.
A complete description of the different components of this chain is given, as well as test beam results.
A description of a new prototypes of  TTC and ROD modules is presented, including data compression schemes and TTC protocol.

Id: 76
Corresponding Author : Wladyslaw DABROWSKI
Experiment : ATLAS
Sub-system  : TRACK
Topic: Electronics for trackers

Progress in development of the readout chip for the ATLAS Semiconductor Tracker

W. Dabrowski, Faculty of Physics and Nuclear Techniques, UMM, Krakow, Poland
F. Anghinolfi, CERN, Geneva, Switzerland
A. Clark, University of Geneva, Switzerland
T. Dubbs, SCIPP, UCSC Santa Cruz, CA, USA
L. Eklund, CERN, Geneva, Switzerland
M. French, Rutherford Appleton Laboratory, Didcot, UK
W. Gannon, Rutherford Appleton Laboratory, Didcot, UK
A. Grillo, SCIPP, UCSC Santa Cruz, CA, USA
P. Jarron, CERN, Geneva, Switzerland
J. Kaplon, CERN, Geneva, Switzerland,
J. Kudlaty, MPI, Munich, Germany
C. Lacasta, IFIC, Valencia, Spain
D. LaMarra, University of Geneva, Switzerland
D. Macina, University of Geneva, Switzerland
I. Mandic, Jezef Stefan Institute, Ljubljana, Slovenia
G. Meddeler, Lawrence Berkeley National Laboratory, Berkeley, CA, USA
H. Niggli, Lawrence Berkeley National Laboratory, Berkeley, CA, USA
P.W. Phillips, Rutherford Appleton Laboratory, Didcot, UK
P. Weilhammer, CERN, Geneva, Switzerland
E. Spencer, SCIPP, UCSC Santa Cruz, CA, USA
R. Szczygiel, CERN, Geneva, Switzerland
A. Zsenei, University of Geneva, Switzerland

Abstract :

The development of the ABCD chip for the binary readout of silicon strip detectors in the ATLAS Semiconductor Tracker has turned into a pre-production phase, following comprehensive evaluation of the ABCD2T prototype chip. The ABCD2T design is one of the two options of the binary readout architecture which have been developed for the ATLAS SCT. It is manufactured in the DMILL process and comprises in a single chip all blocks of the binary readout architecture. In the paper we will present a summary of the ABCD2T performance as well as design issues and performance of the ABCD3T chip which is expected to be the final version for the ATLAS SCT detector.

Summary :

The development of the readout chip for silicon strip detectors in the ATLAS Semiconductor Tracker has entered into a pre-production phase, following comprehensive evaluation of the recent ABCD2T prototype chip. The ABCD2T design is one of the two options of the binary readout architecture which have been developed for the ATLAS SCT. It is manufactured in the DMILL process and comprises in a single chip all blocks of the binary readout architecture, the front-end circuits, discriminators, binary pipeline, derandomizing buffer, data compression logic, and the readout control logic as required for the ATLAS SCT. A significant improvement of the chip performance has been achieved by implementation of the individual threshold correction in each channel using a digital-to-analogue converter (TrimDAC) per channel.

Detailed evaluation of the ABCD2T design has been performed employing specific test procedures separately for the analogue and digital blocks. The design meets most of the specification, however, the test results indicate that some corrections and improvements are still possible. In particular, this applies to the TrimDAC circuit which is used for threshold correction in each channel. The response characteristics of this circuit exhibit significant non-linearity which degrades the final uniformity of the threshold. The source of the problem has been identified and corrected in the ABCD3T design.

In parallel to detailed evaluation the ABCD2T design the chips have been used extensively for building prototype SCT detector modules using various hybrid layouts and technologies. This work provided us with a complete evaluation of the chip performance.

The DMILL technology is qualified as a radiation resistant one, however, the radiation levels expected for the SCT detector in the ATLAS experiments are at the upper limits of those specified for the DMILL process, i.e. 10 Mrad of the ionising dose and 1E14 n/cm2 1 MeV eq. neutron fluence. In addition, if one takes into account very advanced requirements regarding the noise, speed and power consumption of the ABCD2T chip, it becomes obvious that radiation effects in the basic devices, although limited, can not be ignored.

Radiation hardness of the chip was evaluated in various tests which covered the total dose effects and the single event upset effects. The performed radiation tests indicated for some potentially weak points in the design. The two most important were a significant increase of the digital power consumption and decrease of the signal level in the token/data passing circuit after total ionising dose of 10 Mrad. Both problems have been traced down to particular circuit structure which are sensitive to drift of device parameters after irradiation. More robust solutions for these particular circuits have been elaborated and implemented in the ABCD3T chip.

In total, 16 wafers with the ABCD2T chips split in two different batches have been manufactured at TEMIC foundry. All the chips were fully tested at the wafer level and detailed analysis of yield and failure modes was performed.

In the paper we will present a summary of the ABCD2T performance as well as design issues and performance of the ABCD3T chip which is expected to be the final version for the ATLAS SCT detector.

Id: 77
Corresponding Author: Jonathan FULCHER
Experiment: CMS
Sub-system: Tracker
Topic: Electronics for Tracker

Single Event Upset Studies on the APV25 Readout Chip

J Fulcher, G Hall, E Noah , M Raymond
Imperial College, London, UK

D Bisello, G. Marseguerra, J Wyss
Padova University, Padova, Italy

M French, L Jones, Q Morrissey, A Neviani
Rutherford Appleton Laboratory, Didcot, UK

Abstract

The microstrip tracker for the CMS experiment at the LHC will be read out using APV25 chips.  During high luminosity running of the LHC the tracker will be exposed to particle fluxes up to 107 cm2 s-1.  This high rate of particles introduces a concern that the APV25 could occasionally suffer from Single Event Upset (SEU).  In order to evaluate the expected upset rate under these circumstances the APV25 was run under controlled conditions in a heavy ion beam.  This enabled the measurement of the SEU upset cross-section, and hence a prediction of the upset rate in CMS.  The upset cross-section for a range of particle LETs (Linear Energy Transfer) was measured and the referred threshold energy and saturated cross-section was evaluated.  These data are then used to predict the upset rate for the APV25 in the CMS tracker.

Summary

During the research and design phases of the APV chip, much care has been taken to assure a high degree of total dose radiation tolerance.  The chips have been fabricated in AVLSI-RA Bulk CMOS, DMILL and deep sub-micron processes.  Extensive testing has been carried out on representative test structures from various processing runs, and the degree of radiation tolerance of these processes has been thoroughly investigated, including SEU measurements of the APV6 (the bulk CMOS version). However, the susceptibility of the APV25 to SEU was not known.  The new version of the APV has been fabricated in a 0.25 mm technology, in which the SEU effect is not yet well measured, so a full understanding of the implications of these single event effects is imperative.  An investigation of the behavior of the APV25 in a heavy ion beam makes it possible to extrapolate from the data to predict the SEU rate in the final system.

SEU is a non-destructive phenomenon, which affects the digital memory registers that store logic states within the APV.  It manifests itself as a soft error appearing in a device and is caused by the deposition of charge by an ionizing particle.  In the APV25 soft errors could cause a variety of undesirable effects, some of which would result in temporary malfunction and possible loss of data.  In the event of such errors the APV can be reset and after a latency ( ~ 3 ms ), normal operation would resume.  It is clear that an understanding of the upset rate will help in the determination of the required reset rate of the tracker, therefore it is important that this rate be evaluated to enable considered design of this part of the tracker system.

In order to calculate the predicted upset rate in the final system an evaluation of the SEU sensitivity was carried out by placing the APV25 in a beam of heavy ions, at the TANDEM accelerator at INFN Legnaro in Italy and measuring the SEU cross-section.  This was achieved by measuring the beam fluence and LET value along with the number of chip upsets caused by the heavy ion beam during a particular time interval.  Cross-section curves, in the case of heavy ion irradiation, typically represent the cross-section of the device as a function of Linear Energy Transfer (LET) of the bombarding ions.  These curves generally have a threshold LET, where upsets begin to appear, and a saturating cross-section for high values of LET.  These two defining features of the device behavior can then be used to make a prediction of the upset rate for other forms of radiation.  For the CMS tracker, the required calculations are complicated since the particles are typically of single charge and therefore only cause large enough ionization by virtue of nuclear interactions with silicon lattice sites.  Calculations of the cross-section through simulations of such interactions have been performed and form the basis of the SEU predictions in the CMS tracker

The results of the test have provided good measurements giving a threshold LET of around 13 MeV.cm2.mg-1, and the SEU cross-section for important elements of the circuit. Predictions have been made of SEU rates in CMS, of less than 10-6 upsets.chip-1.s-1, which allow detailed planning of the CMS system operation.

Id: 83
Corresponding Author: Geoff HALL
Experiment: CMS
Sub-system: Tracker
Topic: Electronics for Tracker

The CMS Tracker APV25 0.25µm CMOS readout chip

M. J. French, L. L. Jones, Q. Morrissey, A. Neviani, R. Turchetta
Rutherford Appleton Laboratory, Didcot, OXON, OX11 0QX, United Kingdom

J. Fulcher, G. Hall, E. Noah, M. Raymond
Blackett Laboratory, Imperial College, London SW7 2AZ, United Kingdom

K. Kloukinas, P. Moreira
CERN, 1211 Geneva 23, Switzerland

N. Bacchetta, D. Bisello, G. Marseguerra, J. Wyss
University of Padova, Italy

Abstract:

The APV25 is the 128-channel readout chip for silicon microstrips in the CMS tracker. It is the first major chip for a high energy physics experiment to exploit a modern commercial 0.25µm CMOS technology. Experimental characterisation of the circuit shows full functionality and excellent performance both in pre- and post-irradiation conditions. The measured noise is significantly reduced compared to earlier APV versions. Automated on-wafer testing of many chips has demonstrated a very high yield. A summary of the design and detailed results from measurements will be presented. Operation of the chip in conjunction with other CMS system components will be described.

Summary:

The chip has dimensions 8mm x 7.15mm. Each APV25 channel contains a preamplifier and shaper, with a 50ns peaking time, followed by a 192 deep memory into which samples are written at 40MHz. Locations of data awaiting readout are flagged so they are not overwritten. Following a trigger, three samples from the memory are processed with the APSP deconvolution filter, which re-filters the data with a shorter time constant.
The APV25 contains system features including programmable on-chip analogue bias networks, a remotely controllable internal test pulse generation system and a slow control interface which allows programmable setting of bias currents and voltages in the amplifier and shaper, choice of operation mode, calibration, latency adjustment and error reporting, etc.
The preamplifier is a charge sensitive amplifier with a PMOS input transistor of dimensions 2000µm/0.36µm and current of 400µA. It consumes 0.9mW and is the dominant contribution to the total APV25 power budget of 2.3mW/channel. The power supplies are +1.25 and –1.25V. A switchable unity gain inverter is used to allow signals of either polarity to be measured. The shaper is an effective CR-RC filter with shaping adjustable over a limited range. The total front end gain of the amplifier is approximately 100mV/MIP (25000e).
The pipeline is a 128 by 192 array of switched capacitor cells. Each cell comprises two transistors, to perform the read or write operation, and a storage capacitor. The pipeline is read out by the APSP processor which is an amplifier with a switched capacitor network in the feedback loop. The ratios of capacitors define the weights used by the deconvolution algorithm.
A 128:1 multiplexer drives the analogue output from the chip which emerges at 20MS/s following a digital header sequence in a current form. Data from two APV25 chips are interleaved at the APVMUX chip to arrive at the final transmission speed of 40MS/s.

Results:

The chip functionality was complete after a single design iteration. However, it was noted that the resistance of the input lines to the amplifier could be reduced so the noise performance of the final version, which is now in fabrication, will improve further on this.
The peak mode pulse shape is a very good approximation to ideal 50ns CR-RC pulse shaping. The deconvolution mode data accurately achieve the short pulse shape expected for single bunch crossing timing. Irradiations have taken place using x-rays, 10MeV electrons and reactor neutrons to fluence levels greatly in excess of those expected in CMS; all results are excellent. Very minor changes in performance are seen after high ionising doses.
Automatic wafer testing of each chip will identify “known good die” which will be cut from wafers and assembled onto hybrids. A system is already in operation  and the time required to test each APV die on the wafer is less than 2 minutes. Measurements from several hundred chips show yields of  perfect chips of more than 80%, which is excellent for a complex circuit of 57mm2 in size.
Single Event Upset studies have been carried out in heavy ion beams which will be presented in an accompanying paper to the workshop.

Id: 84
Corresponding Author: Ken WYLLIE
Experiment: ALICE & LHCB
Sub-system: Tracker
Topic: Electronics for Tracker

First results from the ALICE1LHCb pixel chip

K. Wyllie1), M. Burns1), M. Campbell1), E. Cantatore1), V. Cencelli2), P. Chochula1), R. Dinapoli3), S. Easo4),
F. Formenti1), T. Grassi1), E. Heijne1), P. Jarron1), K. Kloukinas1), P. Lamanna3), F. Meddi1), M. Morel1), V. O’Shea4),
V. Quiquempoix1), D. San Segundo Bello5), W. Snoeys1), L. Van Koningsveld1)

1) CERN, Geneva, Switzerland
2) INFN Rome, Italy
3) University and INFN Bari, Italy
4) University of Glasgow, Glasgow, UK
5) NIKHEF, Amsterdam, The Netherlands.

Abstract:

ALICE1LHCb is an integrated circuit to read out silicon pixel sensors used for particle tracking in the ALICE Silicon Pixel Detector or for particle identification in the LHCb RICH. It has been fabricated in a commercial 0.25 micron technology, with consideration given to radiation tolerance, testability and system integration.
Results from the first laboratory measurements are presented. These include characterisation of the front-end, with measurements of noise and threshold uniformity. The functionality of the digital circuitry is described whilst operating the chip in both ALICE and LHCb modes. The use of the serial JTAG interface is outlined, in terms of configuring the chip and testing connectivity at the system level.

Summary:

The ALICE1LHCb chip has been designed to read out silicon pixel sensors used for particle tracking in the ALICE Silicon Pixel Detector or for particle identification in the LHCb RICH.
In ALICE, chips will be bump-bonded to thin sensors mounted on staves forming a barrel geometry, and must be sensitive to minimum-ionising particles. In LHCb, single chips will be encapsulated within the vacuum envelopes of hybrid photon detectors, and must be sensitive to photoelectrons of energy ~20keV.
The architecture of the chip has been designed in such a way that it can be operated in one of two different modes to suit the application. This was presented at LEB99 [1].

The chip has been fabricated in a commercial 0.25 micron technology. Tolerance to total-dose radiation effects is enhanced by the use of an enclosed 'edgeless' transistor layout, and guard-rings are used to eliminate inter-component leakage and radiation-induced latch-up. Special circuit designs are used for memory elements to render them immune to single-event upset.

The chip has a total sensitive area of 12.8mm * 13.6mm, sub-divided into pixel cells of 50 microns * 425 microns. Each cell contains an analog front-end followed by a discriminator, two digital delay units, a FIFO memory and readout logic. First measurements are presented on the performance of the front-end, including the noise levels, channel-to-channel threshold variations and timewalk.

The digital functionality has been tested, with data obtained while operating the chip in ALICE mode with a clock frequency of 10MHz and in LHCb mode with a clock frequency of 40MHz.

The use of the JTAG serial interface is described. This is used both to read and write configuration data into the chip, and to test its connectivity by means of boundary-scanning the input/output pads.

[1] "A Pixel Readout Chip for Tracking at ALICE and Particle Identification at LHCb", 5th Workshop on Electronics for LHC Experiments, Snowmass, Colorado, USA, 20-24 September 1999.

Id: 86
Corresponding author: Mitch NEWCOMER
Experiment: ATLAS
Sub-system: Tracker
Topic: Electronics for Trackers

Implementation of a Digital Time Measurement Chip (DTMROC99)in DMILL for the ATLAS TRT

C. Alexander, F. Anghinolfi, R. Van Berg, N. Dressnandt, T. Ekenberg, Ph. Farthouat, P. T. Keener, N. Lam, D. Lamarra, J. Mann, F. M. Newcomer, V. Ryjov, M. Soderberg, R. Szczygiel, H.H. Williams

Abstract:

A 16 channel digital time measurement and readout chip, the DTMROC99, has been designed and built in DMILL, a BI-CMOS rad-hard process. This chip  is designed to accept low level ternary inputs from the ASDBLR99, a companion analog front end chip, to record the time of arrival of avalanche signals from tracks with 1ns precision as well as to record the detection of Transition Radiation photons in a 144 bit data word. Data is stored in a 3.3us pipeline and transferred to a 13 deep buffer if a Level 1 trigger is decoded.  In addition to its main readout function, the chip provides four threshold voltages and two test pulse outputs for the two ASDBLR's it reads out.  Communication utilizes specially designed LVDS compatable, low power differential inputs and outputs.

DESCRIPTION OF CHIP:

The DTMROC99 is a digital time measurement and readout chip for the ATLAS TRT straw tube detector. It receives 16 channels of differential ternary encoded signals from two 8 channel ASDBLR99 chips. The ternary (3-level) signals are a composite of two binary discriminator output pulses: one unit of current indicating the presence of a charged particle track and a two unit pulse indicating that the track amplitude is large enough to be from transition radiation. (i.e. caused by an electron track.)

In the DTMROC99 chip, these ternary signals are decoded back into separate ``tracking" and ``transition" pulses by TERNARY RECEIVERS. The transition pulses' existence or absence is recorded at 25ns intervals timed by the 40MHz system clock (BC). The tracking pulse is essentially digitized by sampling for its presence or absence every 3.125ns and setting a bit accordingly. In this way an 8-bit word is generated defining the leading edge and width of the tracking pulse to a resolution of 3.125ns. Eight 40MHz clocks (BC1 - BC8) each delayed by the appropriate multiple of 3.125ns are derived from the system clock using a Delay-Locked-Loop (DLL).

This 8 bit time sample word plus the transition-radiation bit are formed into 9-bit words. All 16 channels then form 144 bits for each 25ns time period. This data is stored in a PIPELINE for 132 clock cycles during which time the decision whether or not to retain the data is made. If a trigger signal (Level 1 accept) is sent to the DTMROC99 chip, the data is stored in a DERANDOMIZER, and then read out of the chip as a serial 40MHz data stream under the control of the READOUT CONTROLLER.

All this is under the full control of a COMMAND DECODER which accepts an external serial bit stream and issues the appropriate control signals to the chip sub-blocks.

Special LVDS compatable RECEIVERS and DRIVERS are used to communicate with the outside world to avoid generation of noise near the sensitive ASDBLR99 chip inputs.

In addition, the DTMROC99 also provides two TESTPULSE and four THRESHOLDS for the two ASDBLR99 chips. Testpulse outputs provide a shaped signal to generate a current pulse similar the signal produced by the straw sensor when filled with the TRT optimized Xe/Ar/CO2 mixture. Both the amplitude and delay of these testpulses are programmable. Four six bit DACs provide  a tracking and transition radiation threshold for each ASDBLR.

DESIGN METHODOLOGY

The chip is an assembly of analog and digital blocks contributed by five institutions and integrated at the chip level by a private firm. Analog block performance was confirmed using SPICE and digital blocks were confirmed (and in some cases designed) using Verilog.  Subsequent to design, a Verilog representation for each analog block was written to allow a full hierarchical chip level connectivity representation. This verilog representation was  used to perform basic functionality tests prior to submission and to develop test vectors used to drive the chip tester after fabrication.

VERIFICATION OF THE FINAL DESIGN

Verilog models were specified only for nominal process conditions. Derating factors were applied to account for changes due to process, supply voltage, temperature and radiation effects, but differences between SPICE and verilog calculations led to the conservative and time consuming approach of checking the design using SPICE on the extracted netlist. In practice large interconnected sections were simulated together and the internal parts of some blocks such as the the pipeline were carefully reduced in complexity to allow meaninnful simulation results to be available within a one week time frame.  Using this process several several timing errors were identified and fixed prior to submission. In some cases, the timing was unacceptable only when two or more contitions were not nominal.  These were noted and accepted in order to get
actual experience with the design.

CHIP FUNCTIONALITY

PERFORMANCE

The chip is fully functional and its performance is accurately predicted by simulation tools. Overall, the standard deviation of time bin width is measured to be less than 1ns for all working chips. Ternary input signals as short as 4ns have been reliably detected.

* RADIATION TESTS

No performance degradation was observed after exposure to 1E14 neutrons/cm**2. Proton irradiation to 1e14p/cm**2 has been performed and we are awaiting the return of the exposed parts. In addition, we expect to perform SEU tests in the late spring or summer.

* BEAM STUDIES

A board employing four DTMROC99 chips and eight ASDBLR99's has been designed at CERN to be compatible with the TRT wheel prototype. We intend to use this board to instrument a prototype wheel and test the full readout chain at the CERN H8 beamline this summer.

Id: 87
Corresponding Author: Etam NOAH
Experiment: CMS
Sub-system: Tracker
Topic: Electronics for Trackers

Total Dose irradiation of a 0.25µm process

M. J. French
Rutherford Appleton Laboratory, Didcot, OXON, OX11 0QX, United Kingdom

I. Dindoyal, G. Hall, E. Noah, M. Raymond
Blackett Laboratory, Imperial College, London SW7 2AZ, United Kingdom

D. Bisello
University of Padova, Italy
 

Abstract

A commercial 0.25µm process will be used for various electronic components of the CMS tracker, one of these being the APV25 readout chip for silicon microstrips. Irradiating and measuring individual transistors is important in assessing the radiation tolerance of the chip. Transistors from two different foundries owned by the same company were irradiated up to doses of 50Mrad(SiO2) with a 10keV X-ray source. Threshold voltage shifts of up to 140mV were observed whilst noise measurements showed very little degradation in the white noise region after irradiation and annealing. Detailed results of both static characteristics and noise will be presented.

Summary

High speed, low noise and low power consumption are some of the requirements placed on electronics for the LHC. The electronic components also have to survive the harsh radiation environment with ionising doses of up to 10Mrad being reached in the inner tracker regions of CMS. The readout system for the silicon microstrips adopted by the CMS collaboration is based on the APV chip series. The APV25 is the latest chip in the series and is designed in a commercial 0.25µm CMOS technology. This paper reports on a total dose radiation study of transistors manufactured by two different foundries (referred to as foundry A and foundry B) employing the same 0.25µm process. The static characteristics and noise of the transistors were measured before and after irradiation and annealing.

The largest noise contribution in the APV25 comes from the input PMOS transistor of the preamplifier, which has dimensions of 2000µm/0.36µm. All the PMOS transistors measured had a width of 2000µm and lengths varying from 0.24µm to 0.64µm. The NMOS transistor measured had dimensions of 2000µm/0.36µm.

An X-ray source was used to irradiate the transistors in steps up to a dose of 50Mrad(SiO2), with measurements being made after each step. The X-ray tungsten tube was operated at 50kV. This, along with the aluminium filtering ensured that 80% of the dose was delivered by radiation around 10keV. During irradiation, the transistors were biased so as to be under normal operating conditions. During the annealing stage, the transistors were biased and kept at a temperature of 100oC.

Measurements of the static characteristics showed threshold voltage shifts of up to 140mV for PMOS transistors. Some annealing of these transistors reduced the shifts to around 90mV. In addition, there was no significant degradation of the sub-threshold slope or the transconductance. The shift in the threshold voltage for the NMOS transistor was 15mV after 50Mrad(SiO2), increasing to 75mV after annealing. There was some small degradation of the transconductance and the sub-threshold slope for the NMOS transistor.  The threshold voltage shifts observed would not significantly affect the functionality of a chip such as the APV25.

Noise measurements were made with the transistors in saturation and in the moderate to strong inversion region with a drain current of 500µA and a drain voltage of 0.5V. A comparison of the noise before and after irradiation for PMOS transistors shows very little difference for frequencies above 1MHz (higher than the corner noise frequency), which is the region of interest.

After a total dose of 50Mrad(SiO2), 5 times higher than the predicted total dose in the CMS tracker, all the transistors from both foundries were fully functional, showing very small changes in static characteristics and no significant increase in noise levels. The results suggest a small difference in oxide quality between the two fabrication runs.

Id: 88
Corresponding Author: John COUGHLAN
Experiment: CMS
Sub-system: Tracker
Topic: Electronics for Trackers

Design of the Front-End Driver card for CMS Silicon Microstrip Tracker Readout.

S.A. Baird, K.W. Bell, J.A. Coughlan, R. Halsall, W.J. Haynes, I.R. Tomalin
CLRC Rutherford Appleton Laboratory, Oxon, UK.
E. Corrin
Imperial College, London, UK.

Abstract:

The CMS silicon microstrip tracker has the order of 10 million readout channels. The tracking readout system employs several hundred off-detector Front-End Driver (FED) cards to digitise, sparsify and buffer analogue data arriving via optical links from on-detector pipeline chips (APVs). This paper describes the baseline design of the Front-End Driver card which is implemented as a 96 ADC channel (10 bits) 9U VME board. At typical LHC operating conditions the total input data rate per FED after digitisation of over 3 GBytes/s must be substantially reduced. The required digital data processing is highly parallel and heavily pipelined and is carried out in several large FPGAs. The process of FPGA digital design using VHDL and design optimisaton with board level simulation together with the tools employed are discussed.

Summary:

The CMS silicon microstrip tracker has the order of 10 million readout channels. The tracking readout system employs several hundred off-detector Front-End Driver (FED) cards to digitise, sparsify and buffer analogue data arriving via optical links from on-detector pipeline chips (APVs). The Front-End Driver card is currently in the final stages of design. The baseline FED design is implemented as a 96 ADC channel (10 bits) 9U VME board. Each ADC channel receives multiplexed data from 2 front end analogue pipelined ASICs (APVs). The essential features of data processing are as follows. In the first stage the amplitude modulated optical data is converted to electrical levels by opto-receiver packages containing PIN diodes and a custom amplifier ASIC. The analogue data is digitised at 40 MHz by 10 bit commercial ADCs.
The data from each ADC is then processed in its own independent digital pipelined processing logic. Following the recognition of the header accompanying each data frame from the APV, pedestals are removed and the common mode is calculated and subtracted. The APV strip data must then be re-ordered before applying the cluster finding algorithm. The final sparsified data from all ADC channels is then collected, formatted and buffered locally before transferal to the next layer of the CMS data acquisition system.
The entire digital logic is programmed in VHDL and implemented in several large FPGAs. The latest tools are being employed in the FPGA design. Extensive use has being made of simulation tools to optimise the level of internal data buffering. Monte-Carlo generated tracker data is also used to test possible hit and cluster finding FPGA algorithms. Hardware-software co-simulation allows the software for the control and monitoring of the FED to be developed and tested in parallel with the hardware design. The importance of adopting standards in the design process to facilitate testing and maintenance of such a large system is discussed.
The FED is designed to operate at the CMS level 1 trigger rate of 100 kHz. The resulting input rate per FED after digitisation of over 3 GByte/s will be reduced to an average output rate per FED of approximately 150 MByte/s at the expected average hit rates in the tracker. The baseline design will have a total of 500 FEDs in the tracker readout system and will provide over 70% of the final CMS data volume.

Id: 90
Corresponding Author: Cristoforo MARZOCCA
Experiment: ALICE
Sub-system: Tracker
Topic: Electronics for Tracker

Design and Characterization of a DAC for the Slow Control of the Pixel Chip

F. Corsi (*), R. Dinapoli (*)(#), P. Lamanna(*), C. Marzocca(*)
* Dipartimento di Elettrotecnica ed Elettronica - Poltecnico di Bari
# INFN - Sezione di Bari

Abstract :

A digital to analog converter for slow control of pixel front end chip has been designed in a 0.35 um standard CMOS technology to prove the effectiveness of the chosen circuit structures for this application. The DAC provides a total output current variation of about 15uA with an accuracy of 8 bits (LSB=60nA).

The DAC is based on a PMOS current bank (an NMOS of a reasonable size would operate in the weak inversion region for these current levels and would hence be unsuitable for accurate current sources). The bit value determines whether the current corresponding to these bit is switched to the output or not.
The occupied area is about 300um x 300um and total power dissipation is 85uW.  The results of the test measurements performed on the 36 fabricated prototypes show that statistical fluctuations of the output current due to mismatch are negligible compared to the desired accuracy for all the input configurations.

Summary :

To ensure uniformity of all channels in a pixel system containing many readout chips, the bias of each chip has to be controlled individually. This is readily done using on-chip DACs for biasing. This also allows to re-optimize the settings for every chip regularly to compensate for radiation induced variations.
The main specifications for this current output digital to analog converter include area occupation and power dissipation, radiation hardness and accuracy which must be guaranteed in presence of device mismatch and significant irradiation dose.
The proposed DAC structure has been implemented in a standard 0.35 um deep-submicron CMOS technology with special layout techniques to obtain radiation tolerance. The core of the circuit is an array of 2^n-1 elementary current sources realized with PMOS transistors suitably biased and dimensioned to deliver the current Ibit corresponding to the least significant bit of the DAC. Starting from the power available, the desired output current variation, expressed as a fraction of the maximum output current, and the needed accuracy set the value of Ibit and the number of bits of the DAC. For a minimum area design, W=Wmin has been chosen.
The value of the length L and, thus, the overdrive Vgst, have been defined considering the matching properties of the transistors employed as a function of W and L.

The variance of the output current has been expressed in terms of the matching parameters of the technology used and, imposing that this variance is less than Ibit, the minimum length of the elementary current source has been derived. Of course the dimensions of the current source array must be compatible with the total area available, otherwise the number of bits must be reduced.

Global variations of the MOS threshold voltage are compensated by means of an all-PMOS bias circuit based on a threshold extractor. The 2^n-1 elementary current sources are suitably summed in order to obtain the n bit currents, scaled as the powers of two. The DAC configuration is set by means of n PMOS deviators, which send the related bit current toground or to the output stage of the circuit. This stage is needed to rescale the current delivered by the source array to the value required by the application, in our case 10uA, and is based on the concept of current reflector.

Up to now measurement tests have been performed on 22 out of the 36 prototypes manufactured of the 8 bit DAC. The results show that the absolute differential non-linearity error is always less than one half of the minimum output step Ilsb, whose average value is 60nA, thus achieving the 8 bit accuracy. The following table summarizes the main measurement results.

Average offset error                            274nA

Gain variance                                   2.2 %

Max Integral Nonlinearity Error                 118nA

Max Differential Nonlinearity Error             27nA

Measurements on the remaining prototypes are still in progress and radiation hardness characterization of the DAC will take place soon after.

Id: 91
Corresponding Author: Michael BURNS
Experiment: ALICE
Sub-system: Tracker
Topic: Electronics for Tracker

The ALICE Silicon Pixel Detector Readout System

Federico ANTINORI (1), Jaroslav BAN (2), Michael BURNS (1), Michael CAMPBELL (1), Peter CHOCHULA (1, 3), Fabio
FORMENTI (1), Tullio GRASSI (4), Alexander KLUGE (1), Pierluigi LISCO (5), Franco MEDDI (1, 6), Michel MOREL (1),
Giorgio STEFANINI (1), Kennith WYLLIE (1)

(1) CERN, 1211 Geneva 23, Switzerland
(2) Institute of Experimental Physics, 04353 Kosice, Slovakia
(3) Institute of Experimental Physics, 84215 Bratislava, Slovakia
(4) Formerly CERN, 1211 Geneva 23, Switzerland
(5) Universita degli Studi di Bari, I-70126 Bari, Italy
(6) Universita di Roma La Sapienza, I-00185 Roma, Italy

Abstract:

The ALICE SILICON PIXEL DETECTOR (SPD) is located within the Inner Tracking System (ITS) and is the detector with
the highest active channel density and closest to the point of interaction.

Approximately 10 million active electronic channels, contained in a volume of 34 litres, have to be read out and
controlled.

Such a high density in an inaccessible position have imposed a high degree of multiplexing to reduce the amount of
cabling to a minimum.

This paper will describe the proposed architecture of the readout and control paths.
 

Summary:

The basic building block of the ALICE SPD is the ladder consisting of a Pixel detector matrix flip-chip bonded to
five front end readout chips.

Four ladders are aligned in the beam direction, glued and wire bonded onto a bus to form a 33cm long stave. Two
pilot chips are located at the extremities of this bus to perform the readout and control functions and transmit the
digital data to a remote Router which will assemble the data for transmission to the DAQ.

Six staves, two from the inner layer and four from the outer, are mounted on a carbon fibre support and cooling
sector. Ten such sectors are then mounted together around the beam pipe to close the full barrel. In total there
will be 60 staves, 240 ladders, 1200 chips, 9.83 * 10^6 cells or active channels of read out.

Each front end readout chip contains a mixture of analogue and digital circuitry for the readout of 8192 detector
cells which are arranged in a matrix of 256 rows by 32 columns. Each cell comprises of a preamplifier/shaper,
discriminator, trigger latency delay line, a four event de-randomising buffer and an output shift register.

Acquisition and readout are independent activities which are performed in parallel. Both are controlled by the Pilot
chip. The front end chips run as slave devices. The Pilot chip, on receipt of a L1 trigger signal will cause the
detector hit pattern to be stored in the first free location of the de-randomising buffer of the front end chip. The
L2 decision will determine whether the front end chip is read out or not. A L2Y will cause each Pilot chip to
initiate a read out cycle by a sequential addressing of its own ten front end chips. The data from the addressed
de-randomising buffer are shifted out of the front end chip into the Pilot chip and serialised for transmission over
an optical fibre link to the Router module which will be located outside of the ALICE detector. A L2N will cause the
data from the de-randomising buffer to be ignored. In each case the de-randomising buffer location is freed for
future use.

Each Router will receive the data from six optical fibre links. Each Router input stage will perform, on the fly,
zero suppression of the redundant data before formatting for insertion into the DAQ via the ALICE DDL. The controls
for the pilot chips and readout chips will be issued by the Router on reception of the trigger system decisions. The
Router also monitors the readout chip de-randomising buffer usage and issues the appropriate busy to the DAQ
control. Additional memory is contained to provide multi-event buffering. An additional data path has been supplied
to enable spying on the event data.

The control, parameter loading and testing of the front end chip is realised by JTAG. A JTAG controller is
incorperated in the Router module. Currently two solutions for making the JTAG connection between the Router module
and Pilot chip are under evaluation. Either to use a short copper link of <50 metres or employing a second optical
fibre link which would not have such a length constraint.

Id: 99
Corresponding Author: Bernardo MOTA
Experiment: ALICE
Sub-system: Tracker
Topic: Electronics for Trackers

Digital Implementation of a Tail Cancellation Filter for the Time Projection Chamber of the ALICE Experiment

R.E.Bosch, B. Mota, L. Musa
CERN, Geneva (Switzerland)

FOR THE ALICE COLLABORATION

Abstract:

In the ALICE TPC, the readout chambers are conventional multiwire proportional chambers with cathode pad readout. The pad signal has a rather complex shape, which depends on the details of the chamber and the pad geometry, characterized by a long tail due to the motion of the positive ions. Since the zero suppression has to be done before the data transfer, the high channel occupancy calls for a very precise tail suppression. In order to be compatible with the required dE/dx resolution, a suppression to 0.1% or better of the maximum pulse height, is required. We present a digital implementation of a shortening filter based on the approximation of the tail by the sum of exponential functions.The hardware implementation of the filter is described and the results analyzed.

Summary:

The ALICE TPC, of cylindrical shape, will be 500cm long, subdivided into two drift spaces of 250cm by a central plane, and extends in the radial direction from 84cm radius out to 247cm. The image charge is detected by 570 000 pads located on two readout planes at the cylinder end-caps. The readout planes are based on conventional multiwire proportional chambers with cathode pad readout. The chambers deliver on their pads a current signal with a fast rise time (less than 1ns), and a long tail due to the motion of the positive ions. For every pad, the current is integrated and subsequently shaped by a shaping amplifier. The pulse-height spectrum covering a maximal drift time of 88us is sampled at about 6MHz. The large granularity of the ALICE TPC (about 3 x 10^8 pixels) leads to a large event size (300MByte) and a data volume in the front-end that, at a trigger rate of 200Hz required for the ALICE physics program, is far beyond the limit of the present data handling techniques. Therefore, the zero suppression has to be done in the front-end electronics before the data is transferred to the DAQ system. Moreover, the ALICE TPC will cope with an extremely high charged particle multiplicity. A typical central Pb-Pb event, for instance, will produce about 3x10^4 tracks in the detector acceptance, which correspond to an occupancy of 40% in the inner most regions of the TPC. Therefore, in order to perform effectively the zero suppression, the pile-up effects have to be minimized and, consequently, the long signal tail has to be suppressed very precisely. In order to be compatible with the required dE/dx resolution, a suppression of 0.1% of the maximum pulse height, is required.

The pad signal has a rather complex shape that depends on the details of the chamber and the pad geometry. The 1/t tail behavior from a closed proportional tube is replaced by a bipolar signal due to the particular motion of the positive ions relative to the pad and wire planes. The negative undershoot reaches several per mille of the peak pulse height and falls into the normal drift time regime of a TPC. The measured TPC signal can be fitted, with the required accuracy, by the sum of N exponential functions. The latter can be expressed as the convolution of the initial impulse charge and a signal transfer function corresponding to the sum of the exponential terms. The cancellation of the tail is then realized by deconvolution filtering technique.

The accuracy of the filter realized as analog network is limited by the tolerance of its components. Owing to the poor precision in the matching of the passive elements, provided by the actual integrated circuit technologies, an analog implementation of the filter cannot reach an accuracy of 0.1% if the use of external tunable components has to be avoided. On the other hand, a digital system allows much better control of the accuracy requirements by choosing the word length and type of arithmetic (fixed point versus floating point). Furthermore, a digital system allows flexibility in reconfiguring the digital signal processing operations by changing programmable coefficients. This is indeed extremely important, considering that the exact shape of the signal is known with high accuracy only when the detector is operated. Moreover, this allows some flexibility in the choice of the gas composition and drift field depending on first running experiences. A N-1 order digital filter can be deduced in a way that N-1 of the poles of the signal transfer function are cancelled. The remaining exponential is the fastest and it allows the output to reach 0.1% of the maximum pulse height after 1 to 2 microseconds. Since the digital filter is part of the front-end electronics, it has to be fast, in order to process a new sample each 6MHz clock cycle, and sufficiently small for cost and power consumption reasons. A 16-bit words and fixed-point arithmetic is consistent with the 0.1% accuracy. Preliminary synthesis of a 2nd order filter with the standard cells library of a 0.35um CMOS process leads to a circuit of about 1500 gates, and a propagation delay below 100ns.
This circuit showed the required accuracy on measured detector signals

Id: 101
Corresponding Author: Jan KAPLON
Experiment: ATLAS
Sub-system: Tracker
Topic: Electronics for Trackers

Analogue Read-Out Chip for Si Strip Detector Modules for LHC Experiments
E. Chesi1, J. A. Clark2, V. Cindro3, W. Dabrowski4, D. Ferrere2, G. Kramberger3, J. Kaplon1, C. Lacasta5, J. Lozano1, M. Mikuz3, C. Morone2 S. Roe1, A. Rudge1, R. Szczygiel6, M.Tadel3, P. Weilhammer1, A. Zsenei2
1CERN, 1211 Geneva 23, Switzerland
2University of Geneva, Switzerland
3Jozef Stefan Institute, Ljubljana, Slovenia
4Faculty of Physics and Nuclear Techniques, UMM, Krakow, Poland
5IFIC, Valencia, Spain
6Institute of Nuclear Physics, Krakow, Poland

Abstract

We present a 128-channel analogue front-end chip SCT128A for readout of silicon strip detectors employed in the inner tracking detectors of LHC experiment. The architecture of the chip and critical design issues are discussed. The performance of the chip has been evaluated in detail in the bench test and is presented in the paper. The chip is used to read out prototype analogue modules compatible in size, functionality and performance with the ATLAS SCT base line modules. Several full size detector modules equipped with SCT128A chips has been built and tested successfully in the lab with b particles as well as in the beam test.

Summary:

The LHC operating conditions present a very big challenge to the front-end electronics of Si trackers for experiments designed for high luminosity physics. Historically most collider experiments have so far used full analogue readout front-ends for Si trackers and vertex detectors. This method allows individual treatment of data in each channel with optimised and adaptable software and thereby the most detailed control and monitoring of the whole system. Analogue readout is to a large extent immune to external electromagnetic pickup (common mode) since common mode noise can be fully eliminated with software. The price to pay for this safety is a heavier load on data transmission off the detector over optical links, both in bit rate and in the required number and quality of the links.

The ATLAS Semiconductor Tracker has adopted a binary scheme for the readout of silicon strip detectors as the baseline. The binary architecture allows a more compact design and has the advantage of a much reduced data transfer rate with more chips using a single optical link. This architecture is, however, not immune at all to the common mode noise and so it is very sensitive to the external electromagnetic interference.

In this paper the ATLAS back-up solution, the SCT128A chip will be presented. The SCT128A chip is an example of the analogue readout architecture for silicon strip detectors, which meets all basic requirements of the LHC experiments. It comprises five basic blocks: front-end amplifiers, analogue pipeline (ADB), control logic including derandomizing FIFO, command decoder and output multiplexer. The chip has been manufactured in the DMILL process, the same as used for the binary chip ABCD. The front-end is a fast transimpedance amplifier, using a bipolar input transistor and providing pulse shaping with peaking time of 25 ns.

The design and the performance of the chip will be presented. The basic chip performance have been evaluated in the test bench.  Analogue prototype module consisting of two 6.4 cm x 6.3 cm ATLAS baseline detectors read out by 6 SCT128A chips has been built. The chips are mounted on a ceramic hybrid connected to the sensors in the end-tap configuration. The pitch adapter needed to match the strip pitch of  80 mm and the pitch of input pads on the chip, which is 60 mm, is integrated on the hybrid. The performance of the module, which has been tested with a Ru b- source and in a 100 GeV pion beam, will be discussed.

An optical link for transmission of data from the SCT128A chip using VCSELs is under development. Performance of the prototype analogue optical link used for read out of the analogue module will be presented and discussed.

Id: 102
Corresponding Author: Danek KOTLINSKI
Experiment: CMS
Sub-system: Tracker
Topic: Electronics for Trackers

The CMS Pixel Detector

Danek Kotlinski, Paul Scherrer Institute, Switzerland

Abstract:

In the presentation the readout architecture of the CMS pixel detector will be discussed.
The data rate and volume expected at the full LHC luminosity and it's implication on the readout chip will be presented. The overall pixel readout system  and the integration with the CMS data acquisition system will be emphasized.
The first pixel detector layer will be placed at 4cm from the beam in a very high radiation environment. Some aspects of the radiation hardness and its impact on the readout design will be discussed.

Summary:

The CMS pixel detector consists of 3 barrel layers located at 4.3 cm, 7.2 cm and 11.0 cm. The barrel is 52 cm long and is supplemented by two endcap disks on each side. The detector is equipped with sensor modules which are 1.6 cm wide and 6.4 cm long. Each detector module is readout by 16 chips. The readout chips are organized in 26 double-columns, each consisting of 106 square 150*150 microns pixels.

When pixels in a double-column are hit by a charged particle the time-stamp of the event is recorded in the column time-stamp buffer. For all hit pixels the pixel address and the analog signal are transferred to the column periphery. There the data waits for the arrival of the 1st level trigger. Groups of 8 or 16 readout chips are connected to one readout link. In order to synchronize the data transmission a "token-bit" manager chip is used. This chip, through a token mechanism, controls the access of each double-column to the readout link. It formats data packets by sending a packet header and trailer and also monitors the system and signals errors. Pixel hits confirmed by the trigger are send through the readout link to the readout electronics (FEDs) 100 m away from the detector. For each hit pixel 6 analog signals are send, they include the analog amplitude, chip identification and column and row pixel addresses, with the digital information being analog coded. About 1000 links are used to readout the whole CMS pixel detector.

The clock, trigger and the reset/synchronization signals are send down to the detector from the control modules (FECs). A separate set of links is used for this purpose. These are also used to download various setup parameters (e.g. pixel thresholds) and to communicate slow control messages.

The finite space available on the readout and token-bit chips means that the size of all data buffers must be optimized for the LHC requirements. Extensive Monte Carlo simulations have been performed to select the right buffer sizes and to estimate the data losses. With out present design the total data loss at full LHC luminosity for the pixel barrel detector at 7 cm is about 4%. This includes the data lost due to buffer overflows in the readout chip, lost data packets due to too high trigger burst rates and the 2-clock column dead time. More details will be given during the presentation.

The pixel readout is integrated with the CMS DAQ through the readout unit (RU). The RU module has a detector specific part (FED) with 48 readout links connected to it. About 26 of such units are needed for the whole pixel detector. At the LHC high luminosity about 10000 pixels are hit every 25ns. The average pixel events size is about 50 Kbytes, which at 100 kHz trigger rate corresponds to a 5 Gbytes/s data flow.

The pixel hits can be used in a standalone pixel track finding and primary vertex finding algorithms. Such algorithms could be used in the CMS 2nd and 3rd level triggers.

Id: 103
Corresponding Author: Laurent BLANQUART
Experiment: ATLAS
Sub-system: Tracker
Topic: Electronics for Trackers

Front-End electronics for ATLAS Pixel detector

Abstract:

The electronics subgroup of the ATLAS pixel detector has pursued an iterative programme of design development over the last 3 years. The initial phase of this demonstrator programme was aimed at realizing ATLAS specification front-end chips using radiation-soft technologies, the designs of which could then easily be adapted for fabrication at rad-hard foundries. First realistic prototypes were designed in 2 parallel efforts (Europe and US) in 97/98, producing a rad-soft AMS prototype (FE-A/FE-C) and a rad-soft HP prototype (FE-B). Throughout 98/99, more than 60 single chip assemblies and 10 electrically functional modules were produced and have been studied extensively in lab and during 7 testbeam periods at SPS. All of the ATLAS requirement issues (except for the radiation hardness) were addressed in detail such as noise, threshold dispersion, timewalk, digital/analog crosstalk, power supply rejection...with very encouraging results. These measurements on both single chip assembly and module are presented. A unified design approach has been adopted for rad-hard front-end chips, i.e. all working on the same design to be implemented in 2 rad-hard processes. The rad-hard designs, namely FE-D for the DMILL process and FE-H for the Honeywell process, maintain the spirit of the demonstrator programme (i.e. pin compatibility, same pixel pitches...) and combine features of both FE-A/C and FE-B. FE-D has been received in Oct. 99 and FE-H will be submitted during summer 2000.

Id: 105
Corresponding Author: Markus FRENCH
Experiment: CMS
Sub-system: Tracker
Topic: Electronics for Trackers

APVMUX, An analogue multiplexing chip for the CMS Tracker
M. French, P. Murray, L. Jone (Rutherford Appleton Laboratory)
M. Raymond (Imperial College)

Abstract:

A chip for multiplexing pairs of APV25 chip outputs onto differential analogue cable has been designed. The chip includes SEU tolerant logic to detect and control the APV signal phasing and termination resistors required by the APV25 chip. The termination impedance and switching phase are programmable by I2C and bond control respectively. The design and implementation is outlined and test results presented.

Summary:

The APV25 chip designed for the CMS tracker provides a differential analogue current signal. This must be terminated to ground and in order to match the numbers of optical inks in CMS, pairs of APV25s are required to multiplex onto individual fibres. The fibres are driven by separate driver chips that require a differential voltage input.
The purpose of the APVMUX chip is to provide this function. Each multiplexer chip can take up to eight APV25 signal inputs (the maximum for any hybrid in CMS) and multiplex them in pairs onto four differential lines that communicate to a separate laser driver module where the fibres are driven.
The phasing of the multiplexing function is derived from the trigger and 40MHz clock that drive the APV25s, this ensures the multiplexer is synchronous with the APV25 output signal. The relative phase is also controlled by two bond pads that either reverse the APV order or adjust the skew by half a clock cycle, this ensures that optimal timing may be achieved on the FE modules.
The termination impedance present in the MUX chips is programmable via the I2C interface on the APV module and allows trimming to control the voltage conversion for link gain optimisation.
In order to facilitate efficient use of the APV25 wafers the size of the MUX die was constrained in one dimension. This led to the inclusion of the PLL circuit, formerly presented as a separate chip, included in the same die. This reduced the number of different chips on each FE hybrid by integrating both functions together.
The design was submitted on the April2000 wafer run and results showing pairs of APV25 chips multiplexed together and the function of the phase and polarity control will also be presented.

Id: 106
Corresponding Author: Nancy MARINELLI
Experiment: CMS
Sub-system: Tracker
Topic: Electronics for Trackers

The CMS Tracker  front-end and  control electronics in an LHC like beam test

W.Beaumont(b), M.Bozzo(f), C.Civinini(e), J.Coughlan(k), F.Drouhin(h), P.Figueiredo(d), L.Fiore(c), A.Giassi(j), K.Gill (d), J.Gutleber(d), G.Hall(g), L.Latronico(f), C.Ljuslin(d), M.Loreti(i), C.Maazouzi(l), S.Marchioro(d), N.Marinelli(g), C. Paillard(d), T.Parthipan(k), P.Siegrist(d), L.Silvestris(c,d), I.Tomalin(k), A.Tsirou(d), P.G.Verdini(j), P.Walsham(g),
B.Wittmer(a), A.Zghiche(l,d), F.Vasey (d)

(a) RWTH, I. Physikalisches Institut, Aachen, Germany,
(b) Universitaire Instelling Antwerpen, Antwerpen, Belgium
(c) INFN, Sezione di Bari, Bari,  Italy
(d) CERN, 1211 Geneva 23, Switzerland
(e) INFN, Sezione di Firenze, Firenze,  Italy
(f) INFN, Sezione di Genova, Genova,  Italy
(g) Blackett Laboratory, Imperial College, London SW7 2AZ, United Kingdom
(h) Universite de l’Haute Alsace, Mulhouse, France
(i) INFN, Sezione di Padova, Padova,  Italy
(j) INFN, Sezione di Pisa, Pisa,  Italy
(k) Rutherford Appleton Laboratory, Didcot, OXON, OX11 0QX, United Kingdom
(l) Institut de Recherches Subatomiques, IN2PS-CNRS Strasbourg, France
 

Abstract:

A complete prototype of the CMS tracker read-out and control system has been built using components that are very close to the final design. The system is based on analogue amplifier and pipeline memory chips (APV), analogue optical links transmitting at 40Mbps and a VME digitisation and data handling board (FED), supplemented by a control system which sets and monitors the components of the system. This system has been successfully operated for the first time under LHC like beam conditions,  in a 25ns structured beam provided by the SPS at CERN,  mainly aiming  to  test the synchronisation of the system and pile-up effects in a high trigger rate environment.
Preliminary results are presented in this paper

Summary:

The CMS Tracker front-end electronics has been designed to operate at the 40MHz LHC machine frequency with low noise level while ensuring adequate bunch-crossing identification.  A first test in an LHC like beam has been successfully performed in order to check the system synchronisation and the effect on the data quality due to the high trigger rate
Four silicon strip detectors of the "standard" Tracker design have been put on the beam line equipped with a total  of 16 APV6 chips. Readout data have been transmitted through analogue optical link to the DAQ interface (two FED-PMC  8 channels ADC)  and data have then been stored in a high performance  objectivity database system
The fast control information (clock and trigger) provided by the global Timing, Trigger and Command system have been distributed by digital optical fibres from the VME mezzanine Front End Controller (FEC).  Local PLL ASICs  (one per silicone module)  allowed the  recovering of the encoded clock and trigger information and the synchronization of all modules, compensating for different cable lengths.  A local ring of controller  ASICs (CCUs) have been used to handle the transitions from high speed optical link to a number of industry standard I2C buses allowing the  decoding of slow control information hence the setting, control and monitoring of  all the parameters required for the proper operation of the front-end ASICs and their ancillary electronics.

Results
The synchronization of  12 APV6  out of  16 was successfully achieved by tuning the PLLs delays.  Synchronicity can be checked by looking online at the address of  the APV pipeline memory cells where data are stored in. When the APVs are synchronous they all show the same address. Four APV6, sitting on different detectors, turned out to be out of synchronization probably because of glitches on the clock or on the trigger line. Further details will  be available after completing the on-going offline data analysis.
Detailed measurements on each analogue optical link have been performed in order to determine the correct settings for the gain on the laser drivers.
The behavior of the APV6  with  triggers close in time has been checked. The APV6 has been designed to accept two consecutive triggers separated by at least two empty 25 ns buckets, commonly labeled "1001" trigger type, ie the minimal separation in time of two consecutive acceptable triggers is 75 ns. Such sequences, which have been measured to be present in 16% of the beam triggers, were selected, using fast logic triggering algorithm, and successfully read and recorded. The readout response of the APV6 to 2 consecutive triggers 75ns apart has been obtained and measured. This is the first observation of this very satisfactory response of electronic channels under the severe LHC like timing conditions.