Id: 94
Corresponding Author: Aurore SAVOY-NAVARRO
Experiment: General Interest
Sub-system: General Interest
Topic: Packaging and Interconnections

Performance of a new MCM-D technology front­end digital readout

P. Cluzel 1 , R. Della­Negra 1 , M. Goyot 1 , M. Miguet 1 , A. Savoy­Navarro 2
1 IPNL­Universit’e Louis Bernard de Lyon/IN2P3­CNRS, France
2 LPNHE­Universit’es de Paris 6 et 7/IN2P3­CNRS, France

Abstract

A CEE ESPRIT project developed a new MCM­D packaging technology with a view to industrial, biomedical and HEP applications. The objective was to establish a cost­efficient, commercial manufacturing base in silicium­ based MCMs, with active substracts and ball­grid array interconnects. Among the main features are the integration of active and passive components in the substrate and the use of a flip­chip technique and wafer rerouting. The demonstrator built with this new technology is a prototype of a fast digital readout front­end electronics, mixing analogue and digital components. The tests show very high functioning performances.

Summary:

A CEE ESPRIT project developed a new MCM-D technology with a view to industrial, biomedical, and H.E.P. applications. The objective of the overall project was to establish a cost­efficient, commercial manufacturing base in silicium­based MCMs, with active substrates and ball grid array interconnects. The new feature of this technology is the integration of passive and active components in the substrate, which would otherwise be connected to an MCM via wire­bonding. The first level of connection of the standard ICs to the substrate is done using a flip­chip interconnect. The development of a commercial source for wafer rerouting to facilitate flip­chip interconnects also constitutes a major goal.

This MCM-D technology presents several advantages due to the use of an active substrate, the flip­chip technique with wafer rerouting and the BGA as interconnects. The active substrate offers as benefits that there is no need to have chips for single active functions, less discrete components for biasing, loading, decoupling and filtering. Moreover it improves the testability thanks to the integrated test structures. All this reduces the lower layers of the substrate are those of the CMOS process and include the active CMOS cells. The upper layers are those of a complementary process and include up to four aluminium interconnect levels and thin­film passive elements such as tantalum­silicon resistors and silicon nitride capacitors.

The use of a flip­chip technique and wafer rerouting gives a size reduction with the reduction of the length of the interconnects and also a reduction of the power consumption. For the interconnects the use of BGA provides self-aligning properties thus leading to a better production yield, it also makes this technology compatible with standard SMD assembly processes and it permits a large number of I/O's.

A demonstrator was built in order to test most of the properties and potentiality of the developed technology. This MCM­based circuit contains the basic components of a fast digital readout front­end electronics for HEP detectors. The two basic components of this fast digital readout are a low noise preamplifier followed by a 12 bit fast analog­to­digital converter, mixing analogue and digital components. It also includes a PLL and boundary scan cells for the testability of some integrated digital functions associated with the ADC, integrated and SMD passive components.

A VME and LABVIEW based test bench allowed to test the performances of each component separately (analogue and digital) and of the overall readout chain. The results of detailed tests on the functioning of this device, show very high performances in terms of noise, stability, imaging properties and signal processing.