DILOGIC-2 A SPARSE DATA SCAN READOUT PROCESSOR FOR THE HMPID DETECTOR OF ALICE

H. Witters, IMEC vzw, 3001 Leuven, Belgium (witters@imec.be)
J.C. Santiard, CERN, Geneva, Switzerland (jean-claude.santiard@cern.ch)
Paolo Martinengo, CERN, Geneva, Switzerland (paolo.martinengo@cern.ch)
For the ALICE collaboration
 

Abstract:

Processing of analog information are always spoiled by additional DC level and noise given by the sensors or their additional readout electronic. The Dilogic-2 ASIC circuit has been developed in a 0.7um n-well CMOS technology to process the data given by Analog to Digital Converters, in order to eliminate the empty channels, to subtract the base line (pedestal) and store locally the true analog information.

Summary:

The Dilogic-2 can handle up to 64 channels by group of 16, 32, 48 or 64 channels. At the present time, the Gassiplex0.7-3 front-end analog circuit is used by group of 48 channels that are multiplexed on the same ADC. The processing has to be done in two steps, firstly pedestals and noise of each channels have to be measured and stored on the chip, then the normal operation can start, zeros will be eliminated and the on-chip memory will be loaded by true value information. The sparse data scan section is made of a digital comparator and a subtractor; the pedestal field has been limited to 8-bits while the data have 12-bits range. These two elements are fed on one side by the analog information and on the other side by the contents of two separate memories filled respectively for each channel by the chosen level of comparison (threshold) and the pedestal value. Calling PED(i) and SIG(i) the average and r.m.s. values of a pedestal distribution, the operating threshold of the channel (i) is defined as: TH(i) = PED(i) + N*SIG(i), where N is a selectable constant, usually =3.

Thresholds and pedestals are first measured and stored in a memory, for every channel; the channel address allows finding the right values of each channel during the processing. A BIT-MAP memory (64w x 16-bits) is filled with "1" for channels above threshold or "0" for channels below the threshold, while an analog data FIFO memory (512w x 18-bits) is loaded with the amplitude information (12-bits) and the address of the selected channels (6-bits). These two operations are performed in parallel at a clock speed of 10MHz. Each event readout is turned off by an End-Event word, which contains the number of good channels (7-bits) and the corresponding event number (11-bits). A presettable almost-full flag prevent over-writing the FIFO; an internal 4-bits controller has been implemented to perform the different front-end and back-end operations, particularly one, which is used to test the functionality of the chip by an outside processor. Finally, the Dilogic-2 can be daisy-chained to allow the readout of several hundreds of channels on the same bi-directional data bus at a maximum speed of 20MHz.

Id: 82
Corresponding Author: Paulo FONTE
Experiment: Alice
Sub-system: Trigger
Topic: Particle Identification

A simplified and accurate front-end electronics chain for timing RPCs

A.Blanco(1), N.Carolino(1), P.Fonte (1,2), R. Ferreira-Marques (1,3), A.Gobbi (4)
(for the ALICE collaboration)

1-LIP, Coimbra, Portugal.
2-ISEC, Quinta da Nora, Coimbra, Portugal.
3-Departamento de Física da Universidade de Coimbra, Coimbra, Portugal.
4-GSI, Darmstadt, Germany.

Abstract :

Recent advances in electronics and construction techniques have pushed the timing resolution of Resistive Plate Chambers below 50 ps sigma with detection efficiencies close to 99% for MIPs. In this paper we describe a new front-end electronics chain for accurate time and charge measurement in these devices, having in view a possible application in ALICE's T0 counter.

The circuit is built solely from commercially available and inexpensive integrated circuits, featuring a reduced number of components. It includes a fast (2 GHz bandwidth) two-stage amplifier that feeds a fixed threshold discriminator followed by an external TDC. The amplified signal is also buffered into an external ADC for charge digitization.

The chain was tested with realistic test signals from an RPC, yielding a timing resolution around 10 ps sigma for signal charges above 100 fC and a charge resolution of 5 fC.

Summary :

The recent development of timing Resistive Plate Chambers (RPCs) opened the possibility to build large, high-resolution, TOF arrays at a low cost per channel. Previous work has shown timing accuracies below 50 ps sigma at 99% efficiency for single four-gap chambers [1] and an average timing accuracy of 88 ps sigma at and average efficiency of 97% for a 32 channel system [2].

In this paper we describe a new, streamlined, front-end electronics chain for accurate time and charge measurement in these devices. The circuit will be used in future developments aimed to extend the detector size, to include a position sensitive readout and to achieve better timing resolution and rate capability.

The circuit is made solely from commercially available and inexpensive integrated circuits, featuring a reduced number of components. It includes a fast (2.5 GHz bandwidth) two-stage amplifier that feeds a fixed threshold discriminator followed by an external TDC. The amplified signal is also buffered into an external ADC for charge digitization. A full schematic and PCB layout will be included in the final report.

The test setup included a single-gap RPC as a realistic signal source, feeding in parallel two front-end circuits. The time difference between both timing signals was measured by a TDC constituted by an ORTEC 286 TAC, followed by a shaping amplifier whose output was digitized by a LeCroy 2249B peak-sensing ADC. The amplifier gain was adjusted to give to the TDC a 3 ps bin width and a 6 ns time range. The measured time resolution of the TDC was 3.5 ps sigma. The analogue outputs of both channels were digitized by a LeCroy 2249w charge-sensitive ADC. The fast (electron) component of the signal was selected by a 40 ns gate width. The system was calibrated by injection of a set of know charges using one of the test inputs, yielding a sensitivity of 3.3 fC per ADC bin, a digitization range of 6 pC and a charge resolution of 5 fC (1.5 bins) sigma.

The timing accuracy of the system was measured by slicing the charge distribution in several regions, applying a linear slewing correction to each slice and doing a gaussian fit to the corrected time distribution of each slice. The results show that the electronic timing accuracy is close to 10 ps for fast signal charges above 100 fC and it is degraded for smaller charges.

Further tests using electronically generated signals injected into single timing channels were performed to compare the present to the previous version of the front-end circuit (used in [1]), based on a pre-amplifier made with discrete components. The results shown an evident advantage of the new design for the smaller charges.

[1] P. Fonte, R. Ferreira Marques, J. Pinhão, N. Carolino, A. Policarpo, "High Resolution RPCs for Large TOF Systems", preprint CERN-EP/99-115, to be published in Nucl. Instr. And Meth. in Phys. Res.

[2] A. Akindinov et al., "A four-gap glass-RPC time-of-flight array with 90 ps time resolution",. preprint CERN-EP/99-166, submited to the IEEE Trans. Nucl. Sci.