ELECTRONICS FOR MUON DETECTORS

Id: 2
Corresponding Author: Pierluigi ZOTTO
Experiment: CMS
Sub-system: Muon
Topic: Electronics for muon detectors

First evaluation of neutron induced Single Event Effects on the CMS barrel muon electronics

S. Agosteo(1), L. Castellani(2), A. Favalli(1), I. Lippi(2), R. Martinelli(2) and P. Zotto(3)
1) Dip. di Ingegneria Nucleare (CESNEF) del Politecnico di Milano, Italy
2) Dip. di Fisica dell'Universit and sez. INFN, Padova, Italy
3) Dip. di Fisica del Politecnico di Milano and sez. INFN di Padova, Italy

Abstract:

Neutron irradiation tests of the currently available electronics for the CMS barrel muon detector were performed using thermal neutrons and fast neutrons at E < 11MeV. The Single Events Upset on the Static RAM was measured, while upper limits are derived for devices having experienced no failure. The results are used to guess the upper limits on the mean time between failures in the whole barrel muon detector.

ID:6
Corresponding Author: Yasuo ARAI
Experiment: ATLAS
Sub-system: Muon
Topic: Electronics For Muon Detectors

Development of a 24 ch TDC LSI for the ATLAS Muon Detector

Yasuo Arai, KEK, National High Energy Accelerator Research Organization, Institute of Particle and Nuclear Studies
and
T. Emura, Tokyo University of Agriculture and Technology

Abstract:

A TDC LSI for the ATLAS precision muon tracker (MDT) has been developed. A prototype chip (AMT-1) was processed in a 0.3 um CMOS Gate-Array technology. It contains full functionality of the final TDC.

To get a high resolution around 300 ps, an asymmetric ring oscillator and a PLL circuit are used. All the I/O signals which are active during measurement has LVDS interfaces. A JTAG interface is used for boundary scan and internal register setup. All the memory and control bits has parity bits so that a SEU can be detected. Radiation tolerance for Gamma-ray and Neutron are also reported.

Summary:

A TDC LSI for the ATLAS precision muon tracker (MDT) has been developed. A prototype chip(AMT-1) was processed in a 0.3 um CMOS Gate-Array technology. It contains full functionality of the final TDC; 24 input channels, 256 words level 1 buffer, 8 words trigger FIFO and 64 words readout FIFO. It also include trigger matching circuit which selects data according to the trigger ID. The selected data are transferred through 40~80 Mbps serial line with DS-Link protocol.

To get a high resolution around 300 ps, an asymmetric ring oscillator and a Phase Locked Loop(PLL) circuit are used. These time critical parts were routed in manually. All the input and output signals which are active during measurement has LVDS interfaces. A JTAG interface is used for boundary scan and internal register setup. All the memory and control bits has parity bits so that a Single Event Upset can be detected.

The chip is packaged in a 144 pins plastic QFP with 0.5 mm pin pitch and about 107k gates are used. Gamma-ray irradiation and Neutron exposure are planned. Performance of the TDC chip and radiation tolerance will be reported.

ID: 11
Corresponding Author: Roberto CIRIO
Experiment: CMS
Sub-system: DAQ
Topic: Electronics For Muon Detectors

The CMS DT Muon DDU: a PMC based interface between frontend and data-acquisition

F.Benotto, F.Bertolino, R.Cirio, G.Dellacasa
INFN Torino

Abstract:

CMS will use gas drift tubes as active part of the barrel muon sub-detector. In total 200.000 wires will be readout by TDCs and signals will be sent to data acquisition. The entrance door to the standard CMS DAS will be a board (Detector Dependent Unit - DDU) that will be specific to each sub-detector. We have built a PMC based prototype of the DT muon DDU that features two input channels with Optolink, data check and reconstruction with FPGA and PCI slave output through a FIFO. A description of the board and the FPGA schematics will be given and results from lab tests will be shown.

Summary:

We are developing a PCI Mezzanine Card based digital board that will be used as interface between the frontend electronics of the CMS barrel muon drift chambers and the standard CMS data acquisition system. The drift chambers that instrument the barrel muon detector of CMS will provide 200.000 TDC outputs. The whole frontend electronics will be housed in miniracks located inside the chambers mechanical structure. Each of the 60 sectors (12 phi * 5 weels) in which CMS is segmented will provide an output towards the standard CMS data acquisition. The board we are developing, named Detector Dependent Unit (DDU), will receive data from the sectors, work on them and send them to the standard CMS DAQ.  At the nominal LHC luminosity, the average occupancy of the barrel Drift Tubes will be 1 track/cm^2/s. This figure reflects in 1 muon/sector/event, that adds up to 144 bytes/sector. The total rate for the whole detector will then be 8 MBytes/s. The PMC that we are developing has two inputs, both with an optical transceiver, a serial link, a FIFO. After the two input FIFOs, data are flowing through a Xilinx, that formats them, detects errors and takes appropriate actions. The output of the Xilinx is  sent to a 32 bit output FIFO. The board is a PCI slave, through a PLX 9080 bridge, that can be read with DMA from the CMS DAQ. In case of  errors, the PMC can generate interrupts. The overall schematics of the board will be presented, together with the VxWorks based test setup and test results.

ID: 14
Corresponding Author: T.Y. LING
Experiment: CMS
Sub-system: Muon
Topic: Electronics For Muon Detectors

Radiation Test of CMS Endcap Muon Front-end Electronics with 63 MeV Protons

T.Y. Ling

Abstract:

After brief overview of the CMS EMU electronics system, results on Single Event Effects, TID and Displacement Effects due to neutron and ionizing radiation will be reported. These results are obtained by irradiating the front-end electronics boards with 63 MeV protons. During the irradiation, the electronics board was fully under power, all ASICs and COTS on the board were active and the data was readout in the same way as designed for CMS.

Id: 27
Corresponding Author: Antonio RANIERI
Experiment: CMS
Sub-system: Muon
Topic: Electronics For Muon Detectors

Single Event Upset measurements on the Resistive Plate Chambers Front-End chip for the Compact Muon Solenoid experiment

S. Altieri(1), G. Bruno(1), F. Loddo(2), A. Ranieri(2), P. Vitulo(1)
(1)Dipartimento di Fisica Nucleare e Teorica dell'Università di Pavia e I.N.F.N. Sezione di Pavia
(2)Dipartimento Interateneo dell'Università di Bari e I.N.F.N. Sezione di Bari

Abstract:

A measurement of irradiation damaging has been made on the analog front-end electronics of the RPC detector in the CMS experiment. The measurements were performed according to the estimated neutron fluence foreseen in the most irradiated area of the apparatus. The test results are shown, considering all the possible irradiation effects on the custom RPC front-end electronics, encouraging us on the use of the 0.8m Bi-CMOS technologies from AMS, chosen for such type of application.

Summary:

We report on the results of an irradiation test made at the Pavia 250 kW reactor in which some CMS RPCs 8 channels FE chips have been exposed to neutrons.

The Single Event Upset (SEU) rate has beeen measured as a function of the neutron fluence up to some units in 10e11 cm-2.

The Macroscopic Cross Section for SEU events induced by neutrons into the chips has been measured and results will be shown.

The neutron energy spectrum ranged from 0.4 eV to 10 MeV. The SEU rate has been measured to be 0.02 Hz/chip and the relative Macroscopic Cross Section to be around 1.1 x 10-5 cm-1.

No evidence of a sensible deviation from these numbers has been observed while integrating a neutron flux equivalent to what is expected in 10 years of running in almost all of the CMS muon regions.

Moreover other measurements made using more energetic neutron irradiation are also shown, together with the effects obtained on the off-the-shelf electronics mounted on the front-end board to control the analog RPC chip.

Id: 31
Corresponding Author: Richard BREEDON
Experiment: CMS
Sub-system: Muon
Topic: Electronics For Muon Detectors

PERFORMANCE AND RADIATION TESTING OF A LOW NOISE SWITCHED CAPACITOR ARRAY FOR THE CMS ENDCAP MUON CHAMBERS

R.E. Breedon, B. Holbrook, Winston Ko, D. Mobley, P. Murray, S.M. Tripathi
University of California, Davis, CA 95616 USA

Abstract:

The 16-channel, 96-cell per channel switched capacitor array (SCA) ASIC developed for the cathode readout of the cathode strip chambers (CSC) in the CMS endcap muon system is ready for production. For the final full-sized prototype, the Address Decoder was re-designed and LVDS Receivers were incorporated into the chip package. Under precision testing, the chip exhibits excellent linearity within the 1V design range and very low cell-to-cell pedestal variation. Performance of the SCA during beam tests of a fully-instrumented chamber and results from radiation testing at a 63.3 MeV proton cyclotron will be presented.

Summary:

During the first-level trigger latency period of approximately 128 bunch crossings (3.2 us), signals from the front-end electronics of sub-detectors in CMS must be held in temporary storage before being passed to the DAQ system or rejected. The endcap muon system employs a switched capacitor array to allow full-wave sampling and storage of the precise cathode measurement before digitisation. This enables a higher level of control over pileup effects (baseline shift) than other pipeline options. The SCA supports random addressing and simultaneous reading and writing for deadtimeless operation.

A pulse on a strip of a CSC emerges from the preamp/shaper (Tpeak = 100 ns) and is split into two signals: one for the level-1 trigger, the other sampled by the SCA at 20 MHz. Eight samples of each pulse are saved in the SCA, the first 2-3 of which are taken before the pulse rise to establish the baseline. Sixteen cathode strip channels from each of the six layers in a muon station are connected to a front-end board (CFEB). Sixteen channels from one layer are handled by one SCA. Each channel has 96 capacitor cells; cells selected for readout are multiplexed within the SCA. As the SCA will be used also for the innermost ME1/1 chamber, a total of 16,632 CSCs will be required.

The final prototype SCA was fabricated in the AMI 0.8 um CWL process via submission to MOSIS. A custom test board provides the interface to a Tektronix Data Analysis System (DAS) 9200, which selects test voltages and provides SCA addresses. The design is optimised for a 1V input range, although pulses up to 3V may be handled with reduced accuracy. Operating at full speed, the RMS deviation from linearity over 0-1V is about 0.6%. There is remarkably low noise affecting the cell-to-cell pedestal variation: With a fixed input voltage, the RMS variation of output voltages over all capacitor cells is 0.05-0.06%.

For the final production design, we have incorporated LVDS receivers into the ASIC to conserve space on the CFEB and reduce noise. Thirty samples of the previous iteration were used to populate five CFEBs to instrument a full-sized CSC prototype for beam tests at CERN in September 1999. The SCA performed excellently and results from the cathode analysis will be presented.

We monitored samples of the production design while they were exposed to a 63.3 MeV proton beam. We will present threshold shift curves for both powered and unpowered irradiated chips. The performance of chips bench-tested after exposures of up to 100 krad was within tolerances of an unexposed part.

Id: 38
Corresponding Author: Angelo RIVETTI
Experiment: LHCB
Sub-system: Muon
Topic: Electronics For Muon Detectors

A FAST BINARY FRONT-END IMPLEMENTED IN A 0.25 UM CMOS TECHNOLOGY USING A NOVEL CURRENT-MODE TECHNIQUE

D. Moraes(1), F. Anghinolfi(1), P. Deval(2), P. Jarron(1), A. Rivetti(1).
(1)CERN, CH-1211 Geneva 23, Switzerland.
(2)MEAD Microlectronics S.A., Venoge 7, 1025 St. Sulpice, Switzerland.

Abstract:

A prototype of an IC has been developed with a very fast and low noise preamplifier, using a 0.25micron CMOS technology. The prototype contains a low- and high gain version of the preamplifier. It was designed to have an input impedance below 10 Ohms and an peaking time of 10ns at an input capacitance of 20pF. The low gain version was specially developed to be used on the Cathode Pad Chambers of the LHCb Muon System, where a very low threshold combined with high speed and low noise are required in order to obtain high efficiency and good time resolution.

Summary:

The investigation of the characteristics of state-of-the-art deep submicron CMOS technologies show that analogue circuits with very good performance can be designed using these processes. In particular, deep submicron technologies are well suited for the design of binary front-end systems. In these applications, in fact, the limitation on the dynamic range imposed by the squeezed power supplies (typically 2.5 V for a 0.25 um CMOS) is not a primary issue.

Current-mode architectures can be a viable alternative to the more conventional voltage-mode ones to build very fast circuits Therefore, combining current-mode techniques with the use of deep submicron technologies provides the opportunity of building analog circuits with very good speed/power consumption trade-off.

In high energy physics applications the radiation tolerance of the circuits is often a critical point. The thin gate oxide inherent in deep submicron CMOS technologies, combined with the systematic use of enclosed layout transistors and guard-rings, has shown to provide very good resistance to total dose radiation damage. However, the use of enclosed geometries imposes constraints on the aspect ratio of MOS transistors. This is of particular concern in the design of current mirrors, which are fundamental building blocks in current mode circuits.

To investigate the above issues we have designed two current mode binary circuits. The circuits use the same topology, but the input stage has been optimised to match two different input capacitance (10pF and 20pF respectively), having in mind two different applications:

1) The front-end of medium capacitance silicon detectors (for the 10pF version)

2) The front-end of the Cathode Pad Chamber of the LHCb muon system (for the 20 pF version).

Each processing channel is formed by a current mode preamplifier and a two-stage discriminator. The first step of the discrimination is carried out in the current domain, whilst the second stage is a conventional voltage mode differential pair. In fact, to interface the chip with the outside circuitry is more practical to have the signals in the voltage domain. LVDS signals are hence provided at the output of each channel., The input impedance is very low (less than 10 Ohms) , owing to the novel current mode feedbackintroduced in the preamplifier.

The gain of the preamplifier is different for the two versions. A current gain of 6 has been chosen for the low gain version ( 20pF input capacitance). For the high gain version (input capacitance 10 pF) a gain of 64 has been selected.

The noise has been calculated to be 600 electrons rms for the high gain version (14 ns peaking time) and 1100 electrons for the low gain version (10 ns peaking time)

The power consumption is 3.5 mW and 10 mW for the high and low gain version, respectively.

A prototype of 2x2 mm^2 containing four channels of each type has just been submitted for fabrication. Extensive tests results are expected to be presented at the conference.

Id: 51
Corresponding Author: Jorgen CHRISTIANSEN
Experiment: General Interest
Sub-system: Muon
Topic: Electronics For Muon Detectors

A data driven high-resolution Time-to-Digital Converter

J. Christiansen, A. Marchioro, P. Moreira, M. Mota, V. Ryjov CERN, CH-1211 Geneva, 23 Switzerland
S. Débieux Engineering School of Geneva, Microelectronics Lab, Geneva, Switzerland

Abstract:

A data driven multi-channel Time-to-Digital Converter (TDC) circuit with programmable resolution (25ps - 800ps binning) has been implemented in a 0.24um CMOS technology. An on-chip PLL is used for clock multiplication up to 320MHz from an external 40MHz reference. A 32 element Delay Locked Loop (DLL) performs time interpolation down to 97.5ps. Finally, finer time interpolation is obtained using an on-chip RC delay line. Time measurements are processed and buffered in a data driven architecture based on time tags. This results in a highly flexible triggered or non-triggered TDC which can be used in many different experiments.

Summary:

A highly flexible high resolution, multi-channel TDC has been built in a modern 0.24um CMOS technology. Its high flexibility enables it to be used in several LHC experiments: ALICE TOF detector, CMS muon drift chamber detector and LHCb outer tracker. The complete design containing more than 1 million transistors has been submitted for fabrication and will be fully characterized before LEB 2000.

The time digitization is based on a clock synchronous counter and a DLL with 32 delay elements both driven from an on-chip PLL.

An on-chip adjustable RC delay line spanning the "length" of a DLL delay cell is optionally used to further increase the time resolution. The RC delay line is divided into four segments each used to latch a time measurement. From these four measurements an interpolation with a resolution of 25ps can be obtained.

In low resolution modes ( 800ps - 100ps time binnig) 32 channels are available per TDC. In the high resolution mode four low resolution channels are controlled by the RC interpolator resulting in 8 channels.

The PLL and the DLL are self-calibrating being locked to the external reference clock. The RC delay line used in the high-resolution mode is to a high degree insensitive to the operating conditions (within +-20 deg.C) and only needs to be calibrated for process variations.

Individual channel buffers enable multiple time measurements to be performed with low dead time. The digitization of individual leading and/or trailing edges enables time over threshold measurements of signal amplitudes to be performed. Time measurements are written into four 256-deep latency buffers waiting to be serviced by a trigger-matching unit. The extraction of hits related to triggers are based on trigger time tags from an internal 16-deep trigger FIFO. Unique features of the data driven time tag based trigger matching is the fact that the trigger latency is not directly limited by the size of the latency buffers and that single hits can be matched to multiple triggers. Extracted measurements are written into a 256-deep readout FIFO waiting to be read out. Trigger matching can also be completely disabled whereby the latency buffers and the readout buffer works as simple FIFO's. Accepted time measurements can be read out via a 40MHz, 32 bit parallel bus for high rate applications or alternatively via a serial link.

Extensive error checking and monitoring is included in the TDC. Parity checks are applied throughout the data path to detect any malfunction caused by single event upsets. A JTAG interface is used to load programming parameters (~600bits) and access built-in test and verification features.

Id: 74
Corresponding Author: Franco Gonella
Experiment: CMS
Sub-system: Muon
Topic: Electronics for muon detectors

The "MAD", a Full Custom ASIC for the CMS Barrel Muon Chambers Front End Boards

Franco Gonella and Matteo Pegoraro from INFN - Sez. Padova (Italy)

Abstract:

Front end electronics of CMS barrel muon chambers is built around a full custom ASIC, named MAD, designed and developed by INFN Padova, that provides amplification, discrimination and cable driving circuitry for a quadruplet of drift tubes.
The system is organized in compact boards located in the gas volume and includes I2C slow control features for channels enable/disable and temperature monitoring, and a flexible test pulse system for calibration purposes.
Attained results confirm the good performances of the system; particularly, big effort was put in radiation tests (neutron, gamma rays and ions) to check behavior and reliability in LHC environment.

Summary:

Front end electronics of CMS barrel muon chambers is organized in compact boards (Front End Board, located in the detector gas volume) whose fundamental component is a full custom ASIC (named MAD) that provides the primary processing of drift tubes signals. To accomplish the variable size of the chambers two version of FEBs are produced differing in the number of electronic channels: 16 or 20.
The ASIC, 2.5x2.5 mm2 die area, is made using 0.8 µm BiCMOS technology by Austria Mikro Systeme and housed in a TQFP44 package; the chip was designed and developed by INFN Padova.
The task of this IC is to amplify signals picked up by chamber wires, compare them against an external threshold and transmit the results to the acquisition electronics.
The working conditions of the detector set requirements for high sensitivity and speed combined with low noise and little power consumption. Moreover, as the basic requirement for the front end is the ability to work at very low threshold to improve efficiency and time resolution, a good uniformity is also needed for sensitivity and threshold between channels of different chips.
The ASIC implements 4 complete analog chains, each made of a charge preamplifier and a simple shaper with baseline restorer, whose output is compared with an external threshold by a latched discriminator; the output pulses are then stretched by a programmable one shot and sent to an output stage able to drive long twisted pair cables with LVDS compatible levels.
A temperature sensor with sensitivity of 7.5 mV/°K and masking features for disabling noisy channels at shaper stage and check trigger functionality are also included.
Gain value is 3.3 mV/fC in average, constant up to 500 fC input with less than 1% integral nonlinearity; saturation occurs at about 800 fC. Threshold uniformity is very good, the r.m.s. is below 0.6 mV; propagation delay is about 4 ns.
Key characteristics for low threshold operation are noise and crosstalk: bare chips exhibit ENC of 1400 e- (slope of 60 e-/pF) and a value below 0.1% for the latter while complete board increase these two figures to 1900 e- and 0.2% mainly because of input protection network.
Also included in the FEBs are an I2C bus interface to set masks and temperature probe output and a flexible test pulse system for time and trigger calibration. The total power dissipation of the system is very low, below 25 mW/channel.
The reliability of the whole system is presently under investigation regarding ageing and radiation tolerance both critical in a hardly accessible environment as CMS detector: tests performed still now on FEB (accelerated ageing and irradiation with neutrons, ions and gamma rays) show good MTBF characteristics and immunity to latch-up events.

Id: 80
Corresponding Author: Paul O'CONNOR
Experiment: ATLAS
Sub-system: Muon
Topic: Electronics for muon detectors

Performance and Radiation Tolerance of the ATLAS CSC On-Chamber Electronics

A. Gordeev, V. Gratchev, A. Kandasamy, P. O'Connor, V. Polychronakos, V. Tcherniatine, K. Vetter
Brookhaven National Laboratory

J. Dailing, N. Drego, D. Hawkins, A. Lankford, Y. Li, S. Pier, M. Schernau, D.Stoker, B. Toledano
University of California, Irvine

Abstract:

The on-detector electronics for the ATLAS Cathode Strip Chamber (CSC) performs amplification, analog buffering, and digitization of the charge signals from individual cathode strips. Working in a high-rate environment (strip hit rate up to several hundred kHz) the system requires a signal-to-noise ratio of 200:1 and a dynamic range of 10 bits. Radiation conditions are: ionizing dose of 4.4 krad/yr and neutron flux of 7x10^12 n/cm^2/yr.
The system consists of 320 chamber-mounted ASM boards serving a total of over 61,000 channels. Performance and radiation tolerance of ASM prototypes will be discussed.

Summary:

The ATLAS Cathode Strip Chambers (CSCs) find the muon position by interpolation of the charge collected in 3 - 5- adjacent strips. The performance requirements are:

- position resolution in the r-theta plane: ~ 50 microns (implies a signal:noise > 200:1);
- position resolution in the r-phi plane: ~ 1.4 mm;
- dynamic range of 10 bits;
- overall rate per chamber: ~ 10^7 Hz;
- analog buffering during the L1 trigger latency;
- deadtimeless readout;
- radiation tolerance to 4.4 krad/yr and 7 x 10^12 n/cm^2/yr.

The on-chamber electronics is organized into 192-channel Amplifier-Storage Module (ASM) boards which have charge-sensitive preamplifier/shapers, switched capacitor array analog memories, analog-digital converters, data serializer/deserializers, current and temperature monitors, calibration, and fiber optic links. The ASMs occupy a volume of about 2300 cm^3, dissipate 30W of power, and generate 1.3 Gb/s of data at the expected maximum trigger rate.

The full system consists of 64 chambers having over 61,000 channels. Beam test results indicate that the required performance can be achieved, even in the presence of high background rates. Results of recent radiation tests will also be discussed.

Id: 81
Corresponding Author: Paul O'CONNOR
Experiment: ATLAS
Sub-system: Muon
Topic: Electronics for muon detectors

Off-Detector Electronics for a High-Rate CSC Detector

A. Gordeev, V. Gratchev, A. Kandasamy, P. O'Connor, V. Polychronakos, V. Tcherniatine, K. Vetter
Brookhaven National Laboratory

J. Dailing, N. Drego, D. Hawkins, A. Lankford, Y. Li, S. Pier, M. Schernau, D. Stoker, B. Toledano
University of California, Irvine

Abstract:

The off-detector electronics system for a high-rate muon Cathode Strip Chamber (CSC) is described. The CSC's are planned for use in the forward region of the ATLAS muon spectrometer. The electronics system provides control logic for switched-capacitor array analog memories on the chambers and accepts a total of nearly 37 Gbyte/s of raw data from 64 chambers. The architecture of the system is described as are some important signal processing algorithms and hardware implementation details.

Summary:

The described electronics system supports high-rate muon Cathode Strip Chambers (CSC's) planned for use in the forward region of the ATLAS muon spectrometer. Because the chambers are situated in a severe radiation environment, much of the control and data reduction electronics is located off-detector. All 960 channels of each chamber are read out on every level one trigger. With four 12-bit time samples per channel per trigger and a trigger rate of 75 kHz, the 64 chambers of the CSC system output a total of 27.6 Gbyte/s. A planned ATLAS trigger rate upgrade to 100 kHz pushes the data rate to 36.9 Gbyte/s.
The off-detector electronics performs several operations to reduce the CSC data rate. These operations are carried out in two custom-designed VME modules, the Sparsifier and the Readout Driver (ROD). The full system contains a total of 32 Sparsifiers and 8 ROD's.
The Sparsifier performs simple zero suppression and as well as rejection of pulses that are not aligned in time with the arrival of the level one trigger. The Sparsifier is also capable of applying corrections to the data, such as scaling and pedestal subtraction. The Sparsifier transmits reduced data to the ROD via moderate-rate serial connections. The ROD's principal function is to build a single ATLAS-standard event fragment containing data from all eight chambers it services. The ROD also provides extensive data monitoring and is capable of reducing the data rate, for example, by rejecting neutron hits.
Digital signal processors perform most of the data storage, transfer, and processing functions on both the Sparsifier and the ROD. A single DSP module design, containing a DSP, an FPGA, memory, and glue logic, is utilized in a variety of roles on both the ROD and the Sparsifier.