Id: 26
Corresponding Author: Jan David SCHIPPER
Experiment: LHCB
Sub-system: General Interest
Topic: Electronics For Trackers

Low Noise Amplifier

J.D. Schipper, NIKHEF R. Kluit,NIKHEF

Abstract:

As a design study for the LHC experiments a 'Low Noise Amplifier Shaper' for capacitive detectors is developed. This amplifier is designed in 0.6 um technology from AMS. The goal was to design an amplifier with a noise contribution of 250 electrons, a 12 electrons per pF contribution from the input capacitor and a relative high gain. A test chip with two versions of the amplifier, a 'radiation tolerant' (gate-around FET's) and a 'normal' version has been fabricated and is now under test. These designs and there characteristics, simulated and measured, will be compared and discussed.

Summary:

For the LHC experiments at CERN a 'Low Noise Amplifier Shaper' for the readout of Silicon Micro Strip detectors is developed. The goal for this 'Low Noise Amplifier Shaper' is to study an amplifier design with a relative high gain and an equivalent noise charge of 250 electrons, plus 12 electrons / pF detector capacity at the input. These noise requirements are based on a 150 u Silicon strip detector (12000/MIP). The design of the amplifier is based on the amplifier in the HELIX-128 chip developed for HERA-B. The principle of the circuit is a folded cascode. This scheme is used for two reasons: Speed and power supply (dynamic range). A test chip with two versions of the amplifier, a 'radiation tolerant' (gate-around FET's) and a 'normal' version has been fabricated and is now under test. The both versions are a not equal, caused by the size limitations of the 'gate around' N-FET's. In the 'normal' version of the circuit the input P-FET is connected with the source to ground. In the 'gate around' version the feedback FET must be a P-type FET. The fact that the gate for an N-FET must be a closed figure makes it impossible to realise a W/L ratio smaller then about 4. This has been implemented by redefining the DC levels of the amplifier. During the design phase the design has been simulated intensively to verify the functionality and the predicted noise figure.

Version            Simulated         Measured                  Tpeak                                  Gain Noise     Gain   Noise
Gate around     57 mV        1741 el.                         56 mV                                                    3235el.                22 nsec
Normal            29 mV        1956 el.                         38 mV                                                        2305el.                25 nsec

In the table above some preliminary results are given. The Gain and bandwidth are as expected, but the noise is higher as expected.

Id: 34
Corresponding Author: Daniel BAUMEISTER
Experiment: LHCB
Sub-system: Tracker
Topic: Electronics For Trackers

Design and test of a readout chip for LHCb

Niels van Bakel, Jo van den Brand, Hans Verkooijen (Free University of Amsterdam / NIKHEF Amsterdam)

Daniel Baumeister, Werner Hofmann, Karl-Tasso Knoepfle, Sven Loechner, Michael Schmelling, Edgar Sexauer (Max-Planck-Institute for Nuclear Physics, Heidelberg)

Martin Feuerstack-Raible (University of Heidelberg)

Neville Harnew, Nigel Smale (University of Oxford)

Abstract:

For the LHCb experiment a first prototype of a 128 channel analogue pipeline chip, named Beetle, has been developed and submitted in a standard 0.25 um CMOS process.

It integrates 128 channels with charge sensitive preamplifiers and shapers, whose outputs are sampled with 40 MHz into an analogue pipeline with a maximum latency of 160 sampling intervalls. A comparator behind the shaper provides a binary signal. The 128 channels can be multiplexed on either 4, 2 or 1 outputs. The bias settings are programmable and monitorable via a standard I2C-interface. The architecture of the chip is described as well as simulation and test results are presented.

Summary:

For the LHCb experiment a first prototype of a 128 channel analogue pipeline chip, named Beetle, has been developed and submitted. This readout chip will be made in a standard 0.25 um CMOS process.

It integrates 128 channels with low-noise charge-sensitive preamplifiers and shapers. The risetime of the shaped pulse is 25 ns wih a 25% remainder of the peak voltage after 25 ns. A comparator with configurable polarity and threshold level behind the shaper provides a binary signal. Four neighbouring comparator channels are being ORed and brought off chip via LVDS ports. Either the shaper or comparator output is sampled with the LHC-bunch-crossing frequency of 40 MHz into an analogue pipeline with a programmable maximum latency of 160 sampling intervalls and an integrated derandomizing buffer of 16 stages. The pipeline cells are realized as nmos gate-capacitances. The stored charge is read out via a charge-sensitive amplifier and multiplexed with 40 MHz onto 4 or 1 ports. In binary readout multiplexing runs at 80 MHz on two ports. Current drivers bring the serialized data off chip.

The chip works with a trigger rate of 1 MHz and performs readout deadtimeless in 900 ns. For testability and calibration purposes a charge injector with adjustable pulse height has been implemented. The bias settings and various other parameters are programmable and monitorable via a standard I2C-interface. The chip contains only synthesized logic which has been placed and routed automatically. The architecture of the chip is described in detail as well as simulation and test results are presented.

Id: 38
Corresponding Author: Angelo RIVETTI
Experiment: LHCB
Sub-system: Muon
Topic: Electronics For Muon Detectors

A FAST BINARY FRONT-END IMPLEMENTED IN A 0.25 UM CMOS TECHNOLOGY USING A NOVEL CURRENT-MODE TECHNIQUE

D. Moraes(1), F. Anghinolfi(1), P. Deval(2), P. Jarron(1), A. Rivetti(1).
(1)CERN, CH-1211 Geneva 23, Switzerland.
(2)MEAD Microlectronics S.A., Venoge 7, 1025 St. Sulpice, Switzerland.

Abstract:

A prototype of an IC has been developed with a very fast and low noise preamplifier, using a 0.25micron CMOS technology. The prototype contains a low- and high gain version of the preamplifier. It was designed to have an input impedance below 10 Ohms and an peaking time of 10ns at an input capacitance of 20pF. The low gain version was specially developed to be used on the Cathode Pad Chambers of the LHCb Muon System, where a very low threshold combined with high speed and low noise are required in order to obtain high efficiency and good time resolution.

Summary:

The investigation of the characteristics of state-of-the-art deep submicron CMOS technologies show that analogue circuits with very good performance can be designed using these processes. In particular, deep submicron technologies are well suited for the design of binary front-end systems. In these applications, in fact, the limitation on the dynamic range imposed by the squeezed power supplies (typically 2.5 V for a 0.25 um CMOS) is not a primary issue.

Current-mode architectures can be a viable alternative to the more conventional voltage-mode ones to build very fast circuits Therefore, combining current-mode techniques with the use of deep submicron technologies provides the opportunity of building analog circuits with very good speed/power consumption trade-off.

In high energy physics applications the radiation tolerance of the circuits is often a critical point. The thin gate oxide inherent in deep submicron CMOS technologies, combined with the systematic use of enclosed layout transistors and guard-rings, has shown to provide very good resistance to total dose radiation damage. However, the use of enclosed geometries imposes constraints on the aspect ratio of MOS transistors. This is of particular concern in the design of current mirrors, which are fundamental building blocks in current mode circuits.

To investigate the above issues we have designed two current mode binary circuits. The circuits use the same topology, but the input stage has been optimised to match two different input capacitance (10pF and 20pF respectively), having in mind two different applications:

1) The front-end of medium capacitance silicon detectors (for the 10pF version)

2) The front-end of the Cathode Pad Chamber of the LHCb muon system (for the 20 pF version).

Each processing channel is formed by a current mode preamplifier and a two-stage discriminator. The first step of the discrimination is carried out in the current domain, whilst the second stage is a conventional voltage mode differential pair. In fact, to interface the chip with the outside circuitry is more practical to have the signals in the voltage domain. LVDS signals are hence provided at the output of each channel., The input impedance is very low (less than 10 Ohms) , owing to the novel current mode feedbackintroduced in the preamplifier.

The gain of the preamplifier is different for the two versions. A current gain of 6 has been chosen for the low gain version ( 20pF input capacitance). For the high gain version (input capacitance 10 pF) a gain of 64 has been selected.

The noise has been calculated to be 600 electrons rms for the high gain version (14 ns peaking time) and 1100 electrons for the low gain version (10 ns peaking time)

The power consumption is 3.5 mW and 10 mW for the high and low gain version, respectively.

A prototype of 2x2 mm^2 containing four channels of each type has just been submitted for fabrication. Extensive tests results are expected to be presented at the conference.

Id: 49

Corresponding Author: Angel DIEGUEZ
Experiment: LHCB
Sub-system: Calorimetry
Topic: Electronics For Calorimeters

A BiCMOS discriminator interface for the SPD

A. Diéguez, S. Bota Departament d'Electrònica, Sistemes d'Instrumentació i Comunicacions, Universitat de Barcelona, C/Martí Franquès, 1, E-08028, Barcelona. Spain

D. Gascón, L. Garrido Departament d'Estructura i Constituents de la Matèria, Universitat de Barcelona, C/Martí i Franques 1, E-08028 Barcelona. Spain.

M. Roselló Departament d'Electrònica, Enginyeria i Arquitectura La salle, Universitat Ramon Llull, Pg. Bonanova 8, E-08022, Barcelona. Spain.

Abstract:

A prototype chip for the analogue readout of the SPD in the LHCb Calorimeter is presented. The chip has been designed using the 0.8mm-BiCMOS technology of AMS and optimised for minimum size and maximum performance at the required frequency of operation in LHC experiments. It consists of a dual structure formed by two integrators, two track and hold circuits, two substractors, two comparators and a multiplexer. The die size occupied by one discriminator circuit is approximately 1720 mm x 330 mm.

Summary:

The microelectronic circuit designed is a pulse discriminator interface for the Scintillator Pad Detector (SPD) at the Electromagnetic Calorimeter (ECAL) at LHCb. It has to operate at the L0 trigger level of LHC (f=40MHz, T=25ns) to detect the signals from electrons at the SPD, discriminating the signal originated by photons (background). The signal entering the discriminator is originated at the SPD, transmitted through an optical fibre and amplified in a photomultiplier. The jitter of the input signal makes better to integrate it rather than consider its maximum value. So, the first block of the discriminator is an analogue integrator. On the other hand, because of the shape of the input signal, only its 83% is integrated in 25ns. This mandates the use of at least a dual architecture (two channels in each discriminator) in order to allow the substration in the current period of the 17% of the signal integrated in the previous one. A dual architecture avoids also to have dead time on integration. The integrated value to be substracted is stored in a track and hold. After the substraction, a comparator with tunable treshold gives a logic signal indicating an interesting event to be stored in the experiment. The last signal is finally multiplexed.

So, each channel of the discriminator comprises an integrator, a track and hold, a substractor and a comparator. The output of the discriminator is obtained through a final 2/1 differential multiplexer. In the prototype chip all blocks have been included separately and two different discriminators. Each one of these discriminators corresponds to two different integrator circuits. The circuit is fully differential in order to reduce noise effects. All the blocks in the circuit are biased between 2.5V and -2.5V, and polarisation currents are lower than 250mA in all blocks. The circuit has been implemented with the 0.8mm-BiCMOS technology of AMS in order to have the required frequency of operation. Because of the large number of channels to process (6000), the design has been optimised for minimum area. Each discriminator circuit, including the routing area and clock distribution is about 1720 mm x 330 mm.

It will be presented a detailed description of each block in the discriminator, as well as their functional behaviour and the final performance of the entire discriminator.

Id: 62
Corresponding Author: Hans VERKOOIEN
Experiment: LHCB
Sub-system: Tracker
Topic: Electronics For Trackers

Design of a comparator in a 0.25µm CMOS technology

Niels van Bakel, Jo van den Brand (Free University of Amsterdam / NIKHEF Amsterdam), Hans Verkooijen (NIKHEF Amsterdam), Daniel Baumeister, Werner Hofmann, Karl-Tasso Knoepfle, Sven Loechner, Michael Schmelling, Edgar Sexauer (Max-Planck-Institute for Nuclear Physics, Heidelberg) Martin Feuerstack-Raible (University of Heidelberg), Neville Harnew, Nigel Smale (University of Oxford)

Abstract:

A comparator for the LHC-B vertex detector front-end chip, the Beetle, has been designed in a 0.25µm CMOS technology and is sent for fabrication. To improve threshold uniformity, each comparator has a 3 bits DAC. The comparator can handle positive and negative inputsignals. A polarity signal changes the polarity of the threshold voltage and makes the outputsignal always positive when active. The outputsignal is latched by a 40MHz clock and is selectable between time-over-threshold (in 25ns bins) or active for one clockcycle. Simulation- and measurement results will be discussed.

Summary:

For fast primary vertex reconstruction and pile-up rejection binary hit information is needed from the LHC-B vertex detector front-end electronics. Therefore a comparator for the Beetle chip has been designed. The Beetle is a 128 channel analog pipeline chip for the LHC-B experiment and, like the comparator, implemented in a 0.25µm CMOS technology, using rad-tolerant layout rules. To make the comparator insensitive for low frequency inputsignals, e.g. temperature drift and different offsets, one of the inputs of the comparator has a low-pass filter to obtain the DC-voltage of the incoming signal. This voltage is summed to the threshold voltage. The threshold voltage is the combination of a controllable voltage used for all comparators and a individual voltage for each comparator controlled by a 3 bits DAC. The comparator operates in a 40MHz system. The outputsignal of the compared time-over-threshold voltage is latched at a well defined time by a 40MHz clock, which is related to the beam timing. The width of the analog inputsignals is roughly 25ns and therefore the time-over-threshold can be longer than one period. By means of a "output mode selection" the outputsignal can be time-over-threshold (in 25ns bins) or one pulse of 25ns once the inputsignal went over threshold. The comparator can deal with positive and negative inputsignals. A polarity signal switches the polarity of the threshold voltage and controlles the output stage so that the outputsignal is always a positive pulse. In addition a multiplexer to store hits as binary information has been designed. This multiplexer selects the signal to the analog pipeline between the shaper output or the comparator output and converts the digital signal from the comparator in 0 or 10 MIP signal. Specifications -The timewalk of the outputsignal is 10ns for signals between 5mV to 100mV above threshold. -The inputsignal should be between GND + 0.8V and VDD - 0.8V. -The powerconsumption is expected to be 350µW.

Id: 64
Corresponding Author: Florent VAUTRIN
Experiment: LHCB
Sub-system: Tracker
Topic: Electronics For Trackers

Comparative study of current-mode versus voltage-mode analog memory in a 0.25um CMOS technology

F.VAUTRIN, J.MICHEL, F.BRAUN

Abstract:

The aim of this work is the study of switched-current and voltage-mode memory cells in order to develop a model including non-ideal effects such as charge injections,non-linear capacitance and readout system influence. These models will allow non-linearity control regard to surface, speed and power criteria in digital dedicated submicronic technology. Such models lead to a memory cell optimization in order to include it in an analog memory for LHC experiments.

Summary:

By definition, an analog memory consists of several thousands of channels of several hundreds of depth cells. The study of these memories goes through memory cells performances identification The cells have to be faithfully reproducible, low noise, of minimum area and power. Power per cell and area per cell are critical points. A state of the art on analog memories works show that the balance between power and area can be achieved by using submicronic technologies. Moreover, such technologies can be used in radiative environment. It is important to study second generation switched-current structures as an alternative to voltage mode structures. These structures are fully compatibles with the new CMOS submicronic technologies dedicated to digital circuits. Indeed, there are not limited (first approximation) by linearity and hysteresis of storage capacitors, like in voltage-mode. The goal of this study is to identify accuracy limits that can be reached with minimum size architectures in a deep submicronic technology (0.25 um) for both types of cells: voltage mode and current mode. By comparison to a typical N bits acquisition system, accuracy error should be less than half a quantum. By studying operating phases of each cell, we have developed theoretical models that include non-linear effects such as charge injections, readout system influence for both types of cells, finite output conductance for current-mode cell, and non-linear capacitance for voltage mode cell. These models are polynomials of output signal as a function of input signal. Accuracy is divided in two parts: static and a dynamic accuracy. In fact, dynamic error is over-evaluated and final precision is only conditioned by static precision that is to say non-linearity error. In such a cell with a 40 MHz acquisition frequency, dynamic error is limited to a half quantum of 9 bits for an 8 bits final precision. This analysis highlights predominant factors that influence non-linearity error: memory capacitance value, output impedance, memory transistor size (switched-current). For both cell types, final accuracy, acquisition frequency and power dissipation are fixed constraints. Freedom degrees are full-scale, area and errors repartition. For voltage-mode cell, the full-scale is fixed by technology constraints. The model predicts an 8 bits non-linearity error for a 300fF capacitance value and a 60 um2 area. A comparison with current-mode cell shows an 8 bits non-linearity error for an 800 fF capacitance value and a 140 um2 area. The paper is focused on polynomials development and exploitation. Such models allow the optimization of a memory cell for LHC experiments. In current-mode cells, full-scale and bias current are variables. By exploiting these models, the designer is able to do compromises between accuracy, power dissipation and area in order to obtain the same accuracy than a voltage mode cell. Finally, two optimal cells are presented.

Id: 84
Corresponding Author: Ken WYLLIE
Experiment: LHCB & ALICE
Sub-system: Tracker
Topic: Electronics for Tracker

First results from the ALICE1LHCb pixel chip

K. Wyllie1), M. Burns1), M. Campbell1), E. Cantatore1), V. Cencelli2), P. Chochula1), R. Dinapoli3), S. Easo4),
F. Formenti1), T. Grassi1), E. Heijne1), P. Jarron1), K. Kloukinas1), P. Lamanna3), F. Meddi1), M. Morel1), V. O’Shea4),
V. Quiquempoix1), D. San Segundo Bello5), W. Snoeys1), L. Van Koningsveld1)

1) CERN, Geneva, Switzerland
2) INFN Rome, Italy
3) University and INFN Bari, Italy
4) University of Glasgow, Glasgow, UK
5) NIKHEF, Amsterdam, The Netherlands.

Abstract:

ALICE1LHCb is an integrated circuit to read out silicon pixel sensors used for particle tracking in the ALICE Silicon Pixel Detector or for particle identification in the LHCb RICH. It has been fabricated in a commercial 0.25 micron technology, with consideration given to radiation tolerance, testability and system integration.
Results from the first laboratory measurements are presented. These include characterisation of the front-end, with measurements of noise and threshold uniformity. The functionality of the digital circuitry is described whilst operating the chip in both ALICE and LHCb modes. The use of the serial JTAG interface is outlined, in terms of configuring the chip and testing connectivity at the system level.

Summary:

The ALICE1LHCb chip has been designed to read out silicon pixel sensors used for particle tracking in the ALICE Silicon Pixel Detector or for particle identification in the LHCb RICH.
In ALICE, chips will be bump-bonded to thin sensors mounted on staves forming a barrel geometry, and must be sensitive to minimum-ionising particles. In LHCb, single chips will be encapsulated within the vacuum envelopes of hybrid photon detectors, and must be sensitive to photoelectrons of energy ~20keV.
The architecture of the chip has been designed in such a way that it can be operated in one of two different modes to suit the application. This was presented at LEB99 [1].

The chip has been fabricated in a commercial 0.25 micron technology. Tolerance to total-dose radiation effects is enhanced by the use of an enclosed 'edgeless' transistor layout, and guard-rings are used to eliminate inter-component leakage and radiation-induced latch-up. Special circuit designs are used for memory elements to render them immune to single-event upset.

The chip has a total sensitive area of 12.8mm * 13.6mm, sub-divided into pixel cells of 50 microns * 425 microns. Each cell contains an analog front-end followed by a discriminator, two digital delay units, a FIFO memory and readout logic. First measurements are presented on the performance of the front-end, including the noise levels, channel-to-channel threshold variations and timewalk.

The digital functionality has been tested, with data obtained while operating the chip in ALICE mode with a clock frequency of 10MHz and in LHCb mode with a clock frequency of 40MHz.

The use of the JTAG serial interface is described. This is used both to read and write configuration data into the chip, and to test its connectivity by means of boundary-scanning the input/output pads.

[1] "A Pixel Readout Chip for Tracking at ALICE and Particle Identification at LHCb", 5th Workshop on Electronics for LHC Experiments, Snowmass, Colorado, USA, 20-24 September 1999.