ID: 3
Corresponding Author: Federico FACCIO
Experiment: General Interest
Sub-system: General Interest
Topic: Optoelectronics and data transfer systems

SEU tests of an 80Mbit/s optical receiver

F. Faccio, K. Gill, M. Huhtinen, A. Marchioro, P. Moreira, F. Vasey
CERN, CH-1211 Geneva 23, Switzerland

G. Berger
Cyclotron Research Center, UCL, B-1348 Louvain-la-Neuve, Belgium

Abstract:

The sensitivity to SEU is presented for a rad-hard 80Mbit/s receiver developed for the CMS Tracker digital optical link. Bit Error Rate (BER) measurements were made while irradiating with 59MeV protons and 62MeV neutrons, for different angles to the beam and for a wide range of optical power in the link. The photodiode is the most sensitive element to SEU. Direct ionisation can explain the SEU rate for protons incident at high angles of incidence and nuclear interactions explain the SEU rate for incident neutrons, as well as for protons for the low angles of incidence and higher optical power.

Summary:

The LHC experiments will use thousands of digital optical link channels for the transmission of timing, trigger and control signals. A large number of optical receivers will seat inside the detector, operating in a radiation environment. Radiation will threaten the correct operation of the optical receivers by degrading the performance of the photodiode, the receiver circuit, or by inducing errors (Single Event Upsets) in the data transmission. To study the sensitivity to radiation-induced errors of the rad-hard 80Mbit/s receiver developed for the CMS Tracker digital optical link, we have exposed the receiver to beams of 59 MeV protons and 62 MeV neutrons.

We performed BER measurements at CERN and at the irradiation facility (CRC, in Louvain-la-Neuve) to verify the reliability of our measurement system in the absence of irradiation. Then, we repeated the measurement in presence of proton and neutron beams. The measurements confirm that the most sensitive element to SEU is the PIN photodiode and not the receiver chip. This was expected on the basis of previous works and of the much greater sensitive volume for charge collection of the photodiode (80 µm in diameter and 2 µm in thickness). Errors induced by ionization in the photodiode occur only during the transmission of a '0' symbol.

By changing the angle of the photodiode to the beam, and by comparing proton and neutron irradiation results, we were able to distinguish between errors induced by direct ionization (from the protons) and by nuclear interactions in the diode (from both protons and neutrons). Protons incident at high angle, that is almost parallel to the diameter of the photodiode, have a sufficiently long trajectory in the sensitive volume to induce an error via direct ionization. Instead, when the angle is low (45o or less), the path-length of the protons in the sensitive volume is only a few microns at most, and the energy deposited via direct ionization is not sufficient to cause SEU. In this case, errors are dominated by ionization from heavy recoils originated from nuclear inelastic interaction of the incident protons in the photodiode. This is confirmed by the neutron irradiation measurements, for which the error cross-section (the number of errors divided by the particle fluence) is equivalent to the one measured for protons at low angles of incidence. Moreover, as expected for processes dominated by inelastic scattering, no angle dependency was observed for the neutron irradiation.

An increase of the optical power raises the threshold for errors and we observe, in all cases, a decrease of the error cross-section at high optical power. We can estimate that, for the optical receiver tested, an optical power of about -12dBm (corresponding to 63 µW) is necessary to achieve a BER below 10-12 in the presence of a particle flux of about 106 cm^-2 s^-1. A similar flux of hadrons above 5 MeV is expected in the silicon tracker of CMS, at a radial distance of about 40cm.

ID: 5
Corresponding Author: Bruce TAYLOR
Experiment: General Interest
Sub-system: Trigger
Topic: Trigger Electronics

LHC machine timing distribution for the experiments

B.G. Taylor, CERN for the RD12 Collaboration

Abstract:

At the LHC the 40.079 MHz bunch crossing clock and 11.246 kHz machine orbit signal must be distributed from the Prevessin Control Room (PCR) to the TTC systems of the 4 LHC experiments, to the test beam facilities in the West and North areas and to beam instrumentation around the ring.

To achieve this, a single high-power laser transmitter with optical fanout to all the destinations has been installed at the PCR. A standard TTC machine interface (TTCmi) has been developed which receives the signals and can deliver very low jitter timing signals to LHC experiment TTC distribution systems with multiple trigger partitions.

Summary:

At the LHC the 40.079 MHz bunch clock and 11.246 kHz machine orbit signal must be distributed from the Prevessin Control Room (PCR) to the TTC systems of the 4 LHC experiments and to beam instrumentation located at 24 points around the ring. Also, during LHC-structured SPS beam tests, the bunch clock and 43.375 kHz SPS orbit signal must be broadcast to the test beam facilities in the West and North areas.

To achieve this, a single high-power 1310 nm laser transmitter has been installed at the PCR. The bunch clock and the LHC and SPS orbit signals are received from the BA3 Faraday Cage by coaxial cables with galvanic isolation. A VCXO-PLL in the laser transmitter reduces the clock jitter and a synchronizer prevents metastability of the SPS orbit signal, whose frequency swings 29 Hz during acceleration. The 40.079 MHz clock has a constant frequency and before each slow extraction the SPS is rephased to it, just as it will be before each transfer to the LHC when it is used as injector.

The encoded laser transmitter signal is fanned out by a passive optical tree coupler and distributed to all the destinations by singlemode fibres. These distribution fibres are largely underground and preliminary tests over a 13 km link have shown that the diurnal variation in the phase of the received 40.079 MHz clock is very small.

A standard TTC machine interface (TTCmi) has been developed which receives the optical signals at the LHC experiments, decodes the composite signal and reduces the bunch clock jitter to less than 10 ps rms (about 6% of the rms bunch collision length). To compensate for the phase differences in the orbit signal received at different locations around the LHC ring, the TTCmi provides for the phase of the signal to be adjusted throughout the 88.924 µs period in 3564 steps of the bunch-crossing interval of about 25 ns.

The TTCmi incorporates an optical signal monitor and a biphase mark encoder for local TTCtx laser transmitters, which can broadcast the TTC signals to up to 8960 destinations per crate. It can also deliver the low-jitter clocks electrically to multiple TTCex encoder/transmitters at LHC experiments with up to 40 independent trigger partitions.

A TTCmi has been constructed for each of the LHC experiments and units have been installed at the X5 and X7 test beam facilities in the West Area and at H2, H4 and H8 in the North Area. As with the TTC systems at the experiments, the use of a single CERN-wide system for the distribution of the LHC machine timing signals is expected to result in cost savings and operational and maintenance advantages.

ID: 10
Corresponding Author: Thomas TOIFL
Experiment: General Interest
Sub-system: Trigger
Topic: R/M field tolerant electronics

Measurements of Radiation Effects on the Timing, Trigger and Control Receiver (TTCrx) ASIC

Thomas Toifl, Paulo Moreira, Alessandro Marchioro
CERN

Abstract:

The Timing, Trigger and Control Receiver Asic (TTCrx) receives and distributes the clock, the trigger decision, and other synchronisation signals. In this paper the radiation-hard version of the TTCrx, manufactured in DMILL technology, is discussed. First, the architecture of the circuit is described, where we concentrate on the changes to the existing prototype and on the measures taken to increase robustness with respect to single event upsets (SEU). In the second part we will present measurements of the circuit characteristics before and after irradiation with gammas and neutrons. In the last part we will then show measurements of the SEU behavior.

Summary:

A tree network of optical fibres will be used for the distribution of the clock, trigger and control signals to the LHC particle detector systems as defined by the RD12 collaboration. At the receiver side, a photodiode converts the optical signal into electrical impulses, which are then received by the Timing, Trigger and Control Receiver ASIC. The circuit recovers the clock and the encoded data from the incoming Biphase Mark encoded bitstream. It contains fine-deskew units to adjust the delay of the clock with a nominal delay resolution of 104 ps. The level 1 trigger and other synchronisation signals, e.g. the bunch counter reset signal, can be delayed by a programmable number of cycles. In addition, the chip decodes slow control data and makes them available to connected electronics on a parallel bus.

In the first section of the paper we will discuss the architecture and functionality of the circuit, where we concentrate on the changes to a previous prototype. We will also describe the design measures taken for increased robustness with respect to SEU effects.

In the second section of the paper we will present measurement results, divided into three parts: The first part contains general performance measures before irradiation. The second part is concerned with the measurement of total dose effects due to gamma and neutron irradiation. In the third part we will then show measurement results for the SEU sensitivity, for which the chip and the photodiode were irradiated in a proton, neutron and heavy ion beam.

ID: 15
Corresponding Author: Piotr KULINICH
Experiment: General Interest
Sub-system: DAQ
Topic: Detector Control And Real Time Systems

Silicon DAQ based on FPDP and RACEway

PHOBOS collaboration

Abstract:

DAQ for Si-detector of PHOBOS setup (RHIC) with Scalable Power for read out and Zero Suppression is described. Data from VA-HDR chips with analog multiplexor, are digitized by FADC. Digital buffers are multiplexed by DMU modules at speed 100 MBytes/sec and transmitted through FPDP and virtual extender of FPDP to fiber (FFI).

At the receiver end (in counting house) data from fiber are distributed between a number of dedicated processors (in RACEway multiprocessor frame) for Zero Suppression. After ZS data are concatenated and transmitted to Event Builder.

Summary:

Read out and Zero Suppression of Si-detector of PHOBOS experiment at RHIC is described.

Data from VA-HDR chips with analog multiplexor, are digitized by FADC. Digital buffers are multiplexed by DMU modules at speed 100MBytes/sec and transmitted through FPDP and virtual extender of FPDP to fiber (FFI).

As an interface for interconnection a Front Panel Data Port is used ( FPDP - a 160 Mbytes/s Front-Panel Data Port ). This is defacto standard in high data rate read-out and on February 11, 1999, FPDP was approved as an American National Standard Institute Standard, ANSI/VITA 17.

A number of firms supply products in that standard now, and there are few "extenders" which use Fiber Channel (ICS-7240, AAEC: FFOIB ) or HIPPI-Serial or G-link interfaces for FPDP.

FPDP is 32-bits synchronous data interface (with clock up to 40 MHz)

It's relatively simple, no backplane requires.

It could be "bussed" (up to 20-30 modules with FPDP could be connected to a 80-wires cable)

It doesn't require "software" control.

It's quite natural for FIFO read-out.

In the case of PHOBOS DAQ use of FPDP is attractive because it permits to make constructive block relatively simple and independent from fiber link. At stage of testing, FPDP cable could be connected without fiber link to RIN-T daughter-card of "Mercury" FPDP/RACEway interface).

Custom designed FFIs (Fiber FPDP link Interface) are used as an "virtual" extenders of parallel FPDP bus. HP's G-link and optical module FTR-8510 are main components of serial data transfer, and control logic is implemented in two fast ispLSI-2128. FFI module is built on VME-like board and uses only "+5V" and "Ground" lines. So it could reside either in standard VME crate or in custom crate. In the counting house we need RACEway access, so FFI is connected to RIN-T and ROU-T boards in MERCURY crate. In at the front end MDB crate FFI is connected to MDC (control unit) and DMUs.

At the receiver end (in counting house) data buffers from fiber interface (FFI) are distributed between a number of dedicated processors (in RACEway multiprocessor frame) for Zero Suppression. After ZS data are concatenated and transmitted to Event Builder.

Such approach permits to scale the power/speed of ZSS by changing the number of fibers and/or number of processors. It permits to use C language for ZS code, and to use different algorithms for different parts of detector.

ID: 17
Corresponding Author: Peter ALFKE
Experiment: General Interest
Sub-system: Trigger
Topic: Trigger Electronics

Recent Progress in Field-Programmable Logic

Peter Alfke, Director, Applications Engineering, Xilinx, Inc

Abstract:

1. Programmable logic for ultra-low power applications. CPLDs operating with a few microamps of supply current, and FPGAs retaining configuration and register content with less than 100 microamps of supply current. An autoranging 400 MHz six-digit frequency counter consumes <2 mA in idle, <40 mA at 400 MHz input frequency.

2. FPGAs with > 1 Mbit of dual-ported on-chip RAM. FIFOs up to 1024 deep, 64 bits wide ( or wider), clocked at >150 MHz with independent read and write clocks

3. LVDS and LVPECL interfaces running at 622 MHz data rate, and recent developments at GHz serial data I/O.

4. Recent and ongoing experiments with radiation-hardened FPGA.

Id: 30
Corresponding Author: Vladimir POPOV
Experiment: General Interest
Sub-system: Trigger
Topic: Trigger Electronics

Development of HERA-B high-pT level-0 trigger logic system

H.Riege, J.Schutt, R.van Staa
II Institut fur Experimentalphysik Universitat Hamburg, Germany

V.Popov
Institute for Theoretical and Experimental Physics, Moscow, Russia

Abstract:

High-pt trigger has been developed for the HERA-B fixed target experiment as complementary option to the basic trigger. It increases considerably the number of B mesons decay channels detectable by the experiment. The high-pt trigger performs fast and effective selection of particles with high transverse momenta. Trigger system includes three layers of gaseous chambers placed in the magnetic field with 19000 readout channels. Hit information is being transfered from the chambers to the trigger logic via high-speed optical link lines. Selection algorithm is performed by the dedicated logic electronics which allows to select O(107) events out of 1012combinations per second. Pretrigger logic consists of a number of sections. Selection capability of the pretrigger logic is on average 16 events from 192000 combinations each 96 ns (time interval between two consequent bunches). Various tests of hardware prototypes have been done. The commissioning of the high-pt trigger logic system is on-going.

Summary:

High-p t trigger has been proposed for the HERA-B fixed target experiment as complementary option to the basic trigger [1]. It increases considerably the number of B mesons decay channels detectable by the experiment and thus the physics program. The high-p t trigger performs fast and effective selection of charged particles with high transverse momenta.

The high-p t trigger provides preliminary selection ('pretrigger') of events and initiates Kalman filter procedure of the first level trigger. The selection procedure based on triple coincidences between signals coming from gaseous chambers. The high-p t pretrigger system organized using approximately 19000 detecting pads of different sizes distributed among three superlayers of chambers mounted in the magnet.

Challenging design of front-end electronics is done. Special low-mass twisted pairs cable has been developed to carry signals from the signal wires to the front-end cards. In order to reduce total amount of material in the fiducial volume of the detector these cables have no additional shield.

The front-end preamplifier cards are mounted on the edge of the detector fiducial area. They based upon the ASD-8 amplifier-shaper-discriminator ASIC [2].

A charged particle traversing the detector fires projective pads in three layers. Logical signals from front-end electronics is being transfered to the pretrigger logic system in serial form via high-speed optical link lines with data rate 800 Mbits/s. Dedicated logic electronics performes selection of 0(10 7 ) events out of a few 10 12 combinations per second. Several predefined coincidence combinations of fired pads are used to produce the pretrigger signal. The result is being transformed into a data stream of initial track parameters and transmitted to the appropriate first level trigger processors.

The high-p t trigger logic electronics is implemented in VME standard. The logic system has sectional structure and is composed of boards of two types - the Pretrigger Board and the Master Card. Each section consists of one Master Card and a number of pretrigger boards. Two processes are running asynchronously in every section - incoming data filtering procedure and serialization-encoding process. Output of the first process is the input for the second one. A pretrigger board fulfils filter procedure for raw input data in order to diminish the data rate to the level acceptable by the next process. Only that information which passed the test for coincidences is being passed to the next, serialization and encoding, procedure.

The master card acquires data from a group of pretrigger boards, completes pretrigger logic task, defines track parameters and sends messages to the appropriate FLT processors.

A pretrigger board accepts signals from 576 pads of six entire rows. Since the board serves entire rows of pads no readout overlapping occurs and no additional 're-mapping' modules are needed.

Selection capability of the pretrigger logic is on average 16 events from 192000 combinations each 96 ns (time interval between two consequent bunches).

The high-p t pretrigger latency is not more than 0:5 mu s.

The trigger logic has flexibility to the selection criteria - coincidence combinations can be easily reprogrammed.

In order to reduce pretrigger rate further optimization of selection algorithm is forseen in the master card. Important additional facilities for monitoring and testing are implemented in the pretrigger logic.

The high-p t trigger prototype has been developed and intensively tested in the HERA-B experiment environment. The first half of pretrigger logic system has been installed. The commissioning of the high-p t trigger system is going on. Some results obtained are presented. The perfomances of the system are discussed.

References

[1] E.Hartouni et al., DESY-PRC 95/01 (January 1995).

[2] F.M.Newcomer, IEEE Trans.Nucl.Sci, 40(1993) 630.

Id: 32
Corresponding Author: Juan AGAPITO
Experiment: General Interest
Sub-system: General Interest
Topic: R/m Field Tolerant Electronics

Instrumentation amplifiers and voltage controlled current sources for LHC cryogenic instrumentation

J. A. Agapito(3), F. M. Cardeira(2), J. Casas(1), A. P. Fernandes(2), F. J. Franco(3), P. Gomes(1), I. C. Goncalves(2), A. Hernandez Cachero(3), J. Lozano(3), M. A. Martin(3), J. G. Marques(2), A. Paz(3), A. J. G. Ramalho(2), M. A. Rodriguez Ruiz(1) and J. P. Santos(3).
1 CERN, LHC Division, Geneva, Switzerland.
2 Instituto Tecnol¢gico e Nuclear (ITN), Sacav‚m, Portugal.
3 Universidad Complutense (UCM), Electronics Dept., Madrid, Spain.

Abstract:

Two different topologies for the basic instrumentation amplifier have been studied. Both amplifier and current source circuits have been designed, constructed and tested under radiation. All radiation campaigns have been carried out in ITN (Portugal) research nuclear reactor. A new facility for neutron beam extraction has been constructed. On line measurements of the offset voltages, offset currents, closed loop gain, and bias currents have been performed on the two structures for two different operational amplifiers, OPA124 & TLE2071. A study of the influence of each individual parameters to the whole has been carried out. Three voltage controlled current sources have been made with every instrumentation amplifier. Three values of current for each set of amplifiers have been fixed, adjusted to the different ranges of measurement of the cold mass temperature sensor. On line measurements of the currents are presented as a function of neutron radiation. And finally on line measurements of commercial voltage references are presented as a function of radiation.

Summary:

The influence of neutron and gamma radiation on operational amplifiers parameters was studied and experiments in a nuclear reactor were performed and reported in LEB99. Those tests provided the necessary information to select the amplifier that exhibited a better radiation tolerance to the expected doses in LHC cryogenic system. None of the amplifiers were instrumentation operational amplifiers, to be used in the signal conditioners for the cold mass temperature measurement and control. We decided to analyze instrumentation amplifiers and current source circuits designed with single operational amplifiers using the characteristics obtained in last campaigns. Two different topologies for the basic instrumentation amplifier have been studied. Both amplifier and current source circuits have been designed, constructed and tested under radiation. All radiation campaigns have been carried out in ITN (Portugal) research nuclear reactor. A new facility for neutron beam extraction has been constructed so that the gamma radiation has been reduced and the neutron fluence maintained to a rate as to obtain the whole desired dose in 5 days, 12 hours work. On line measurements of the offset voltages, offset currents, closed loop gain, and bias currents have been performed on the two structures of instrumentation amplifiers for two different operational amplifiers, OPA124 & TLE2071. The radiation is monitored by mean of three photodiodes placed in the center and the two ends of the set of circuit boards.

A study of the influence of each individual parameters to the whole has been carried out. The open loop gain is severely affected by neutron radiation. The circuits under study exhibit a stable closed loop gain as long as the open loop gain is maintained over 100V/mV. When this is lower, the structure with 2 opamp's is less affected than the 3 opamp's circuit. There is also an increase of the common mode gain, which affects in the reduction of the CMRR. These is also more important in the 3 opamp's circuit because of its low CMRR even without radiation. On the other hand the circuit with 2 opamp's needs a restricted voltage sweep values for common mode input. The gain of the reference voltage input is 1 and no significant differences between both structures have been detected.

Both circuits are very sensitive to offset voltage deviations of their components. Input opamp's contribute most largely to the offset voltage of the whole amplifier than any other component. Thus the output offset voltage of the instrumentation amplifier is a function of the characteristics of the input amplifiers. The values of all the individual parameter are compared after radiation with those obtained before and presented in a plot.

Three voltage controlled current sources have been made with every instrumentation amplifier. Three values of current for each set of amplifiers have been fixed, adjusted to the different ranges of measurement of the cold mass temperature sensor. The influence of the deviation of the individual parameters does not affect in the same manner to these circuits as it does to the instrumentation amplifier. When the open loop gain decrease dramatically to a value of 10V/mV the current across the sensor deviates less than 0.2% of its nominal value.

On line measurements of the currents are presented as a function of neutron radiation. Finally on line measurements of commercial voltage references are presented as a function of radiation.

Id: 39
Corresponding Author: Gunnar LINDSTROEM
Experiment: General Interest
Sub-system: Tracker
Topic: R/m Field Tolerant Electronics

Developments for Rdaiation Hard Silicon Detectors by Defect Engineering - Results of the CERN RD48 (ROSE) Collaboration

Gunnar Lindstroem (cospokesman of RD48) on behalf of the RD48 collaboration

Abstract:

The success of the Oxygen enrichment of FZ silicon as a highly powerful defect engineering technique and its optimization with various commercial manufacturers are reported. Major focus is on the changes of the effective doping concentration (depletion voltage). Other aspects (reverse current, charge collection) are covered too. Diode characteristics of test pad- and LHC-strip detectors are compared. The RD48 model for the dependence of radiation effects on fluence, temperature and operational time is verified; projections to operational scenarios for main LHC experiments demonstrate vital benefits. Present microscopic understanding of damage effects including differences caused by charged and neutral hadrons are discussed too.

Summary:

The RD48(ROSE) collaboration has succeeded to develop radiation hard silicon detectors, capable to withstand the harsh hadron fluences in the tracking areas of LHC experiments. In order to reach this objective, a defect engineering approach was employed resulting in the development of Oxygen enriched FZ silicon (DOFZ). Systematic measure- ments have been carried out with various standard and oxygenated material in fluence ranges between 5e10 and 5e14 cm-2 (1MeV-n- equivalent). The defect generation on a microscopic scale was also studied, gaining invaluable insight in the underlying physics. Only macroscopic effects of the O-enrichment with direct relevance for LHC detector application are summarized in the following:

* Leakage current: the damage parameter alpha is material independent (no dependence on conduction type, crystal orientation, resistivity and impurities) and is scaling almost ideally with NIEL (non ionizing energy loss) independent of particle type and energy.

* Effective doping concentration (depletion voltage): the damage induced change in Neff is considerably improved after charged hadron irradiation. Short term annealing (10 days at RT) leads to about 3 times less increase in the depletion voltage as compared to standard silicon and the reverse annealing even shows an unexpected saturation at higher fluences. This amounts to a decrease in the Neff-change by as much as a factor of 4 and is also connected with a 5 times larger annealing time, thus offering an additional safety margin for detectors kept at room temperature during maintenance. To present knowledge these improvements hold only for proton irradiation (in accordance with existing checks for pions), for neutrons a beneficial effect was observed by using low resistivity material (e.g. 1 kOhmcm instead of the standard 5 kOhmcm silicon decreases the change in Neff after 2e14 n/cm² by a factor of about 2).

* Charge collection efficiency: while the measurements for Neff have mostly been performed on test pad diodes using C/V methods, these results have been checked both with test and silicon strip detectors measuring the charge collection efficiency as function of bias voltage. The results show a good agreement between both techniques also revealing that the systematic analysis done with test diodes can reliably be used for strip detectors.

* Model description for macroscopic damage effects and projection to LHC: For the above described effects the "Hamburg-model" had been applied for the O-enriched silicon detectors and relevant parameters were extracted. The application of the model to LHC operational scenarios indicates that by using oxygenated instead of standard silicon the lifetime of e.g. the sensors in the B-layer of the ATLAS pixel detector would be extended to almost 10 years. In fact, the ATLAS pixel group had meanwhile decided to use the RD48 developed technique.

* Optimization of the DOFZ technique: So far feasibility studies with various companies have shown that the oxygenation of the silicon bulk by prolonged tempering after normal oxidation (diffusion of O from the SiO2-Si interface) does not result in any problem. Optimization experiments are presently carried out with O-diffusion in the range between 6 days at 1200C and 8 hours at 1150C.

Id: 42
Corresponding Author: Peter SKOROBOGATOV
Experiment: General Interest
Sub-system: General Interest
Topic: R/m Field Tolerant Electronics

The nonlinear behaviour of p-i-n diode in high intense radiation fields

P.K.Skorobogatov, A.S.Artamonov, B.A.Ahabaev Specialized electronic systems

Abstract:

The dependence of p-i-n diode ionizing current amplitude vs dose rate is defined using twodimensional software simulation. It is shown that analyzed dependence becomes nonlinear beginning with relatively low dose rates near 107 rad(Si)/s. This effect is connected with the modulation of p-i-n diode intrinsic region by irradiation. As a result the distribution of electric field becomes non-uniform that leads to decrease of excess carriers collection. The ionizing current pulse form becomes more prolonged because of delayed component contribution. It is necessary to take into account when p-i-n diode is used as dose rate dosimeter.

The p-i-n diodes are widely used for the measurements of ionizing radiation dose rates. The high electric field in its intrinsic region provides the full and fast excess carriers collection. As a results the ionizing current pulse waveform repeats the ionization pulse with the accuracy of several nanoseconds. To investigate the p-i-n diode possibilities at high dose rates the original software simulator "DIO-DE-2D" [1] was used. The "DIODE-2D" is the fundamental system of equations two-dimensional solver. It takes into account carrier generation, recombination and transport, optical effects, carrier's lifetime and mobility dependencies on excess carriers and doping impurity concentrations. The typical p-i-n diode with 380 micrometers intrinsic region width under 300 V reverse bias was investigated. The simulation of p-i-n diode structure have shown that linear dependence between dose rate and ionizing current is valid only at relatively low dose rates up to 107 rad(Si)/s. In the field of high dose rates this dependence becomes non-linear and ionizing current increases more slowly than dose rate. The reason of non-linearity is connected with the modulation of p-i-n diode intrinsic region by excess carriers. Because of low level of initial carriers concentration the modulation takes place at relatively low dose rates. As a result of modulation the distribution of electric field in the intrinsic region becomes non-uniform that leads to decrease of excess carriers collection. The behavior of p-i-n diode becomes similar to that of ordinary p-n junction with prompt and delayed components of ionizing current. The prompt component repeats the dose rate waveform. The delayed component is connected with the excess carriers collection from regions with low electric fields. As a result the ionizing current pulse form becomes more prolonged and dose not repeat the dose rate waveform. The numerical results were confirmed by experimental measurement of p-i-n diode ionizing reaction in wide range of ionizing radiation dose rates. The non-linear character of behavior and prolonged reaction must be taken into account when p-i-n diode is used as dose rate dosimeter.

References [1]. The "DIODE-2D" Software Simulator Manual Guide, SPELS, 1995.

Id: 43
Corresponding Author: Peter SKOROBOGATOV
Experiment: General Interest
Sub-system: General Interest
Topic: R/m Field Tolerant Electronics

Use of external resistor to prevent radiation induced latch-up in commercial CMOS IC's

P.K.Skorobogatov, A.Y.Nikiforov, A.A.Demidov Specialized electronic systems

Abstract:

It is shown that in the case of external resistor usage to prevent radiation induced latch-up in commercial CMOS IC's we have the increase of IC recovery time up to tens of microsecond due to deep saturation of parasitic bipolar transistors. Under numerical calculations it was found that there is an optimal value of external resistor that provides the minimal recovery time of IC.

The usage of commercial CMOS IC's in radiation environment is restricted by the possibility of its latch-up behaviour under irradiation. The external resistor in power supply circuit is a well-known way to prevent latch-up. This method is found on the restriction of IC power supply current to the level lower than latch-up holding current. The experiments were shown however that in this case we unfortunately have the increase of IC recovery time up to tens of microsecond. Under numerical calculations it was found that this effect is connected with deep saturation of parasitic bipolar transistors on the external resistance. It was found that there is an optimal value of external resistor that provides the minimal recovery time of IC. In the case of low resistance the large recovery time is connected with deep level of parasitic transistors saturation. In the case of high resistance value the recovery time is defined by well-substrate p-n junction ionizing current delayed component voltage drop on the external resistance that increases with resistance growth. For CMOS IC's under investigation the optimal value was near 80 Ohm. This effect must be taken into account when commercial CMOS IC's are used in radiation environment.

Id: 51
Corresponding Author: Jorgen CHRISTIANSEN
Experiment: General Interest
Sub-system: Muon
Topic: Electronics For Muon Detectors

A data driven high-resolution Time-to-Digital Converter

J. Christiansen, A. Marchioro, P. Moreira, M. Mota, V. Ryjov CERN, CH-1211 Geneva, 23 Switzerland
S. Débieux Engineering School of Geneva, Microelectronics Lab, Geneva, Switzerland

Abstract:

A data driven multi-channel Time-to-Digital Converter (TDC) circuit with programmable resolution (25ps - 800ps binning) has been implemented in a 0.24um CMOS technology. An on-chip PLL is used for clock multiplication up to 320MHz from an external 40MHz reference. A 32 element Delay Locked Loop (DLL) performs time interpolation down to 97.5ps. Finally, finer time interpolation is obtained using an on-chip RC delay line. Time measurements are processed and buffered in a data driven architecture based on time tags. This results in a highly flexible triggered or non-triggered TDC which can be used in many different experiments.

Summary:

A highly flexible high resolution, multi-channel TDC has been built in a modern 0.24um CMOS technology. Its high flexibility enables it to be used in several LHC experiments: ALICE TOF detector, CMS muon drift chamber detector and LHCb outer tracker. The complete design containing more than 1 million transistors has been submitted for fabrication and will be fully characterized before LEB 2000.

The time digitization is based on a clock synchronous counter and a DLL with 32 delay elements both driven from an on-chip PLL.

An on-chip adjustable RC delay line spanning the "length" of a DLL delay cell is optionally used to further increase the time resolution. The RC delay line is divided into four segments each used to latch a time measurement. From these four measurements an interpolation with a resolution of 25ps can be obtained.

In low resolution modes ( 800ps - 100ps time binnig) 32 channels are available per TDC. In the high resolution mode four low resolution channels are controlled by the RC interpolator resulting in 8 channels.

The PLL and the DLL are self-calibrating being locked to the external reference clock. The RC delay line used in the high-resolution mode is to a high degree insensitive to the operating conditions (within +-20 deg.C) and only needs to be calibrated for process variations.

Individual channel buffers enable multiple time measurements to be performed with low dead time. The digitization of individual leading and/or trailing edges enables time over threshold measurements of signal amplitudes to be performed. Time measurements are written into four 256-deep latency buffers waiting to be serviced by a trigger-matching unit. The extraction of hits related to triggers are based on trigger time tags from an internal 16-deep trigger FIFO. Unique features of the data driven time tag based trigger matching is the fact that the trigger latency is not directly limited by the size of the latency buffers and that single hits can be matched to multiple triggers. Extracted measurements are written into a 256-deep readout FIFO waiting to be read out. Trigger matching can also be completely disabled whereby the latency buffers and the readout buffer works as simple FIFO's. Accepted time measurements can be read out via a 40MHz, 32 bit parallel bus for high rate applications or alternatively via a serial link.

Extensive error checking and monitoring is included in the TDC. Parity checks are applied throughout the data path to detect any malfunction caused by single event upsets. A JTAG interface is used to load programming parameters (~600bits) and access built-in test and verification features.

Id: 55
Corresponding Author: Bjorn SCHWENNINGER
Experiment: General Interest
Sub-system: General Interest
Topic: Trigger Electronics

The Muon Pretrigger System of the HERA-B Experiment

M.Adams (Universitaet Dortmund), P.Bechtle (Universitaet Dortmund), P.Buchholz (Universitaet Dortmund), C.Cruse (Universitaet Dortmund), U.Husemann (Universitaet Dortmund), E.Klaus (Universitaet Dortmund), N.Koch (Universitaet Dortmund), M.Kolander (Universitaet Dortmund), I.Kolotaev (ITEP Moscow and Universitaet Dortmund), H.Riege (Universitaet Hamburg), J.Schuett (Universitaet Hamburg), B.Schwenninger (Universitaet Dortmund), R.van Staa (Universitaet Hamburg), D.Wegener (Universitaet Dortmund)

Abstract:

The muon pretrigger system of the HERA-B experiment is used to find muon track candidates as one of the inputs of the first level trigger. Due to the interaction rate of 40 MHz required to achieve an accuracy of 0.17 on sin(2beta) the total input of the muon pretrigger system is about 10 GBytes/s. The latency to define muon track candidates should not exceed 1 microsecond. Therefore the muon pretrigger is implemented as about 100 large size VME modules in a highly parallelized architecture.

We will present the system as well as performance studies and first physics results.

Summary:

The HERA-B experiment at the proton electron collider HERA at DESY, Germany, is designed to study the properties of B mesons with the main emphasis on CP violation. The B mesons are produced by hadronic interactions of protons with an energy of 920 GeV in a fixed wire target. An interaction rate of 40 MHz at an effective bunch crossing rate of 8.5 MHz is required to achieve an accuracy of 0.17 on sin(2beta). This leads to about 200 charged tracks per event in the detector and occupancies up to 20%. Therefore a highly selective and efficient trigger system is needed to suppress the background. It consists of four levels, the first level being a hardware trigger while the higher levels are software based using computer farms. The first level trigger (FLT) including the pretrigger systems must not exceed a latency of 10 microseconds and give a reduction of the input rate by a factor of 200 without causing deadtime. To meet these requirements it performs a track search algorithm either for high pT hadron, electron, or muon tracks, followed by a momentum and charge determination. Then the di-lepton invariant masses are calculated and adjustable cuts are applied.

The track searching of the FLT is being initiated by three distinct pretrigger systems, one of which is the muon pretrigger. It uses the hit information of two adjacent layers of muon chambers to define muon track candidates by means of a coincidence scheme. The building blocks of the muon pretrigger system are approximately 100 VME modules of three different types.

The pretrigger link boards (PLB) transfer the data used by the coincidence algorithm from the data buffers near the detector to the processing units of the muon pretrigger over a distance of 50m. The PLB also adds information to tag the detector data with an identifier to allow for an asynchronous data processing in the trigger system. The data are serialized and transferred via 800 MBit/s optical links to the pretrigger coincidence units (PCU). The main task of the PCU is to execute the coincidence algorithm. Therefore the input data from the PLB boards - amounting to about 20 GBytes/s in total - have to be partially duplicated and distributed to CPLDs which perform the main parts of the algorithm. The processing on the PCU takes place at a rate of 25 MHz. After serializing the coincidence data a pretrigger message generator (PMG) board translates it by means of look-up tables into messages for the FLT processors. These messages contain the track parameters and event identifiers used as starting points for the FLT tracking algorithm.

All muon pretrigger hardware is being operated in HERA-B since end of 1999 and used for triggering. We will present the system as well as results on its performance, which are achieved both from monitoring functions accessing the hardware and from archived event data. Also measurements of the efficiency and inefficiency will be shown, as well as first physics results using the muon pretrigger system.

Id: 57
Corresponding Author: Max URBAN
Experiment: General Interest
Sub-system: Trigger
Topic: Trigger Electronics

First Level Trigger for H1, using the latest FPGA generation

M. Urban, A. Rausch, U. Straumann Physikalisches Institut Universitaet Heidelberg

Abstract:

To cope with the higher luminosities after the HERA upgrade, H1 builds a set of new MWPCs, which provide information to distinguish between beam background and true ep interactions. The first level trigger uses the latest 20K400 APEX FPGAs with 500 user IO pins to find tracks in 10000 digital pad signals. It allows to reconstruct the vertex and cut on its position. The system works deadtime free in a pipelined manner using 40 MHz clock frequency. The pipelines needed for data acquisition are also programmed into the same FPGAs. Test results including timing stability will be shown.

Id: 58
Corresponding Author: Horst FISCHER
Experiment: General Interest
Sub-system: Tracker
Topic: Electronics For Trackers

TDC based Readout for High-Rate Drift Tubes and Wire Chambers

H. Fischer*, J. Franz, A. Grunemaier, F.H. Heinsius, L. Hennig, K. Konigsmann, M. Niebuhr, T. Schmidt, H. Schmitt, H.J. Urban Fakultat fur Physik, Universitat Freiburg, 79104 Freiburg, Germany

Abstract:

The tracking system for the COMPASS experiment at CERN will consist of about 40000 drift tubes. In our report we discuss the design of and the practical experience with the drift-tube readout system which we set up during the year 2000 detector commissioning run.

The front-end board for the electronic processing of the signals produced by the drift tubes contains 64 preamplifiers, shapers, discriminators and time-to-digital converters. For the analog processing of the signals the ASD8b chip has been selected. For the COMPASS experiment we have developed a new TDC (F1) which comprises an asymmetric ring oscillator controlled by a phase locked loop. The digitised signals are transmitted via serial links to readout-driver modules. This 9U VME unit interfaces up to 16 front-end data-links to one optical S-LINK. Besides local event building the FPGA-based module covers front-end board initialisation, trigger distribution and data flow surveillance

Summary:

The tracking system for the COMPASS experiment at CERN will consist of about 40000 drift tubes. In our report we will discuss the design of and the practical experience with the digital readout system which we begin to set up during the year 2000 detector commissioning run.

The overall size of the experiment (6x4x40m^3), the expandability and the upgradability requirements of the experiment prerequisites a scalable and distributed readout system. The paradigm of the COMPASS readout foresees digitisation immediately at the detector. Data are stored on the front-end boards in random access memory or pipelines until trigger decisions have been taken. On-chip zero suppression, sparsification and signal over background extraction is accomplished by time correlation of hits with the trigger time.

The front-end board for the electronic processing of the signals produced by the drift tubes contains 64 preamplifiers, shapers, discriminators and time-to-digital converters. For the analog processing of the signals the ASD8b chip has been selected. The ASD8b has been originally designed for the drift tube readout of the SDC detector. Attractive attributes like short measurement time, good double pulse resolution and low operational threshold makes it the first choice for our application.

To ensure that the position resolution of the drift tubes is not spoiled by the electronics, the digitisation chain is required to have sub-nanosecond timing accuracy. In particular possible interference between the highly sensitive analog input and the high speed digital readout requires careful design and layout of the front-end board.

For the COMPASS experiment we have developed a new TDC chip (F1) which comprises an asymmetric ring oscillator controlled by a phase locked loop. A chain of 19 delay elements is used to tap time digitisation in steps of 120ps to 150ps (programmable). In a different mode, provided for multi-wire proportional chamber readout, 32 input lines are latched in groups of four to the eight TDC channels. In this case the resolution is 5~ns, and the last four bits of the time stamps are used to flag hits on the four connected lines. The F1 is based on a 0.6 micron sea-of-gates CMOS process. Excellent time resolution, high rate capability, low power consumption and wide flexibility due to in-system programmable setup registers let the chip appear as an ideal candidate for many applications not only in drift tube readout.

Further a common readout-driver module for all different detector front-ends has been developed. This 9U VME unit interfaces up to 16 front-end data-links to one optical S-LINK. Besides local event building the FPGA-based module covers front-end board initialisation, trigger distribution and data flow surveillance.

Id: 71
Corresponding Author: Ulrich GOERLACH
Experiment: General Interest
Sub-system: Tracker
Topic: Electronics for Tracker

A Novel Monolithic Active Pixel Sensor for Charged Particle Tracking and Imaging using Standard VLSI CMOS Technology

J.D. Berst, B.Casadei, G.Claus, C.Colledani, W.Dulinski, Y.Hu, D.Husson,
J.P.Le Normand, R.Turchetta, J.L.Riester LEPSI, IN2P3/ULP,
23 rue du Loess, BP20, F-67037 Strasbourg, France

G.Deptuch, U.Goerlach, S.Higueret, G.Orazi, M.Winter IReS, IN2P3/ULP,
23 rue du Loess, BP20, F-67037 Strasbourg, France

Abstract:

A novel Monolithic Active Pixel Sensor (MAPS) for charged particle tracking made in a standard CMOS technology is proposed. The sensor is a photodiode with a special structure, which allows the high detection efficiency required for tracking applications. The partially depleted thin epitaxial silicon layer is used as a sensitive detector volume. A first prototype has been designed and fabricated using a standard sub-micron 0.6 um CMOS process. It is made of four arrays each containing 64 times 64 pixels, with a readout pitch of 20 um in both directions. Extensive tests made with soft X-ray source ( 55 Fe) and minimum ionising particles (15 GeV/c pions) fully demonstrate the predicted performances, with the individual pixel noise below 20 electrons(ENC) and the Signal-to-Noise ratio of the order of 40, both for 5.9 keV X-rays and Minimum Ionising Particles (MIP). A new version of the circuit has been submitted to the 0.35 um Alcatel-Mietec process. This novel device opens new perspectives in high precision vertex detectors as well as in other applications.

Summary:

A novel Monolithic Active Pixel Sensor (MAPS) for charged particle tracking made in a standard CMOS technology is proposed. The sensor is a photodiode, which is readily available in a CMOS technology. The diode has a special structure, which allows the high detection efficiency required for tracking applications. The partially depleted thin epitaxial silicon layer is used as a sensitive detector volume. Semiconductor device simulations, using either ToSCA based or 3-D ISE-TCAD software packages show that the charge collection is efficient and reasonably fast (order of 100 ns), and the charge spreading limited to a few pixels only. A first prototype has been designed, fabricated and tested. It is made of four arrays each containing 64 times 64 pixels, with a readout pitch of 20 um in both directions. The device is fabricated using standard sub-micron 0.6 um CMOS process, which features twin-tub implanted in a p-type epitaxial layer, a characteristic common feature to many modern CMOS VLSI processes. Extensive tests made with soft X-ray source ( 55 Fe) and minimum ionising particles (15 GeV/c pions) fully demonstrate the predicted performances, with the individual pixel noise below 20 electrons(ENC) and the Signal-to-Noise ratio of the order of 40, both for 5.9 keV X-rays and Minimum Ionising Particles (MIP). A new version of the circuit has been submitted to the 0.35 um Alcatel-Mietec process to improve radiation hardness and to explore the performance of deep-sub-micron technologies with thinner epitaxial layers and thus less primary exploitable ionization.

This novel device opens new perspectives in high precision vertex detectors in particle physics experiments at future colliders, as well as in other applications, like low energy beta particle imaging, visible light single photon imaging (using the Hybrid Photon Detector approach) and high precision slow neutron imaging.

Id: 73
Corresponding Author: Stefan LUEDERS
Experiment: General Interest
Sub-system: General Interest
Topic: Optoelectronics & data transfer systems

Compact Bidirectional 2.5 Gbit/s Optical Transceiver for the H1-Experiment

S. Lueders, R. Baldinger, R. Eichler, C. Grab, B. Meier, S. Streuli, K. Szeker
Institute for Particle Physics, ETH Zuerich, 5232 Villigen PSI, Switzerland

Abstract:

For triggering purposes, 9600 channels have to be read out within 96 ns, i.e. with a rate of 100 Gbit/s, using 40 identical very compact optical transceiver units --- each measuring 130 mm x 45 mm x 9 mm. Taking advance of VCSEL diodes and 90 degree fiber bending, 4x 850 Mbit/s of digitized trigger information as well as two channels with analog monitoring information are transferred to the receiver electronics 40 m away. From there two channels of 10 MHz clock information are received for timing adjustments.

Summary :

The upgrade of the multi-wire proportional chamber (CIP) of the H1-experiment at HERA (DESY) increases the number of chamber-channels to 9600. These channels have to be made available to the z-vertex trigger within the time between two bunchcrossings of 96 ns and thus need be transmitted at a total data rate of 100 Gbit/s. With the extremely tight spatial conditions at the CIP end flange --- an open cylinder with inner and outer radii at 150 mm and 200 mm, respectively, and a length of 130 mm --- a fast and compact bidirectional readout electronic is required, keeping the power consumption and the amount of dead-material in the experiment to a minimum.

40 identical transceiver units, stacked on top of each other in groups of five, were designed to feed the digitized trigger information and selectable analog chamber signals to the receiver electronics 40 m away. In the other direction, clock information is provided.

Using the CIPix chip from the ASIC laboratory, Heidelberg, a 16 fold multiplexing is performed on the digitized information.

A custom made optical hybrid serves as an interface between the optical and electrical world, driving VCSEL diode arrays with four channels of trigger information --- each with a data rate of 625 Mbit/s --- and two channels of analog signals. Aligned to the VCSEL array with a precision of 5 mum, an array of two PIN diodes receives the clock signals needed for internal timing. Firmly attached to the hybrid and positioned with high precision, a 8-fiber ribbon cable deflects the light by 90deg within 5 mm of height and transmits the information to and from the receiver electronics. There, the information is reconverted, demultiplexed and passed on to trigger and monitoring tasks.

Id: 94
Corresponding Author: Aurore SAVOY-NAVARRO
Experiment: General Interest
Sub-system: General Interest
Topic: Packaging and Interconnections

Performance of a new MCM-D technology front­end digital readout

P. Cluzel 1 , R. Della­Negra 1 , M. Goyot 1 , M. Miguet 1 , A. Savoy­Navarro 2
1 IPNL­Universit’e Louis Bernard de Lyon/IN2P3­CNRS, France
2 LPNHE­Universit’es de Paris 6 et 7/IN2P3­CNRS, France

Abstract

A CEE ESPRIT project developed a new MCM­D packaging technology with a view to industrial, biomedical and HEP applications. The objective was to establish a cost­efficient, commercial manufacturing base in silicium­ based MCMs, with active substracts and ball­grid array interconnects. Among the main features are the integration of active and passive components in the substrate and the use of a flip­chip technique and wafer rerouting. The demonstrator built with this new technology is a prototype of a fast digital readout front­end electronics, mixing analogue and digital components. The tests show very high functioning performances.

Summary:

A CEE ESPRIT project developed a new MCM-D technology with a view to industrial, biomedical, and H.E.P. applications. The objective of the overall project was to establish a cost­efficient, commercial manufacturing base in silicium­based MCMs, with active substrates and ball grid array interconnects. The new feature of this technology is the integration of passive and active components in the substrate, which would otherwise be connected to an MCM via wire­bonding. The first level of connection of the standard ICs to the substrate is done using a flip­chip interconnect. The development of a commercial source for wafer rerouting to facilitate flip­chip interconnects also constitutes a major goal.

This MCM-D technology presents several advantages due to the use of an active substrate, the flip­chip technique with wafer rerouting and the BGA as interconnects. The active substrate offers as benefits that there is no need to have chips for single active functions, less discrete components for biasing, loading, decoupling and filtering. Moreover it improves the testability thanks to the integrated test structures. All this reduces the lower layers of the substrate are those of the CMOS process and include the active CMOS cells. The upper layers are those of a complementary process and include up to four aluminium interconnect levels and thin­film passive elements such as tantalum­silicon resistors and silicon nitride capacitors.

The use of a flip­chip technique and wafer rerouting gives a size reduction with the reduction of the length of the interconnects and also a reduction of the power consumption. For the interconnects the use of BGA provides self-aligning properties thus leading to a better production yield, it also makes this technology compatible with standard SMD assembly processes and it permits a large number of I/O's.

A demonstrator was built in order to test most of the properties and potentiality of the developed technology. This MCM­based circuit contains the basic components of a fast digital readout front­end electronics for HEP detectors. The two basic components of this fast digital readout are a low noise preamplifier followed by a 12 bit fast analog­to­digital converter, mixing analogue and digital components. It also includes a PLL and boundary scan cells for the testability of some integrated digital functions associated with the ADC, integrated and SMD passive components.

A VME and LABVIEW based test bench allowed to test the performances of each component separately (analogue and digital) and of the overall readout chain. The results of detailed tests on the functioning of this device, show very high performances in terms of noise, stability, imaging properties and signal processing.

ID: 96
Corresponding Author: Stan JAROSLAWSKI
Experiment: General Interest
Sub-system: General Interest
Topic: Systems reliability and quality assurance

Impact of Reliability Specification on Electrical System Design
Stan Jaroslawski

Abstract:

Advantages of addressing Reliability issues very early in any electrical system design is emphasised. An example of an impact of the Reliability specification on the design of a power subsystem is described.  The power subsystem is part of  High Resolution Limb Sounder (HIRDLS) instrument which is to be flown in space as part of Chem1 mission. The main component of the subsystem is a power supply designated Power Converter Unit (PCU). The PCU has to meet HIRDLS instrument system a very tight Reliability requirement of 0.99. The PCU must also meet HIRDLS instrument power requirement (220Watts total), be compliant with spacecraft requirements, and NASA specifications.

Summary:

Reliability issue is a very important factor in the design of any electrical system and equally applies to products destined for consumer market and to scientific apparatus. Instrumentation for LHC will comprise vast electronic front end and data readout systems that will need to work with very high operational efficiencies. Prediction of failures will allow preventive maintenance to be done during shutdowns and will be instrumental in maintaining operational functionality of experiments. Reliability analysis will also very valuable in selection of electrical system configurations in critical areas. Reliability of systems is routinely studied in space satellite projects and the authors hope that the experience gained from building space instruments could be applied to LHC electronic systems in critical areas.
In engineering, and in mathematical statistics, reliability has a real meaning but is very dependent on the quality of manufacturing and assembly processes. In space programmes this is addressed by Quality Assurance (QA) based on extensive Product Assurance (PA) plans. PA plans comprise a wide range of manufacturing procedures that ensure a very high quality of workmanship. PA plans also define the strategy for procurement components, components’ quality, and components’ screening levels. The plans also lay down rules for levels of testing of the end products. The design to the reliability specification of the power supply described in this paper was baselined on such premises.
This paper gives an example of the actual completed design of a power supply and emphasises the impact that the reliability specification. The power supply was designed for the instrument called High Resolution Limb Sounder (HIRDLS) which is to be flown in the space mission designated CHEM1. Design of the power supply was based on DC-DC converters. The power supply converts d.c. power provided by the spacecraft at 29Volts (primary power) into power rails at +5Volts, +/-15Volts and +30Volts rails (secondary power). Secondary power is supplied independently to seven HIRDLS subsystems. The power supply’s operational life in space is  five years and its design theoretical reliability is specified at 0.99 . The reliability specification was achieved after investigating a number of the on board DC-DC converter configurations; a single set of converters parallel redundancy, and standby redundancy. Reliability was analysed in each case and the best result was achieved by a configuration based on the standby redundancy. In the analyses the overall mean time between failures of all EEE parts was calculated and applied to formulae derived form Poisson density function f(t) =  lambda e - lambda t. (All converter configurations are to be shown in separate diagrams).
In conclusion the paper hopes to leave a message that electronics systems that are buried in the depth of complicated LHC detectors are just inaccessible as are instruments flying in space. One could argue that the LHC front-end electronics would be exposed to even more hazardous conditions than instrument flown in space (ionising radiation, for instance). It is therefore prudent to include in the design of exciting electronics a measure of reliability analysis in order to extend its life.

Id: 97
Corresponding Author: John EVANS
Experiment: General Interest
Sub-system: General Interest
Topic: Grounding Shielding Cooling And Alignment

Electronic Design Automation tools for high-speed electronic systems

B.J. Evans
E. Calvo Giraldo
T. Motos Lopez

CERN, IT/CE

Abstract:

The LHC detectors will produce a large amount of data that will need to be moved very quickly.  The signal-speeds and interconnect-density involved lead to difficult electrical design problems, particularly regarding signal-integrity issues.

Various commercial Electronic Design Automation programs are now available to address these problems. These include 3-D full-wave electromagnetic-field solvers, SPICE-based circuit-simulation programs and printed circuit board signal-integrity point products. We will show how these seemingly disparate tools can be used in a complementary fashion to provide detailed studies of detector-electronic design. Two case studies will be presented from LHC experiments.

Summary:

This report shows how various EDA tools can be used for high-speed digital design. These will be classified into three main groups: electromagnetic field calculation, circuit simulation and PCB analysis. We will highlight how each is best suited for a particular class of problem.

Field calculation programs are used when a very detailed behaviour of the system is needed. These can be applied to several critical aspects of high-speed electronics design - connectors, cables and packaging - and will provide the most comprehensive model information.  The tools directly solve Maxwells equations for a given 3D (or uniform 2D) structure and a set of boundary conditions.  Two distinct methods are used to solve these problems.  Pseudo-static codes are used to solve structures whose dimensions are much larger than the wavelength considered.  When the structure dimensions are comparable to, or less than the considered wavelength, a full-wave code has to be used with a corresponding increased simulation time.   CERN has available the set of Ansoft tools (Maxwell 2D/3D Field Simulator and HFSS) and LC from Cray Research.

The output from the field-solver tools can be used as models for SPICE-based circuit-simulation programs which allows much faster analyses in the time and frequency domains.  We have made extensive use of the PSpice simulator during our investigations.

Signal-integrity analysis for a PCB presents a different kind of problem.  Here, possibly thousands of signals have to be examined and a full 3D-analysis would lead to impracticably long simulation times. However, simplified models still provide extremely useful what-if analysis in the pre-layout phase as well as the possibility of highlighting possible signal integrity violations at the post-layout stage.  This approach has the advantage that these programs can be very well integrated with traditional design tools. All calculations are made from the board layout itself and automatically include effects due to track widths, dielectrics and board stackup.  The PCB layout itself can also be driven by a set of design constraint rules.  CERN has available the SpecctraQuest programs which are fully integrated with our Cadence PCB tools.

Two case studies will be presented in this paper.  The first examines the ALICE Pixel Backplane where it has been proposed (ref) to use a meshed power and ground plane for the detector PCB.  This has been analysed while considering two opposing constraints - the PCB has to be as transparent as possible to the beam while still retaining sufficient signal and power-supply integrity.

The second example considers a cable design for ALICE's Time Projection Chamber (ref ). Here, crosstalk calculations were made while respecting the required cable mechanical properties.

Id: 98
Corresponding Author: John EVANS
Experiment: General Interest
Sub-system: General Interest
Topic: Grounding Shielding Cooling And Alignment

Minimizing crosstalk in a high-speed cable-connector assembly

B.J. Evans
E. Calvo Giraldo
T. Motos Lopez

CERN, IT/CE

Abstract

This paper presents the detailed signal-integrity analysis results of a connector-cable assembly linking the ALICE Time Projection Chamber (TPC) to its Front-End Electronics.

The goal was to minimize the crosstalk (electromagnetic coupling) between signal lines for a given line to ground capacitance. Both mechanical (cable flexibility and strength) and electrical (fast signal rise-times) design constraints were considered.

The design was analysed using Finite Element Method software tools to extract equivalent circuit models for the connector and cable. We will show how these programs helped us to quickly investigate different cable configurations. The resulting PSpice simulations will be presented.