Id: 1
Corresponding Author: Attila RACZ
Experiment: CMS
Sub-system: DAQ
Topic: Detector control and real time systems

Trigger Throttling System for CMS DAQ

A. Racz / CERN-EP

Abstract:

This document is a first attempt to define the basic functionnalities of the TTS in the CMS DAQ. Its role is to adapt the trigger pace to the DAQ capacity in order to avoid congestions and overflows at any stage of the readout chain. The different possibilities for the TTS to measure the load on parts of the chain are examined. It clearly appears that one part of the chain needs fast reaction time (few tens of useconds) whereas the rest of the chain can afford longer reaction time, available to nowadays processors.

Summary:

The role of the CMS Trigger Throttling System has been described in global terms. The situation regarding the different stages of the data acquisition chain is quite different. Intrinsically, the most problematic parts are the front-end systems where full custom solutions must be developed. For the rest of the chain, standard and well known solutions can be used.

After this first analysis, it has been shown that the TTS can be split logically and physically into two parts:

- a first one featuring quick reaction time, custom hardware, located in the global trigger logic

- -a second one with slower reaction time, running on the BM processors

Finally, depending on the overflow recovery procedure, the DAQ availability time can be reduced by an inacceptable factor.

Id: 2
Corresponding Author: Pierluigi ZOTTO
Experiment: CMS
Sub-system: Muon
Topic: Electronics for muon detectors

First evaluation of neutron induced Single Event Effects on the CMS barrel muon electronics

S. Agosteo(1), L. Castellani(2), A. Favalli(1), I. Lippi(2), R. Martinelli(2) and P. Zotto(3)
1) Dip. di Ingegneria Nucleare (CESNEF) del Politecnico di Milano, Italy
2) Dip. di Fisica dell'Universit and sez. INFN, Padova, Italy
3) Dip. di Fisica del Politecnico di Milano and sez. INFN di Padova, Italy

Abstract:

Neutron irradiation tests of the currently available electronics for the CMS barrel muon detector were performed using thermal neutrons and fast neutrons at E < 11MeV. The Single Events Upset on the Static RAM was measured, while upper limits are derived for devices having experienced no failure. The results are used to guess the upper limits on the mean time between failures in the whole barrel muon detector.

Id:4
Corresponding Author: Federico FACCIO
Experiment: CMS
Sub-system: Tracker
Topic: Optoelectronics and data transfer systems

Status of the 80Mbit/s Receiver for the CMS digital optical link

F. Faccio, C. Azevedo, K. Gill, P. Moreira, A. Marchioro, F. Vasey
CERN, CH-1211 Geneva 23, Switzerland

Abstract:

The first prototype of the 80Mbit/s optical receiver for the CMS digital optical link has been manufactured in a 0.25µm commercial CMOS process. Its performance satisfies the low power, wide dynamic range, and speed specifications. The required sensitivity (BER of 10^-12 for an optical power of -20dBm) is easily achieved, since this BER is obtained already at -27dBm. The radiation hardness has been verified irradiating the diode with 6 MeV neutrons (up to 6.5·10^14n/cm2) and the receiver circuit with 10KeV X-rays (up to 20 Mrad). Neither type of irradiation did sensibly modify the BER performance of the receiver.

Summary:

The CMS tracker will use approximately 1000 digital optical links for the transmission of timing, trigger and control signals. An optical receiver, made up of a PIN photodiode and a receiver circuit, will convert the digital optical signals into electric signals in a LVDS logic signal. Since the communication channel end sitting inside the CMS detector will work in a harsh radiation environment, radiation hardness is a must for both the photodiode and the receiver circuit. For this reason, and also to decrease the power budget of the receiver, the circuit has been developed as an ASIC in a 0.25µm commercial CMOS technology. The design has been made using enclosed NMOS transistors and guardrings, techniques that have been proven to achieve multi-Mrad TID hardness and to protect the circuit from Single Event Latchup (SEL).

The ASIC has been fabricated and completely characterised before and after irradiation. The power consumption is limited to about 30mW per channel, a factor of ten smaller than for a commercial radiation-soft component with similar performance. To precisely evaluate the sensitivity of the receiver, we have performed Bit Error Rate (BER) measurements at a bit rate of 80Mbit/s using a dedicated setup. The measurements have been made in a configuration similar to the one foreseen for the CMS tracker optical link. Two Fermionics FB80S-7F InGaAs/InP photodiodes have been bonded to two of the receiver channels of the ASIC, one link being dedicated to the clock and the other to the data transmission. In this condition, and with an optical power in the link of -20dBm (which corresponds to 10µW, the minimum specified level), we did not detect any transmission error in more than 15 days, from which we infer a BER below 9.3·10^-15. The CMS digital link requires a BER of 10^-12, which is reached in our configuration for an optical power of about -27dBm (2 µW).

The radiation hardness of the optical receiver has been verified in two ways. First, several photodiodes were irradiated with 6 MeV neutrons up to a fluence of 6.5·10^14 n/cm2. Two irradiated photodiodes were bonded to the receiver circuit, and the BER of the resulting optical receiver channels was measured, revealing no difference from channels where non-irradiated photodiodes were mounted. Second, the radiation hardness of the ASIC was verified with X-ray irradiations up to a TID of 20 Mrad(SiO2). We did not observe any radiation-induced degradation in the BER of the circuit, and the power consumption increase was limited to about 7%.

ID:7
Corresponding Author: Mikhail MATVEEV
Experiment: CMS
Sub-system: Trigger
Topic: Trigger Electronics

Implementation of Sorting Schemes in a Programmable Logic

Mikhail Matveev (Rice University, Houston, TX 77005)

Abstract:

Trigger systems of each CMS muon subdetector (Cathode Strip Chambers, Drift Tubes, Resistive Plate Chambers) will have a muon sorter unit in their upper parts. We report on a design and simulation results for the following sorting schemes: "3 objects out of 18", "4 objects out of 8", "4 objects out of 24" and "4 objects out of 36". All designs are targeted to a single chip implementation based on Altera 20KE Programmable Logic Devices (PLD). The PLD internal sorting latency varies between 1 and 3 cycles of 40MHz clock frequency. Proposed schemes can be used for the fast sorting at the CMS Muon subsystems as well as other trigger systems at LHC experiments.

Summary:

All experiments proposed at the Large Hadron Collider at CERN require a fast and sophisticated multi-level trigger system for data selection. For example, the main task of Level 1 Trigger System at the Compact Muon Solenoid (CMS) Experiment is to reduce the frequency of events from 40MHz down to 100kHz. Level 1 decision should be made in about 3 us after the interaction in the collision area. There are three major muon subsystems at the CMS: Cathode Strip Chambers (CSC), Drift Tubes (DT), and Resistive Plate Chambers (RPC). Currently it is decided that only four best candidates from each subsystem will be passed to the Level 1 Global Muon Trigger. It is considered that there will be a sorter module at the upper part of each muon trigger subsystem which selects four best candidates from several tens of incoming. We propose a fast and flexible solution which would allow to implement such a sorters. Four sorting schemes are discussed: "3 objects out of 18", targeted to Muon Port Card at the CSC Trigger system, "4 objects out of 8" intended for the RPC Sorting Processor, "4 objects out of 24" for the DT Muon Sorter, and "4 objects out of 36" for the CSC Muon Sorter.

We assume that sorting is based on the value of input patterns: higher ranks correspond to "better" patterns for the purpose of sorting. All schemes are targeted to a single chip implementation in order to reduce the overall sorting latency. Each chip receives 8, 18, 24 or 36 7- or 8-bit input patterns and outputs three or four best along with their 5- or 6-bit addresses. We also assume that all patterns come to sorter chip in parallel being synchronized with the main master clock. Input, output and in some cases intermediate latches provide a reliable synchronous operation and predictable timing. Our task was to provide a reliable operation at 40+Mhz with the minimum latency. Finally we assume that all inputs are not pre-selected (or ranked), but all outputs of the sorter chip should be ranked, or present on the outputs of the sorter chip in descending order.

We focus on the implementation of all sorting schemes in Programmable Logic Devices (PLD) rather than in ASIC. The important advantages of using PLD are low non-recurring fees, reprogrammable features as well as a shorten design cycle. Our designs are targeted to Altera 20KE PLD family. All timing parameters are obtained for the fastest available devices.

All sorting schemes are based on multiple comparisons and data multiplexing. We perform as much comparisons as possible (taking into account the architecture of particular PLD) in parallel at the beginning of sorting in order to reduce the number of steps in sorting tree. In case of (n) input patterns the total number of all comparisons between them in N=n(n-1)/2. N results of comparisons would allow us to obtain (4n) combinatorial signals indicating that the particular pattern is the first, second, third, or fourth best. Further these (4n) signals are used for pattern multiplexing onto chip outputs.

Results of simulation using Altera Quartus software are presented. Sorting "3 out of 18", "4 out of 8", "4 out of 24" and "4 out of 36" can be done inside PLD in one, one, two and three clock cycles of 40Mhz clock frequency respectively.

ID: 11
Corresponding Author: Roberto CIRIO
Experiment: CMS
Sub-system: DAQ
Topic: Electronics For Muon Detectors

The CMS DT Muon DDU: a PMC based interface between frontend and data-acquisition

F.Benotto, F.Bertolino, R.Cirio, G.Dellacasa
INFN Torino

Abstract:

CMS will use gas drift tubes as active part of the barrel muon sub-detector. In total 200.000 wires will be readout by TDCs and signals will be sent to data acquisition. The entrance door to the standard CMS DAS will be a board (Detector Dependent Unit - DDU) that will be specific to each sub-detector. We have built a PMC based prototype of the DT muon DDU that features two input channels with Optolink, data check and reconstruction with FPGA and PCI slave output through a FIFO. A description of the board and the FPGA schematics will be given and results from lab tests will be shown.

Summary:

We are developing a PCI Mezzanine Card based digital board that will be used as interface between the frontend electronics of the CMS barrel muon drift chambers and the standard CMS data acquisition system. The drift chambers that instrument the barrel muon detector of CMS will provide 200.000 TDC outputs. The whole frontend electronics will be housed in miniracks located inside the chambers mechanical structure. Each of the 60 sectors (12 phi * 5 weels) in which CMS is segmented will provide an output towards the standard CMS data acquisition. The board we are developing, named Detector Dependent Unit (DDU), will receive data from the sectors, work on them and send them to the standard CMS DAQ.  At the nominal LHC luminosity, the average occupancy of the barrel Drift Tubes will be 1 track/cm^2/s. This figure reflects in 1 muon/sector/event, that adds up to 144 bytes/sector. The total rate for the whole detector will then be 8 MBytes/s. The PMC that we are developing has two inputs, both with an optical transceiver, a serial link, a FIFO. After the two input FIFOs, data are flowing through a Xilinx, that formats them, detects errors and takes appropriate actions. The output of the Xilinx is  sent to a 32 bit output FIFO. The board is a PCI slave, through a PLX 9080 bridge, that can be read with DMA from the CMS DAQ. In case of  errors, the PMC can generate interrupts. The overall schematics of the board will be presented, together with the VxWorks based test setup and test results.

ID: 12
Corresponding Author: Francois VASEY
Experiment: CMS
Sub-system: Tracker
Topic: Optoelectronics And Data Transfer Systems

Project status of the CMS tracker optical links

F. Vasey, C. Azevedo, T. Bauer(1), B. Checucci(2), G. Cervelli, K. Gill,
R. Grabit, F. Jensen, A. Zanet
CERN, Geneva (Switzerland)
(1)HEPHY, Vienna (Austria)
(2)INFN, Perugia (Italy)

Abstract:

The development phase of the optical data transfer system for the CMS tracker is now complete. This paper will present the project status and review the preparation for production. In particular, it will focus on the results of the market surveys for front-end components, and on the performance evaluation of a close-to-final readout chain.

Summary:

The development phase of the optical data transfer system for the CMS tracker is now complete. The ~50000 uni-directional analogue links used for data readout are based on edge-emitting laser transmitters and pin photodiode receivers operating at a wavelength of 1310nm. In every single-mode fibre, 256 electrical channels are time-multiplexed at a rate of 40MSamples/s. Two in-line patch-panels allow to fan-in the individual fibres originating from the transmitters, first to a 12-way ribbon, and then to an 8-ribbon cable carrying 96 fibres away from the detector to the counting room. All system components situated inside the detector volume (lasers, fibres and connectors) are radiation resistant and non-magnetic. The laser transmitters and their connectorised pigtails are based on single-channel devices to best fit the distributed nature of the sensor elements, while in the counting room, the receivers are 12-channel arrays. The ~1000 bi-directional digital links used for control and timing distribution are based on almost identical components as the analogue readout system, but with a different modularity. The transceiver modules placed inside the detector include radiation resistant photodiodes and discriminating amplifiers (which are not needed in the readout system), and the transceiver modules located in the counting room are based on standard commercial components.

Apart from the custom designed electronics for the analogue and digital laser-drivers and photodiode-receivers, all optical link components are based on Commercial-Off-The-Shelf products (COTS). Slight deviations from the standard manufacturing process are only allowed to meet specific functionality requirements such as low back-reflection, or environmental constraints such as high magnetic field. This development strategy has the advantage of minimising development and system cost, but dictates the launch of extensive validation programmes to confirm that as wide a range of COTS as possible can be used reliably in the CMS tracker environment. Before invitations to tender can be sent out and orders can be placed to start the production of optical links in large quantities, potential suppliers must be qualified in the framework of open market surveys. In the case of the CMS tracker, optical components suppliers have been grouped in four categories: manufacturers of lasers, connectors, fibre-cables and receiver modules. As long as the tendering process for these components is not complete, it is not possible to know which exact devices will be used in the final system. By mid-2000, market surveys for semiconductor lasers and optical connectors will be complete, while the remaining surveys of fibre-cables and optoelectronic receiver modules will still be ongoing. In our presentation, we will present the status of these market surveys, review the results of the evaluation procedures, and discuss the plans and timescales to enter production.

In parallel to the tendering procedure, tests of readout and control chains are being performed with close-to-final components and architecture. The specifications will be reviewed and a model simulating the effects of components tolerances on full system performance will be discussed. New experimental results obtainted on a very realistic readout chain will then be presented, including for the first time an opto-hybrid transmitter module and a 12-channel analogue receiver module.

In summary, this presentation will review the system architecture and specification, discuss the results of the market surveys for front-end components, and present the performance evaluation of a close-to-final readout chain.

ID: 14
Corresponding Author: T.Y. LING
Experiment: CMS
Sub-system: Muon
Topic: Electronics For Muon Detectors

Radiation Test of CMS Endcap Muon Front-end Electronics with 63 MeV Protons

T.Y. Ling

Abstract:

After brief overview of the CMS EMU electronics system, results on Single Event Effects, TID and Displacement Effects due to neutron and ionizing radiation will be reported. These results are obtained by irradiating the front-end electronics boards with 63 MeV protons. During the irradiation, the electronics board was fully under power, all ASICs and COTS on the board were active and the data was readout in the same way as designed for CMS.

ID: 16
Corresponding Author: Mikhail MATVEEV
Experiment: CMS
Sub-system: Trigger
Topic: Optoelectronics And Data Transfer Systems(poster report)

Optical Data Transmission from the CMS Cathode Strip Chamber Peripheral Trigger Electronics to Sector Processor Crate

N.Adams, M.Matveev, T.Nussbaum, P.Padley (Rice University)
J.Hauser, V.Sedov (UCLA)

Abstract:

Data representing three muons will be sent from each sector of the CMS Cathode Strip Chambers to the Sector Processor crate residing in the counting room 100 m apart of the detector. We report on the data transmission scheme based on Agilent HDMP-1022/1024 serializer/deserializer chipset and Methode MDX-19 optical transceivers. Six chipsets and six pairs of optical modules are needed in order to transmit 120 bits of data every 25 ns of the main LHC frequency from the peripheral Muon Port Cards to Sector Receiver modules. Results of prototyping, laboratory tests as well as a possible future options for data transmission are discussed.

Summary:

The CMS Muon System consists of three detectors: Cathode Strip Chambers (CSC), Drift Tubes (DT) and Resistive Plate Chambers (RPC). There are up to four stations of CSC in each CMS endcap. CSC front-end electronics is located on chambers as well as in the VME crates mounted on the periphery of chambers. Trigger Motherboard (TMB) matches anode and cathode tags called Local Charged Tracks (LCT) and sends two best combined LCTs from each chamber to Muon Port Card (MPC). Each MPC collects muon tags from up to nine TMBs, which corresponds to a 60 degree sector for stations ME2-ME4 and a 30 degree sector for station ME1. All TMB and MPC cards are located in the VME 9U crates on the periphery of CSC. The MPC selects the three best muons and sends them over optical links to the Sector Receiver (SR) residing in the counting room 100 meters from the detector.

The main goal of the design was an evaluation of existing commercial solutions for the optical data transmission at 40.08MHz. Proposed design is based on Agilent HDMP-1022/1024 chipset and Methode MDX-19 optical transceivers. Six 20-bit chipsets and six pairs of optical transceivers are needed in order to transmit 120 bits of data representing three muons. Our implementation assumes simplex data transmission from the MPC to the SR without a return path. The transmitters use the main 40.08MHz frequency as a reference clock. At the receiver end, a clock oscillator with slightly different frequency is used for frequency acquisition.

Our prototypes have demonstrated a reliable operation at 40MHz. High power consumption and large board space required for optical modules and serializers or deserializers are drawbacks. Further possible implementations of data transmission circuitry from MPC to SR are discussed. One of these options may utilize the latest Agilent HDMP-1032/1034 chipset for serialization and deserialization. Another approach is to use a multi-channel optical receivers and transmitters. We can also use an appropriate commercial or custom solution adopted by other CMS groups.

ID: 18
Corresponding Author: Song Ming WANG
Experiment: CMS
Sub-system: Trigger
Topic: Trigger Electronics

Performance of a Prototype Track-Finding Processor for the Level-1 Trigger of the CMS Endcap Muon System

D. Acosta, A. Madorsky, B. Scurlock, S.M. Wang, University of Florida
A. Atamanchuk, V. Golovtsov, B. Razmyslovich, St. Petersberg Nuclear Physics Institute

Abstract:

We report on the development and performance of a prototype track-finding processor for the Level-1 trigger of the CMS endcap muon system. The processor links track segments identified in the cathode-strip chambers of the endcap muon system into complete three-dimensional tracks. It then measures the transverse momentum of the best track candidates from the sagitta induced by the magnetic bending. The processor logic for the prototype is implemented in high-density FPGAs and SRAM memory. It receives approximately 3 gigabytes of data every second from a custom backplane operating at 280 MHz. Test results of the prototype are consistent with expectation.

Summary:

The prototype track-finding processor links track segments from individual cathode-strip chambers in the overlap and endcap regions of the CMS muon system into complete tracks. The overlap region is the region that the barrel and endcap muon systems overlap. The processor calculates the transverse momentum (Pt) of the track from the sagitta induced by the magnetic bending, and reports the highest quality tracks to the Level-1 Global Muon Trigger. Each processor handles information from a 60-degree sector in azimuth only.

The processor is pipelined at the LHC bunch crossing rate of 40 MHz. Approximately 500 bits of information from the track segments are sent into the processor every crossing, and the overall latency is 400 ns. The processor consists of a Bunch Crossing Analyser, Extrapolation units, Track Assembly units, a Final Selection unit, and an Assignment unit.

The Bunch Crossing Analyzer (BCA) gathers tracks segments in a window of at least two bunch crossings for the processor to analyze. This feature is important because the barrel muon trigger sends two muons from each chamber in the overlap region to the endcap muon track-finder over consecutive bunch crossings, and the bunch crossing assignment to the track segments of both muon systems is not 100% accurate.

An Extrapolation unit (EU) takes the three-dimensional spatial information from two track segments in different stations, and tests if they are compatible with a muon originating from the nominal collision vertex with a curvature consistent with the magnetic bending in that region. All possible extrapolation categories are performed in parallel to minimize trigger latency. Intermediate results on the extrapolations are shared amongst some EUs to resolve the ambiguity in the association of the azimuth and polar hits when there are two track segments in a same chamber.

A Track Assembly unit (TAU) links successful extrapolations into complete tracks. One TAU performs the linkings for the overlap region, and two TAUs for the endcap region. The Final Selection Unit (FSU) gathers the information from the TAUs, cancels redundant tracks, and forwards the three best distinct tracks to the Assignment Unit (AU).

The AU determines the azimuth and polar coordinates, Pt, sign, and the overall quality for each of the identified muon tracks. The muon Pt is measured using the azimuth angles of the track segments measured in two or three stations. A more accurate Pt measurement for low Pt muons is achieved with the three-station measurement.

Each processor delivers up to three best muon candidates to the Endcap Muon Sorter, which forwards the four best muon candidates to the Level-1 Global Muon Trigger.

The track-finding processor is implemented on a 13-layer 9U VME board. The trigger algorithms of the processor are fully programmable as the BCA, EU, and FSU logic is implemented in high-density Field-Programmable-Gate-Arrays (FPGA) from the Xilinx Virtex family. The TAU and AU are implemented in static RAM (SRAM) memory.

Some tests were performed on the prototype. The measured latency agrees with our estimation. The output from the logic algorithms are consistent with those from our simulation of the prototype. We have also measured the maximum clock rate that the processor can be driven.

Id: 23

Corresponding Author: Ignacy Maciej KUDLA
Experiment: CMS
Sub-system: Trigger
Topic: Trigger Electronics

Readout system for the CMS RPC Muon Trigger

Krzysztof Kierzkowski a), Ignacy M. Kudla a), Esko Pietarinen b), Michal Pietrusilski a), Krzysztof Pozniak c)
a) Warsaw University, Institute of Experimental Physics,
b) Univ.of Helsinki Fac.of Science, Helsinki Institute of Physics HIP,
c) Warsaw University of Technology, Institute of Electronics Systems

Abstract:

The CMS detector will have a dedicated subdetector (RPC chambers) to identify muons, measure their transverse momenta pt, and determine the bunch crossing from which they originate. Trigger algorithm is based on muon track search and classification in raw data from the RPC chambers. Trigger system can be built in the control room (far away from detector) where all trigger data are concentrated. Dedicated synchronous compression/decompression algorithm is used to sent all data for each bunch crossing via optical links. Readout system uses the same data as Trigger system and will be placed in Trigger Rack. The idea of readout system and its limitations are discussed. Paper includes description of prototype boards and test results on synchronous CERN test beam.

Summary:

Very low rate of the RPC chamber data enables to use a synchronous compression/decompression data algorithm to transfer only the non zero RPC data from the detector to the control room. Original structure of the data is restored from the string of frames received through data link with additional latency on the control room side. Zero suppression included in synchronous compression scheme is the base of RPC readout system.

Structure of readout system is based on results of theoretical analysis performed for station ME1/1( highest level of rate) with regard of own noise 100Hz/cm2 and zero suppression algorithm realized by LMUXes. Assumed, that 48 links are read and losses of trigger efficiency can not exceed 1%.

All electronic boards of readout system are placed in trigger crates and joint from oneself by local bus. Single module of readout system serves 40 optical links and cooperates with one RDPM. Maximum size of event sent to RDPM reaches about 1kB, instead average prospective size of event attains about 300 bytes. Both sizes are considerably less than 2kB page size fixed for CMS experiment and large margin of safety is warranted. Large number of links forced division of system on two functional parts:

- Slave Readout Board ( SRB): compressed data stream from optical links derandomizes synchronously to trigger experiment ( L1Accept). One SRB serves 8 optical links. All SRB work simultaneously,

- Master Readout Board (MRB): in two stages passes concentration of data stored in buffer memories of SLBs: within crates in first phase and for both crates in second phase. First phase is passed by both MRBs simultaneously, instead in second phase MRB possessing DDU interface executes of final data concentration and make these data available to RDPM.

Prototype of the readout system has been realized in Altera CPLD device (10K series) in 1999 and will be (was) tested on synchronous test beam at CERN.

Description of the Slave Readout (SR) and Master Readout (MR) algorithms were realized in AHDL. Slave Readout test board covers two SR modules working in parallel. The input signals of compressed data stream may be fed by two ways (electrically, by front connectors or optically, through the interface of fibre optic link). The Master Readout test board may work autonomously (has internal clock and requires external trigger signal) or co-operates with TTC circuit (additionally stores event number and bunch crossing number). The event packet, stored in event data buffer, is accessible via VME interface (for computer reading system) and standardized DDU interface (via PCI). The Readout test system assumes nominal parameters for CMS RPC trigger and works with a nominal clock 40 MHz (data transmission from Slave boards to Master board via internal bus is performed with 20 MHz).

Id: 27
Corresponding Author: Antonio RANIERI
Experiment: CMS
Sub-system: Muon
Topic: Electronics For Muon Detectors

Single Event Upset measurements on the Resistive Plate Chambers Front-End chip for the Compact Muon Solenoid experiment

S. Altieri(1), G. Bruno(1), F. Loddo(2), A. Ranieri(2), P. Vitulo(1)
(1)Dipartimento di Fisica Nucleare e Teorica dell'Università di Pavia e I.N.F.N. Sezione di Pavia
(2)Dipartimento Interateneo dell'Università di Bari e I.N.F.N. Sezione di Bari

Abstract:

A measurement of irradiation damaging has been made on the analog front-end electronics of the RPC detector in the CMS experiment. The measurements were performed according to the estimated neutron fluence foreseen in the most irradiated area of the apparatus. The test results are shown, considering all the possible irradiation effects on the custom RPC front-end electronics, encouraging us on the use of the 0.8m Bi-CMOS technologies from AMS, chosen for such type of application.

Summary:

We report on the results of an irradiation test made at the Pavia 250 kW reactor in which some CMS RPCs 8 channels FE chips have been exposed to neutrons.

The Single Event Upset (SEU) rate has beeen measured as a function of the neutron fluence up to some units in 10e11 cm-2.

The Macroscopic Cross Section for SEU events induced by neutrons into the chips has been measured and results will be shown.

The neutron energy spectrum ranged from 0.4 eV to 10 MeV. The SEU rate has been measured to be 0.02 Hz/chip and the relative Macroscopic Cross Section to be around 1.1 x 10-5 cm-1.

No evidence of a sensible deviation from these numbers has been observed while integrating a neutron flux equivalent to what is expected in 10 years of running in almost all of the CMS muon regions.

Moreover other measurements made using more energetic neutron irradiation are also shown, together with the effects obtained on the off-the-shelf electronics mounted on the front-end board to control the analog RPC chip.

Id: 31
Corresponding Author: Richard BREEDON
Experiment: CMS
Sub-system: Muon
Topic: Electronics For Muon Detectors

PERFORMANCE AND RADIATION TESTING OF A LOW NOISE SWITCHED CAPACITOR ARRAY FOR THE CMS ENDCAP MUON CHAMBERS

R.E. Breedon, B. Holbrook, Winston Ko, D. Mobley, P. Murray, S.M. Tripathi
University of California, Davis, CA 95616 USA

Abstract:

The 16-channel, 96-cell per channel switched capacitor array (SCA) ASIC developed for the cathode readout of the cathode strip chambers (CSC) in the CMS endcap muon system is ready for production. For the final full-sized prototype, the Address Decoder was re-designed and LVDS Receivers were incorporated into the chip package. Under precision testing, the chip exhibits excellent linearity within the 1V design range and very low cell-to-cell pedestal variation. Performance of the SCA during beam tests of a fully-instrumented chamber and results from radiation testing at a 63.3 MeV proton cyclotron will be presented.

Summary:

During the first-level trigger latency period of approximately 128 bunch crossings (3.2 us), signals from the front-end electronics of sub-detectors in CMS must be held in temporary storage before being passed to the DAQ system or rejected. The endcap muon system employs a switched capacitor array to allow full-wave sampling and storage of the precise cathode measurement before digitisation. This enables a higher level of control over pileup effects (baseline shift) than other pipeline options. The SCA supports random addressing and simultaneous reading and writing for deadtimeless operation.

A pulse on a strip of a CSC emerges from the preamp/shaper (Tpeak = 100 ns) and is split into two signals: one for the level-1 trigger, the other sampled by the SCA at 20 MHz. Eight samples of each pulse are saved in the SCA, the first 2-3 of which are taken before the pulse rise to establish the baseline. Sixteen cathode strip channels from each of the six layers in a muon station are connected to a front-end board (CFEB). Sixteen channels from one layer are handled by one SCA. Each channel has 96 capacitor cells; cells selected for readout are multiplexed within the SCA. As the SCA will be used also for the innermost ME1/1 chamber, a total of 16,632 CSCs will be required.

The final prototype SCA was fabricated in the AMI 0.8 um CWL process via submission to MOSIS. A custom test board provides the interface to a Tektronix Data Analysis System (DAS) 9200, which selects test voltages and provides SCA addresses. The design is optimised for a 1V input range, although pulses up to 3V may be handled with reduced accuracy. Operating at full speed, the RMS deviation from linearity over 0-1V is about 0.6%. There is remarkably low noise affecting the cell-to-cell pedestal variation: With a fixed input voltage, the RMS variation of output voltages over all capacitor cells is 0.05-0.06%.

For the final production design, we have incorporated LVDS receivers into the ASIC to conserve space on the CFEB and reduce noise. Thirty samples of the previous iteration were used to populate five CFEBs to instrument a full-sized CSC prototype for beam tests at CERN in September 1999. The SCA performed excellently and results from the cathode analysis will be presented.

We monitored samples of the production design while they were exposed to a 63.3 MeV proton beam. We will present threshold shift curves for both powered and unpowered irradiated chips. The performance of chips bench-tested after exposures of up to 100 krad was within tolerances of an unexposed part.

Id: 47
Corresponding Author: Gustavo CANCELO
Experiment: CMS
Sub-system: Tracker
Topic: Optoelectronics And Data Transfer Systems

Fiber Optic based readout for BTeV's Pixel Detector

Gustavo I. E. Cancelo*, Sergio Zimmermann*, Sergio Vergara**, Peter Denes*, Guilherme Cardoso*, Bob Downing*, Jeff Andresen* * Fermilab, **University of Puebla, Mexico

Abstract:

The current paper describes the design of BTeV's Fiber Optics Pixel Detector readout. The pixel detectors will be located as close as 6mm from the accelerator's beam into the vacuum pipe. The readout electronics will be located at about 6cm from the beam, imposing strong constrains regarding radiation, mass, power dissipation, vacuum and size. This paper includes an analysis of the convenience of using a fiber optic based readout versus alternative solutions. Since the current design will place several components in a high dose proton and gamma radiation environment the fiber optic based readout will need some radiation hardened custom components, which are here specified. Furthermore, test results on optoelectronic devices are provided along with future plans to complete the design.

Summary:

BTeV's pixel detector consists of 31 double-plane stations of about 100cm² of active detection area. These planes are perpendicular to the direction of the beam. The beam passes through the center of the plane formed by two halves as shown Figure 1. Since BTeV intends to use the pixel detector as part of the lowest level trigger system, one of the most important requirements is hit readout speed [1]. The primary goal is to achieve a data transfer rate high enough to sustain the hit readout rate generated at a luminosity of p/cm² and a bunch crossing (BCO) time of 132 ns at Fermilab's Tevatron. Furthermore, the required readout bandwidth must be achieved while keeping small power and mass budget. In particular, mass is very critical for the Pixel Detector, the most inner part of BTeV's detector where multiple scattering must be minimized.

A fiber optic based design, as proposed in this paper, is the technology that best adapts to BTeV's requirements. Every pixel plane will generate, in average, 4Gb/s of data. The pixel amplifier and discriminator chips, located underneath the pixel detectors will store that information. However, since the pixel detector is the primary component of BTeV's trigger, the data must be readout as soon as possible. A modular design is being proposed for the pixel detector electronics as shown in Figure 1. Every module is autonomous. It groups a certain number of Pixel amplifier/discriminator chips and the readout electronics to transfer the data from the pixel planes to the experiment's counting room. Furthermore, every module must allow for an incoming link to receive several commands to initialize and control the pixel devices and provide them with timing information (i.e. clocks).

The readout electronic serializes the data from the pixel chips into high speed serial links. A 1.06Gb/s link is being proposed based on a custom CHFET GaAs design[2]. This device has undergone functionality, BER and radiation tests. It has shown to be radiation resistant and SEU free. Several test results are provided in this paper. The serializer device has a built in VCSEL driver. VCSELs have proven to operate at very high speeds and be radiation resistant. Test results will be shown.

The control and timing link will have a fiber optic receiver to decode the signal coming from a PIN photodiode. The operative frequency is 53.4MHz. This device must also be radiation resistant. The specifications of this chip are completed. In order to reduce the number of fibers to minimize the total mass, the data and clock signals will be encoded together following a bi-phase encoding. A prototype board has been developed to qualify the bi-phase approach working together and generating a low jitter clock for the gigabit serializer. Performance results will be supplied.

Finally, two new developments are being worked out with a company in the optoelectronic business to generate a very small profile optical assembly for the VCSEL and PIN components, and a hermetic package to exit the accelerator's vacuum pipe. The semi-custom VCSEL and PIN assembly design will allow the Pixel Module to be connected and disconnected from the fiber, allowing the modules to be tested and assembled individually, decoupling the inherent module's yield from the optoelectronic issues. In order to reduce the number of points where the vacuum pipe is disrupted, he hermetic package will handle several fibers. The optimum number is still unknown, but decoupling the modules from the fibers is important to better track the problems and increase the overall yield by being able to change individual pieces.

REFERENCES: [1] BTeV: An Expression of Interest for a Heavy Quark Program at C0, BTeV collaboration, Fermilab, May 18, 1997. [2] Radiation Hard Gigabit Systems. Second Workshop on Optical Readout Technologies for ATLAS, Oxford, January 7-8 1999.

Id: 54
Corresponding Author: Guido MAGAZZU
Experiment: CMS
Sub-system: Tracker
Topic: Detector Control And Real Time Systems

The Detector Control Unit: an ASIC for environmental monitoring in the CMS central tracker

Guido Magazzu' - INFN Sezione di Pisa
Alessandro Marchioro - CERN EP-MIC
Paulo Moreira - CERN EP-MIC

Abstract:

The readout system of the CMS central tracker performs several functions: readout of the data from the front-end ASICs, distribution of the timing and trigger signals, distribution and collection of the slow control and status information and collection of local environmental parameters. The DCU (Detector Control Unit) is an integrated circuit which monitors parameters such as the leakage current in the silicon detectors, local voltages and temperatures. All these measurements can be performed by one analog multiplexer followed by a A/D converter interfacing to the slow control system. Such functions could easily be performed by a number of commercial devices, but the constraints of radiation tolerance, low power and maximum integration lead us to design a special integrated circuit which will be here described.

Summary:

Silicon microstrip detectors, when exposed to the high level of radiations of the LHC, are subject to a number of damaging phenomena demanding a careful monitoring of their environmental conditions. To assure proper operation over the expected 10 years lifetime, one has to guarantee that the leakage currents in the microstrips do not exceed certain values and - to avoid reverse annealing phenomena - that the detector is kept at a conveniently low temperature during the whole lifetime. The vital quantities that one needs to monitor close to the silicon strip detector and to the front end modules are therefore the leakage currents of the silicon detectors in the range of 100uA to 10mA and the temperature of the detectors themselves (which can be fairly easily sensed through the utilization of appropriate thermistors) in the range -20 to 20 deg C with a precision of about one degree. Such quantities need to be read and logged with relatively low frequency, therefore a fast conversion time is not important. The hardware necessary for the monitoring of these quantities allows also to monitor other environmental parameters, for instance the local supply voltages, the temperature of the high density hybrid housing the front-end integrated circuits etc. The Detector Control Unit (DCU) perform all these functions in one single integrated circuit. This integrated circuit consists basically of a 12-bit A/D converter which uses a single slope architecture, preceded by an 8 input analog multiplexer. One input is reserved for an on-chip temperature sensor, which measures the temperature of the substrate onto which the chip is mounted, and seven other inputs which are available to measure voltages in the range -1.0 to +1.0 V (almost rail-to-rail). The A/D conversion time is ~ 1 ms and the analog reference to the A/D consists of an on-chip bandgap reference block. As the external temperature sensors are essentially resistors and the input of the DCU is capable of reading voltages, a temperature independent, stable current reference output is also made available from the chip. The DCU is interfaced to the tracker control system via a standard I2C port, through which the user can select one multiplexer input out of the 8 available, start a conversion in the A/D and read the conversion result. The DCU ASIC is designed in a commercial quarter micron technology using special layout techniques to enhance its radiation tolerance. The total chip area measures about 2.0 x 2.0 mm2, has 28 pins and the power consumption is estimated to be less than 50 mW. The digital part of the chip uses triple redundancy and voting to insure protection against SEU effects. To achieve almost rail-to-rail input compatibility, the analog circuitry uses some complementary solution based on double Nmos and Pmos transistors and has an automatic offset cancellation feature. The circuit has been submitted to fabrication and the measured results will be presented.

Id: 59
Corresponding Author: Dave NEWBOLD
Experiment: CMS
Sub-system: Trigger
Topic: Trigger Electronics

An FPGA-based implementation of the CMS Global Calorimeter Trigger

J. Brooke (University of Bristol) D. Cussans (University of Bristol) G. Heath (University of Bristol) A. J. Maddox (Rutherford Appleton Laboratory) D. Newbold (University of Bristol, Corresponding Author) P. Rabbetts (Rutherford Appleton Laboratory)

Abstract:

We present a new design for the CMS Level-1 Global Calorimeter Trigger, based upon FPGA and commodity serial link technologies. For each LHC bunch-crossing, the GCT identifies the highest pt electron, photon and jet candidates; calculates scalar and vector total transverse energies; performs jet-counting, and provides real-time luminosity estimates. The pipelined system logic is implemented using 0.18um Xilinx FPGAs. The traditional system backplane is replaced by fast serial links for trigger data, and Ethernet for control. These technologies allow an improvement in system flexibility and a considerable reduction in cost, complexity and design time compared to an ASIC/VME-based solution.

Summary:

The CMS Level-1 Global Calorimeter Trigger is the final component in the CMS calorimeter trigger chain. It reduces the data flow to the Level-1 Global Trigger by sorting the various categories of calorimeter trigger objects to find those with the highest transverse momentum. It calculates the scalar and vector total transverse energy for each LHC bunch-crossing to allow missing-energy triggers, and provides an indication of jet multiplicity to the Global Trigger to allow multi-jet triggers. The GCT will also perform luminosity monitoring in real time on a bunch-by-bunch basis, based on high-pt jet multiplicities, global energy flow measurements, and other signals.

The system design has recently been reviewed, and a new approach based upon high-performance commodity technologies has been proposed. The custom ASICs previously used for the sort, energy calculation, and other functions, are replaced by 0.18um Xilinx Virtex-E FPGAs. The system backplane is replaced by fast inter-board serial links based on a National Semiconductor Channel Link chipset, along with ethernet for system control and monitoring. The VME crate controllers are replaced by embedded processors on every trigger board, running the Linux operating system. The new system includes improved self-test capability, including JTAG for chip-level diagnosis. Taken together, these technologies allow an extremely flexible and modular system design; the entire range of trigger processing functions are implemented using seven identical boards, differentiated only by the FPGA programs. The cost and design time advantages of such an approach are highly significant. There are also benefits for the software creation and hardware and software debugging tasks. The system is at an advanced stage of prototyping, and the GCT generic trigger processor boards are also being considered as part of an upgrade to the ZEUS Level-1 trigger.

Id: 61
Corresponding Author: Wesley SMITH
Experiment: CMS
Sub-system: Trigger
Topic: Trigger Electronics

CMS REGIONAL CALORIMETER TRIGGER HIGH SPEED ASICs

P. Chumney, S. Dasu, M. Jaworski, J. Lackey, W.H. Smith

University of Wisconsin - Madison

Abstract:

The CMS regional calorimeter trigger system detects signatures of electrons/photons, taus, jets, and missing and total transverse energy in a deadtimeless pipelined architecture. This system contains 19 crates of custom-built electronics. Much of the processing in this system is performed by five types of 160 MHz digital ASICs. These ASICs have been designed in the Vitesse submicron high-integration gallium arsenide gate array technology. The five ASICs perform data synchronization and error checking, implement board level boundary scan, sort ranked trigger objects, identify electron/photon candidates and sum trigger energies. The design and simulation of these ASICs and prototyping results are presented.

Summary:

The CMS Regional Calorimeter Trigger receives compressed data from the calorimeter readout electronics on 1.2 GBbaud copper links, each carrying data for two HCAL or ECAL trigger towers accompanied by error detection codes. 19 total crates (18 for the barrel/endcap and one for both forward calorimeters) each contain seven rear mounted Receiver cards, seven front mounted Electron Isolation cards, and one front mounted Jet Summary card plugged into a custom point-to-point 160 MHz differential ECL backplane. Each crate transmits to the global calorimeter trigger processor its sum Et, missing energy vector, 4 highest-ranked isolated and non-isolated electrons, and 4 highest energy jets and 4 tau-tagged jets along with their locations.

The five digital ASICs developed for the regional calorimeter trigger are the Adder ASIC, Phase ASIC, Boundary Scan ASIC, Sort ASIC and Electron Isolation ASIC. They were produced in the Vitesse FX(TM) and GLX(TM) gate arrays utilizing their submicron high integration gallium arsenide MESFET technology. Except for the 120 MHz TTL input to the Phase ASIC, all ASIC I/O is at 160 MHz ECL.

The Phase ASIC deskews the 120 MHz TTL data from the input 1.2 GBaud copper receiving and deserializing circuitry. It performs error detection and multiplexes the output at 160 MHz ECL. The Phase ASIC also provides test vectors for board and system diagnostics.

The Boundary Scan ASIC implements board-level Boundary Scan and backplane drivers.

The Adder ASIC provides a 4-stage pipeline with eight input operands and 1 output operand. There are three stages of adder tree, with an extra level of storage added to ensure chip processing is isolated from the I/O. The ASIC uses 4-bit adder macro cells to implement twelve bit wide adders.

The Electron Isolation ASIC, processes a total of 36 towers through three separate blocks. The Input Staging block places each reference tower and its neighbors in the same time frame. The Add/Compare block forms four sums between a reference tower and its top, bottom, left and right neighbors. The Find Max block places the single maximum from the original four sums in a register. The HAC Veto, neighbor HAC Veto, and neighbor EM Veto are stored with each of these sums. A final stage of logic sorts through all 16 maxima generated over a bunch crossing time and places that value, along with its Vetos, on the outputs.

The Sort ASIC reads in 4 sets of 4 operands every 25 ns. Each set of 8 operands is divided into two groups of four. The operands are compared in pairs between the two groups, with the larger of the two taking over the position of the left hand member of the pair. This comparison is performed in four stages with a rotation of compared pairs occurring between each stage. By the end of the fourth stage a sufficient number of comparisons have been made to ensure the four largest values of the 16 inputs are in the left-hand group.

Id: 66
Corresponding Author: Claudio RIVETTA
Experiment: CMS
Sub-system: Calorimetry
Topic: Low Voltage And High Voltage Distribution

Design Considerations of Low Voltage DC Power Distribution for CMS Sub-Detectors

B.Allongue, F. Fontaine, F. Szoncso, G. Stefanini CERN Switzerland S. Lusin, P. Robl University of Wisconsin, Madison, USA J. Elias Fermilab, USA C. Rivetta ETH Zurich/CERN Switzerland

Abstract:

A distinguishing feature of LHC detectors is the enormous number of front-end electronics (FE) channels in all of the sub-detectors. Low-voltage power supply systems in the range of multi-kilowatts are required to bias such electronic read-outs. Several configurations has been proposed and analyzed by the different groups showing particular advantages and disadvantages. For the CMS detector, the Hadronic Calorimeter (HCAL) and the Muon End-caps (EMU) have proposed a DC power distribution system based on DC-DC power switching converters.

The topology of this DC power distribution is as follows: AC/DC converters in the control room are used to rectify the three phase mains and generate the primary 311 VDC voltage. Each rectifier supplies several DC-DC converters located in the cavern near the FE. The switching regulators convert the high voltage into appropriated low voltages that are locally distributed to the detector read-outs. Local regulation is performed in the FE at the board level using special linear low-dropout voltage regulators developed by CERN RD-49 collaboration.

The main advantage of this topology is the reduction in volume of the distribution cables due to the relative low primary currents. Locating the DC-DC converters in the hostile environment of the detector cavern is a disadvantage due to the presence of magnetic fields and radiation. Analysis and tests are necessary to characterize the behavior of those units under such conditions and find acceptable solutions. Also, further studies and tests are necessary to mitigate the radiated and conducted noise generated by the switching converters, to ensure stability of multi-converter systems against interactions between units, etc.

In this paper, tests conducted to validate the application of commercial units are reported and future tests are described. Also, an analysis of the overall system performance is presented along with guidelines for design and selection of the components are presented.

Summary:

This paper describes the tests performed to validate switching converter units to be applied in the DC power distribution of CMS-EMU and CMS-HCAL sub-detectors.

Modularity of the DC-DC converters is the primary requirement. It will facilitate replacement of failed units during short-period scheduled access to the cavern providing a reduction in the time that a part of the sub-detector is down. Each modular unit will thus include not only the basic power converters to attain the required output low-voltages but also protection, filtering, monitoring system and interface for remote operation. The tendency is to use commercial units (COTS) to fulfill this design but it is difficult to satisfy all of the requirements with such units. Instead, a 'semi-custom' design has been used based on COTS with the collaboration of manufactures, assembly companies and the universities and laboratories involved.

The primary stage of the design is the search for suitable units that can operate in environments with radiation. A radiation test has been conducted and future tests are under evaluation. The idea is to characterize the radiation tolerance of candidate converters and analyze, in case of failure, critical component to be replaced in the prototypes.

These tests include total dose effects and Single Event Effects (SEE) (single event up-set, single event latchup, single event breakdown, etc.). The first test was performed at the Commisarat d'Energy Atomic (CEA), Dijon, France. A low energy neutron reactor was used to test commercial DC-DC units for total dose effects. Two Vicor converters with 300V input and 5V / 12 V output, 400W, were radiated up to a level of 3x10^11 neutrons/cm^2 during an 8 hrs exposure which represents the total dose for continuous operation over 10 years. The results were satisfactory measuring only less that 0.5% of drift in the output voltage of the converters. This behavior was the similar to the one experienced in previous tests performed on other Vicor units with different characteristics. In future tests, higher energy particles will be used to study the SEE performance of these units and of new prototypes acquired from different vendors.

The magnetic field, in the areas assigned for the DC-DC converters, is about 200mT (2000 Gauss). This level is inappropriate for good operation or performance of converters with magnetic components. This problem involves a study of the maximum levels of magnetic field in different directions that the converter can tolerate operating with good performance. Studies and tests of the inductance and transformer of Vicor converters have been performed using a constant magnetic field at CERN. In the experiment, the level of magnetic field around the converter units will be reduced to an adequate level using a soft-steel magnetic shielding.

Switching power supplies, in general, are noisier than equivalent linear power supplies. In the CMS application it is very important to keep the noise level below values that do not compromise the operation and performance of the FE and neighbor systems. Conductive and emitted noise tests are scheduled on the Vicor units and input/output cables. The first test is performed on Vicor units connected through standard input/output cables to allow a determination of the level of filtering necessary and the shielding necessary in the cables to reduce both the conducted and emitted noise. Similar tests are planned on new prototypes.

Due to the negative input impedance characteristic of the DC-DC switching regulators at low frequencies, interaction between switching regulators and the others part of the input system may result in system instabilities. Small and large-signal models of both converters and line conditioners have been evaluated to analyze the performance and stability of the whole system. Based on this analysis, guidelines to design the proper input filtering of the DC-DC converters is presented.

The Front-end electronics will use on board radiation tolerant linear regulators. This choice simplifies the design of the connection between the converters and the FE because remote sensing is not required. The regulators will absorb the voltage variation due to the drop in the line resistance by changes in the load current. The only consideration on this link is to provide enough damping on the lines with passive elements to avoid big voltage excursions at the FE input.

An additional, but important, last consideration is the reliability of the complete system. As presented above, the DC-DC converters should be modular to assure the easy replacement in case of failure. That allows consideration of units with industry standard mean time between failure (MTBF) performance. If it is not possible to replace units during scheduled weekly accesses, then units with longer MTBF or N+1 redundant units are necessary.

Id: 68
Corresponding Author: Fredrik Jensen
Experiment: CMS
Sub-system: DAQ
Topic: Optoelectronics and data transfer systems

Statistical performance estimation and optimization of the CMS tracker optical links

F. Jensen, C.S Azevedo, G.Cervelli, K.Gill, R.Grabit, F.Vasey
CERN, Geneva, Switzerland

Abstract:

A significant number of analogue performance measurements have been carried out on the CMS tracker optical links with components selected to be close the final system. The measurements form the basis for an estimation of the expected analogue performance of the final tracker links. In particular the typical S/N and linearity performance will be estimated. Realistic performance limits based on estimations of the performance spread of the final 50000 links are also deduced. Finally we discuss ways to further optimize the analogue performance of the optical links using offline processing.

Summary:

The CMS tracker optical links project is in a phase where it is possible to identify the final components to be used in the tracker optical link system. Market surveys have been issued and the component selection process is well underway for the whole system with some additional development work remaining mainly for the electronics. These developments have enabled tests to be carried out with links that closely resemble the final system in significant numbers. These measurements form the basis for a statistical estimation of the analogue performance of the final tracker links. In particular the RMS-noise, Signal-to-Noise Ratio and non-linearity distributions are extracted. The analogue performance distributions enable realistic estimations of typical performance and performance spread of the final 50000 links to be deduced, and realistic system performance limits are shown. These results in turn make it possible to carry out a comparison with the link specifications and determine how successful the system and component specifications have been in achieving adequate analogue performance for the links. Finally we discuss ways to further optimize the analogue performance of the optical links using offline processing. In particular we look at ways to reduce system non-linearity by using a modified link calibration scheme.

Id: 70
Corresponding Author: Ulrich GOERLACH
Experiment: CMS
Sub-system: Tracker
Topic: Electronics for Tracker

CHARACTERISATION OF THE APVD READ-OUT CIRCUIT FOR DC-COUPLED SILICON DETECTORS (Final report)

J.D. Berst, C.Colledani, Y.Hu, R.Turchetta, LEPSI, IN2P3/ULP,
23 rue du Loess, BP20, F-67037 Strasbourg, France

G.Deptuch, U.Goerlach, C. Hu-Guo, P.Schmitt, IReS, IN2P3/ULP,
23 rue du Loess, BP20, F-67037 Strasbourg, France

M.Dupanloup, S.Gardien, IPNL IN2P3/CNRS, F-69622 Villeurbanne, France

Abstract:

The APVD integrated circuit for the front-end electronics of DC-coupled silicon detectors for CMS has been developed and produced in the radiation-hard process DMILL.The APVD_DC contains, like other members of the APV family 128 identical analog channels, each composed of a low noise preamplifier, a CR-RC shaper, an analog pipeline of 160 cells and a signal processing stage. A current compensation circuit is added in every preamplifier to sink the leakage current coming from the detector.

We report on the final test results: the complete circuit has been tested and measured also in the presence of significant leakage currents up to 11 microampere which do not deteriorate the analog performance of the circuit like pulse shape dynamic range and adding about 300 ENC to the noise.

Previous APVD circuits suffered from an instability problem in the analog stage of the circuit occurring at nominal bias values. The analog baseline of the new modified circuit is absolutely stable also under extreme operation conditions, like high bias currents demonstrating that the implemented solution stops indeed the oscillation of the circuit as we previously claimed based on extensive simulations of the circuit.

Id: 72
Corresponding Author: Dezso NOVAK
Experiment: CMS
Sub-system: Calorimetry
Topic: Electronics for Calorimeter

Radiation hardness studies for CMS HF quartz fiber calorimeter

G. Dajkó, A. Fenyvesi, K. Makónyi, J. Molnár
Atomki, Debrecen, Hungary

P. Raics
University of Debrecen, Debrecen, Hungary

I.Dumanoglu
Cukurowa University, Adana, Turkey

J. P. Merlo
University of Iowa, Iowa City, USA

A Kerek, D. Novák
Kungl Tekniska Högskolan, Stockholm, Sweden

Abstract:

A project has been in progress to provide information on radiation hardness properties of Hamamatsu photomultiplier tubes and quartz-fibers to be used in the construction of CMS Very Forward Calorimeter. Neutron activation studies as well as neutron, gamma and electron radiation tolerance tests have been carried out, using 3.7 MeV average energy neutrons, 500 MeV energy electrons and Co-60 gamma radiation. The test setups, the irradiation conditions as well as the experimental results are described.

Summary:

Introduction

Very Forward Calorimeters (VFCs) in LHC detectors cover the pseudorapidity range from 2.5 to at least 5 in order to compute missing transverse energy and for jet tagging. The forward calorimeter (HF) in CMS will experience unprecedented particle fluxes. The 10 years of LHC operation will result in about 1 GRad total dose. Operation at such conditions requires the use of calorimetry technique that is insensitive to radiative load.

The CMS HF is based on the quartz-fiber technology, using silica-core and silica-clad fibers as the active component. This choice was based predominantly on their exceptional radiation resistance. In such a calorimeter, the signal is detected when charged shower particles above the threshold generate Cherenkov light.

The read-out of the light from the fibers are done by UV sensitive photomultiplier tubes (PMT).

The purpose of this paper is the presentation of the performances of the different kinds of silica fibers and ultra-violet photodetectors in the presence of radiation. We focused on a shorter wavelength region between 325 and 800 nm under an irradiation field, with special attention to the PMTs sensitivity range, 400 to 500 nm.

Test facilities and conditions

An IBM-PC based Ocean Optics Model (SD 2000 type) spectrometer with a pulsed Xe lamp was used for all fiber related measurements. One part of a Xe light pulse goes directly to the spectrometer as a reference. The second part is sent to the fiber sample under irradiation. This setup allows in-situ measurement of the fiber darkening. We performed measurements at two different facilities: at the LIL. The LIL , LEP pre-injector at CERN provides a 500 MeV electron beam on the target.

In the fast neutron tests at ATOMKI in Debrecen, Hungary the MGC-20 cyclotron based neutron source was used generating neutrons with an average energy of 3.7 MeV.

All the HAMAMATSU PMT tests - gamma, neutron, and activation - were carried out at ATOMKI.

Analysis and results

The expression for the light attenuation of the fibers can be written as:

A(l)=Ao(l)-(10/L)log(Iirr(l)/Io(l))

where Ao(l) is the attenuation of the fiber prior to irradiation, L is the length of the irradiated fiber and Iirr, Io are the spectral intensities measured for irradiated and unirradiated cases.

The LIL measurements exhibit the well-known absorption peak of high OH content quartz-fibers around 630 nm. In the range from 400 to 525 nm where the HF detector is sensitive for Cherenkov light, the attenuation is typically varying between 2-3 dB/m. In the results of fast neutron tests the UV-tail and the absorption band at around 630 nm are also clearly observable. At 1E15 n/cm2, the induced loss in the region of interest is about 1 dB/m.

Concerning the R5600 type PMTs we carried out a series of measurements like spectral response, dark current characteristics, gain variation, energy spectroscopy and activation as a function of the neutron flux-rate, fluence and the gamma total dose. We observed no degradation in optical characteristics of the tubes for low-flux and low fluence irradiations.

Id: 74
Corresponding Author: Franco Gonella
Experiment: CMS
Sub-system: Muon
Topic: Electronics for muon detectors

The "MAD", a Full Custom ASIC for the CMS Barrel Muon Chambers Front End Boards

Franco Gonella and Matteo Pegoraro from INFN - Sez. Padova (Italy)

Abstract:

Front end electronics of CMS barrel muon chambers is built around a full custom ASIC, named MAD, designed and developed by INFN Padova, that provides amplification, discrimination and cable driving circuitry for a quadruplet of drift tubes.
The system is organized in compact boards located in the gas volume and includes I2C slow control features for channels enable/disable and temperature monitoring, and a flexible test pulse system for calibration purposes.
Attained results confirm the good performances of the system; particularly, big effort was put in radiation tests (neutron, gamma rays and ions) to check behavior and reliability in LHC environment.

Summary:

Front end electronics of CMS barrel muon chambers is organized in compact boards (Front End Board, located in the detector gas volume) whose fundamental component is a full custom ASIC (named MAD) that provides the primary processing of drift tubes signals. To accomplish the variable size of the chambers two version of FEBs are produced differing in the number of electronic channels: 16 or 20.
The ASIC, 2.5x2.5 mm2 die area, is made using 0.8 µm BiCMOS technology by Austria Mikro Systeme and housed in a TQFP44 package; the chip was designed and developed by INFN Padova.
The task of this IC is to amplify signals picked up by chamber wires, compare them against an external threshold and transmit the results to the acquisition electronics.
The working conditions of the detector set requirements for high sensitivity and speed combined with low noise and little power consumption. Moreover, as the basic requirement for the front end is the ability to work at very low threshold to improve efficiency and time resolution, a good uniformity is also needed for sensitivity and threshold between channels of different chips.
The ASIC implements 4 complete analog chains, each made of a charge preamplifier and a simple shaper with baseline restorer, whose output is compared with an external threshold by a latched discriminator; the output pulses are then stretched by a programmable one shot and sent to an output stage able to drive long twisted pair cables with LVDS compatible levels.
A temperature sensor with sensitivity of 7.5 mV/°K and masking features for disabling noisy channels at shaper stage and check trigger functionality are also included.
Gain value is 3.3 mV/fC in average, constant up to 500 fC input with less than 1% integral nonlinearity; saturation occurs at about 800 fC. Threshold uniformity is very good, the r.m.s. is below 0.6 mV; propagation delay is about 4 ns.
Key characteristics for low threshold operation are noise and crosstalk: bare chips exhibit ENC of 1400 e- (slope of 60 e-/pF) and a value below 0.1% for the latter while complete board increase these two figures to 1900 e- and 0.2% mainly because of input protection network.
Also included in the FEBs are an I2C bus interface to set masks and temperature probe output and a flexible test pulse system for time and trigger calibration. The total power dissipation of the system is very low, below 25 mW/channel.
The reliability of the whole system is presently under investigation regarding ageing and radiation tolerance both critical in a hardly accessible environment as CMS detector: tests performed still now on FEB (accelerated ageing and irradiation with neutrons, ions and gamma rays) show good MTBF characteristics and immunity to latch-up events.
 

Id: 77
Corresponding Author: Jonathan FULCHER
Experiment: CMS
Sub-system: Tracker
Topic: Electronics for Tracker

Single Event Upset Studies on the APV25 Readout Chip

J Fulcher, G Hall, E Noah , M Raymond
Imperial College, London, UK

D Bisello, G. Marseguerra, J Wyss
Padova University, Padova, Italy

M French, L Jones, Q Morrissey, A Neviani
Rutherford Appleton Laboratory, Didcot, UK

Abstract

The microstrip tracker for the CMS experiment at the LHC will be read out using APV25 chips.  During high luminosity running of the LHC the tracker will be exposed to particle fluxes up to 107 cm2 s-1.  This high rate of particles introduces a concern that the APV25 could occasionally suffer from Single Event Upset (SEU).  In order to evaluate the expected upset rate under these circumstances the APV25 was run under controlled conditions in a heavy ion beam.  This enabled the measurement of the SEU upset cross-section, and hence a prediction of the upset rate in CMS.  The upset cross-section for a range of particle LETs (Linear Energy Transfer) was measured and the referred threshold energy and saturated cross-section was evaluated.  These data are then used to predict the upset rate for the APV25 in the CMS tracker.

Summary

During the research and design phases of the APV chip, much care has been taken to assure a high degree of total dose radiation tolerance.  The chips have been fabricated in AVLSI-RA Bulk CMOS, DMILL and deep sub-micron processes.  Extensive testing has been carried out on representative test structures from various processing runs, and the degree of radiation tolerance of these processes has been thoroughly investigated, including SEU measurements of the APV6 (the bulk CMOS version). However, the susceptibility of the APV25 to SEU was not known.  The new version of the APV has been fabricated in a 0.25 mm technology, in which the SEU effect is not yet well measured, so a full understanding of the implications of these single event effects is imperative.  An investigation of the behavior of the APV25 in a heavy ion beam makes it possible to extrapolate from the data to predict the SEU rate in the final system.

SEU is a non-destructive phenomenon, which affects the digital memory registers that store logic states within the APV.  It manifests itself as a soft error appearing in a device and is caused by the deposition of charge by an ionizing particle.  In the APV25 soft errors could cause a variety of undesirable effects, some of which would result in temporary malfunction and possible loss of data.  In the event of such errors the APV can be reset and after a latency ( ~ 3 ms ), normal operation would resume.  It is clear that an understanding of the upset rate will help in the determination of the required reset rate of the tracker, therefore it is important that this rate be evaluated to enable considered design of this part of the tracker system.

In order to calculate the predicted upset rate in the final system an evaluation of the SEU sensitivity was carried out by placing the APV25 in a beam of heavy ions, at the TANDEM accelerator at INFN Legnaro in Italy and measuring the SEU cross-section.  This was achieved by measuring the beam fluence and LET value along with the number of chip upsets caused by the heavy ion beam during a particular time interval.  Cross-section curves, in the case of heavy ion irradiation, typically represent the cross-section of the device as a function of Linear Energy Transfer (LET) of the bombarding ions.  These curves generally have a threshold LET, where upsets begin to appear, and a saturating cross-section for high values of LET.  These two defining features of the device behavior can then be used to make a prediction of the upset rate for other forms of radiation.  For the CMS tracker, the required calculations are complicated since the particles are typically of single charge and therefore only cause large enough ionization by virtue of nuclear interactions with silicon lattice sites.  Calculations of the cross-section through simulations of such interactions have been performed and form the basis of the SEU predictions in the CMS tracker

The results of the test have provided good measurements giving a threshold LET of around 13 MeV.cm2.mg-1, and the SEU cross-section for important elements of the circuit. Predictions have been made of SEU rates in CMS, of less than 10-6 upsets.chip-1.s-1, which allow detailed planning of the CMS system operation.

Id: 78
Corresponding Author: Jean-Pierre Mendiburu
Experiment: CMS
Sub-system: Calorimetry
Topic: Electronics for Calorimeter

An electronic calibration for the readout chain of the ECAL-CMS

Youngwook Baek, Daniel Boget, Pierre Zves Davis, Jean Ditta, Nadia Fouque, Jean Pierre Mendiburu
LAPP Annecy-le-Vieux

Abstract :

A calibration system has been developped in 0.8 µ DMILL technology for ECAL-CMS. It consists of several logic and analogic chips that have been funded, and tested in lab and in irradiation beams.

Summary :

We present the status of the electronic calibration designed for the read-out chain of the CMS-ECAL.

In the LAPP (Annecy, France), we have developed several chips in DMILL 0.8 µ technology to integrate the functionalities dedicated to the electronic calibration. A control chip, receives the signals from outside opto-couplers, it de-serializes and transfers this information to a decoding logical circuit. This one recognizes calibration orders, generates a word  and transfers it to a DAC to select an amplitude or set a trigger to the injector.

The injector builds pulses that have  an amplitude proportional to the order given to the DAC and an exponential decaying shape, identical to the APD’s one. The characteristics of each chip have been measured at LAPP on a chain based on a PC through a Labview program  and VME specific elements. Each chip has been tested under irradiation in running conditions at least up to 1014 neutrons/cm2 and 400 krads in gammas  and proved to be hard at least to 10 years of full LHC luminosity.

Id: 83
Corresponding Author: Geoff HALL
Experiment: CMS
Sub-system: Tracker
Topic: Electronics for Tracker

The CMS Tracker APV25 0.25µm CMOS readout chip

M. J. French, L. L. Jones, Q. Morrissey, A. Neviani, R. Turchetta
Rutherford Appleton Laboratory, Didcot, OXON, OX11 0QX, United Kingdom

J. Fulcher, G. Hall, E. Noah, M. Raymond
Blackett Laboratory, Imperial College, London SW7 2AZ, United Kingdom

K. Kloukinas, P. Moreira
CERN, 1211 Geneva 23, Switzerland

N. Bacchetta, D. Bisello, G. Marseguerra, J. Wyss
University of Padova, Italy

Abstract:

The APV25 is the 128-channel readout chip for silicon microstrips in the CMS tracker. It is the first major chip for a high energy physics experiment to exploit a modern commercial 0.25µm CMOS technology. Experimental characterisation of the circuit shows full functionality and excellent performance both in pre- and post-irradiation conditions. The measured noise is significantly reduced compared to earlier APV versions. Automated on-wafer testing of many chips has demonstrated a very high yield. A summary of the design and detailed results from measurements will be presented. Operation of the chip in conjunction with other CMS system components will be described.

Summary:

The chip has dimensions 8mm x 7.15mm. Each APV25 channel contains a preamplifier and shaper, with a 50ns peaking time, followed by a 192 deep memory into which samples are written at 40MHz. Locations of data awaiting readout are flagged so they are not overwritten. Following a trigger, three samples from the memory are processed with the APSP deconvolution filter, which re-filters the data with a shorter time constant.
The APV25 contains system features including programmable on-chip analogue bias networks, a remotely controllable internal test pulse generation system and a slow control interface which allows programmable setting of bias currents and voltages in the amplifier and shaper, choice of operation mode, calibration, latency adjustment and error reporting, etc.
The preamplifier is a charge sensitive amplifier with a PMOS input transistor of dimensions 2000µm/0.36µm and current of 400µA. It consumes 0.9mW and is the dominant contribution to the total APV25 power budget of 2.3mW/channel. The power supplies are +1.25 and –1.25V. A switchable unity gain inverter is used to allow signals of either polarity to be measured. The shaper is an effective CR-RC filter with shaping adjustable over a limited range. The total front end gain of the amplifier is approximately 100mV/MIP (25000e).
The pipeline is a 128 by 192 array of switched capacitor cells. Each cell comprises two transistors, to perform the read or write operation, and a storage capacitor. The pipeline is read out by the APSP processor which is an amplifier with a switched capacitor network in the feedback loop. The ratios of capacitors define the weights used by the deconvolution algorithm.
A 128:1 multiplexer drives the analogue output from the chip which emerges at 20MS/s following a digital header sequence in a current form. Data from two APV25 chips are interleaved at the APVMUX chip to arrive at the final transmission speed of 40MS/s.

Results:

The chip functionality was complete after a single design iteration. However, it was noted that the resistance of the input lines to the amplifier could be reduced so the noise performance of the final version, which is now in fabrication, will improve further on this.
The peak mode pulse shape is a very good approximation to ideal 50ns CR-RC pulse shaping. The deconvolution mode data accurately achieve the short pulse shape expected for single bunch crossing timing. Irradiations have taken place using x-rays, 10MeV electrons and reactor neutrons to fluence levels greatly in excess of those expected in CMS; all results are excellent. Very minor changes in performance are seen after high ionising doses.
Automatic wafer testing of each chip will identify “known good die” which will be cut from wafers and assembled onto hybrids. A system is already in operation  and the time required to test each APV die on the wafer is less than 2 minutes. Measurements from several hundred chips show yields of  perfect chips of more than 80%, which is excellent for a complex circuit of 57mm2 in size.
Single Event Upset studies have been carried out in heavy ion beams which will be presented in an accompanying paper to the workshop.

Id: 87
Corresponding Author: Etam NOAH
Experiment: CMS
Sub-system: Tracker
Topic: Electronics for Trackers

Total Dose irradiation of a 0.25µm process

M. J. French
Rutherford Appleton Laboratory, Didcot, OXON, OX11 0QX, United Kingdom

I. Dindoyal, G. Hall, E. Noah, M. Raymond
Blackett Laboratory, Imperial College, London SW7 2AZ, United Kingdom

D. Bisello
University of Padova, Italy
 

Abstract

A commercial 0.25µm process will be used for various electronic components of the CMS tracker, one of these being the APV25 readout chip for silicon microstrips. Irradiating and measuring individual transistors is important in assessing the radiation tolerance of the chip. Transistors from two different foundries owned by the same company were irradiated up to doses of 50Mrad(SiO2) with a 10keV X-ray source. Threshold voltage shifts of up to 140mV were observed whilst noise measurements showed very little degradation in the white noise region after irradiation and annealing. Detailed results of both static characteristics and noise will be presented.

Summary

High speed, low noise and low power consumption are some of the requirements placed on electronics for the LHC. The electronic components also have to survive the harsh radiation environment with ionising doses of up to 10Mrad being reached in the inner tracker regions of CMS. The readout system for the silicon microstrips adopted by the CMS collaboration is based on the APV chip series. The APV25 is the latest chip in the series and is designed in a commercial 0.25µm CMOS technology. This paper reports on a total dose radiation study of transistors manufactured by two different foundries (referred to as foundry A and foundry B) employing the same 0.25µm process. The static characteristics and noise of the transistors were measured before and after irradiation and annealing.

The largest noise contribution in the APV25 comes from the input PMOS transistor of the preamplifier, which has dimensions of 2000µm/0.36µm. All the PMOS transistors measured had a width of 2000µm and lengths varying from 0.24µm to 0.64µm. The NMOS transistor measured had dimensions of 2000µm/0.36µm.

An X-ray source was used to irradiate the transistors in steps up to a dose of 50Mrad(SiO2), with measurements being made after each step. The X-ray tungsten tube was operated at 50kV. This, along with the aluminium filtering ensured that 80% of the dose was delivered by radiation around 10keV. During irradiation, the transistors were biased so as to be under normal operating conditions. During the annealing stage, the transistors were biased and kept at a temperature of 100oC.

Measurements of the static characteristics showed threshold voltage shifts of up to 140mV for PMOS transistors. Some annealing of these transistors reduced the shifts to around 90mV. In addition, there was no significant degradation of the sub-threshold slope or the transconductance. The shift in the threshold voltage for the NMOS transistor was 15mV after 50Mrad(SiO2), increasing to 75mV after annealing. There was some small degradation of the transconductance and the sub-threshold slope for the NMOS transistor.  The threshold voltage shifts observed would not significantly affect the functionality of a chip such as the APV25.

Noise measurements were made with the transistors in saturation and in the moderate to strong inversion region with a drain current of 500µA and a drain voltage of 0.5V. A comparison of the noise before and after irradiation for PMOS transistors shows very little difference for frequencies above 1MHz (higher than the corner noise frequency), which is the region of interest.

After a total dose of 50Mrad(SiO2), 5 times higher than the predicted total dose in the CMS tracker, all the transistors from both foundries were fully functional, showing very small changes in static characteristics and no significant increase in noise levels. The results suggest a small difference in oxide quality between the two fabrication runs.

Id: 88
Corresponding Author: John COUGHLAN
Experiment: CMS
Sub-system: Tracker
Topic: Electronics for Trackers

Design of the Front-End Driver card for CMS Silicon Microstrip Tracker Readout.

S.A. Baird, K.W. Bell, J.A. Coughlan, R. Halsall, W.J. Haynes, I.R. Tomalin
CLRC Rutherford Appleton Laboratory, Oxon, UK.
E. Corrin
Imperial College, London, UK.

Abstract:

The CMS silicon microstrip tracker has the order of 10 million readout channels. The tracking readout system employs several hundred off-detector Front-End Driver (FED) cards to digitise, sparsify and buffer analogue data arriving via optical links from on-detector pipeline chips (APVs). This paper describes the baseline design of the Front-End Driver card which is implemented as a 96 ADC channel (10 bits) 9U VME board. At typical LHC operating conditions the total input data rate per FED after digitisation of over 3 GBytes/s must be substantially reduced. The required digital data processing is highly parallel and heavily pipelined and is carried out in several large FPGAs. The process of FPGA digital design using VHDL and design optimisaton with board level simulation together with the tools employed are discussed.

Summary:

The CMS silicon microstrip tracker has the order of 10 million readout channels. The tracking readout system employs several hundred off-detector Front-End Driver (FED) cards to digitise, sparsify and buffer analogue data arriving via optical links from on-detector pipeline chips (APVs). The Front-End Driver card is currently in the final stages of design. The baseline FED design is implemented as a 96 ADC channel (10 bits) 9U VME board. Each ADC channel receives multiplexed data from 2 front end analogue pipelined ASICs (APVs). The essential features of data processing are as follows. In the first stage the amplitude modulated optical data is converted to electrical levels by opto-receiver packages containing PIN diodes and a custom amplifier ASIC. The analogue data is digitised at 40 MHz by 10 bit commercial ADCs.
The data from each ADC is then processed in its own independent digital pipelined processing logic. Following the recognition of the header accompanying each data frame from the APV, pedestals are removed and the common mode is calculated and subtracted. The APV strip data must then be re-ordered before applying the cluster finding algorithm. The final sparsified data from all ADC channels is then collected, formatted and buffered locally before transferal to the next layer of the CMS data acquisition system.
The entire digital logic is programmed in VHDL and implemented in several large FPGAs. The latest tools are being employed in the FPGA design. Extensive use has being made of simulation tools to optimise the level of internal data buffering. Monte-Carlo generated tracker data is also used to test possible hit and cluster finding FPGA algorithms. Hardware-software co-simulation allows the software for the control and monitoring of the FED to be developed and tested in parallel with the hardware design. The importance of adopting standards in the design process to facilitate testing and maintenance of such a large system is discussed.
The FED is designed to operate at the CMS level 1 trigger rate of 100 kHz. The resulting input rate per FED after digitisation of over 3 GByte/s will be reduced to an average output rate per FED of approximately 150 MByte/s at the expected average hit rates in the tracker. The baseline design will have a total of 500 FEDs in the tracker readout system and will provide over 70% of the final CMS data volume.

Id: 93
Corresponding Author: Gueorgui ANTCHEV
Experiment: CMS
Sub-system: DAQ
Topic: Optoelectronics and data transfer systems

Readout Unit Prototype for CMS DAQ System

G. Antchev, E. Cano, S. Cittolin, S. Erhan,
B. Faure, D.Gigi, J. Gutleber , C.Jacobs, F. Meijers,
E. Meschi, A. Ninane, L.Orsini, L. Pollet, A.Racz,
D. Samyn, N. Sinanis, W. Schleifer, P. Sphicas

CERN Div.EP/CMD, Switzerland

Abstract :

In the CMS data acquisition system, the Readout Unit (RU) is a major element of the Readout Column and it is placed between Front-end Devices (FED) and Builder Data Network (BDN). The RU is intelligent fast buffer for intermediate storage of data before transferring between the levels of the DAQ system. Readout Unit prototype is developed to achieve the CMS DAQ requirement for data input bandwidth of 400MB/sec and data output bandwidth of 400 MB/sec. The new RU prototype based on reconfigurable hardware structure and high-speed standard busses is presented in this paper.

Summary :

The RU prototype is implemented in two physical units called Readout Unit Input Output (RUIO) and Readout Unit Memory (RUM) interconnect together via fast PCI busses. Those are long size 64bit at 33/66MHz PCI boards. The RUM unit contains dual-port memory (up to 512 Mbytes on DIMM's) where data events will be stored. The memory can be accessed through two on-board PCI busses. Those busses can receive an extension board to accept one additional PMC/PCI board. The RUIO unit is also connected to them. A Memory Management Unit (MMU) on board operates with memory as a hard disk. A third PCI bus on RUM and RUIO is used to configure and control the units. This allows both units to be plugged in a standard PCI bus environment as (PC, SUN Stations or Macintosh). The interconnection between the busses is done by on-board 4 way PCI Bridge.

In this sense the three PCI busses can work independently from each other at the maximum bandwidth of 533MB/s each. Using FPGA's components latest generation provide possibilities to implement different functions in RU.

Id: 95
Corresponding Author: Eric CANO
Experiment: CMS
Sub-system: DAQ
Topic: Detector Control And Real Time Systems

Software developments for the Readout Unit Prototypes for CMS DAQ System

M.Bellato (INFN Sezione di Padova)
G.Antchev, E.Cano, S. Cittolin, B.Faure, D.Gigi, J.Gutleber, C.Jacobs, F. Meijers, E. Meschi, L.Orsini,
L. Pollet, A.Racz,D. Samyn, N. Sinanis,W. Schleifer, P. Sphicas (CERN)
A.Ninane (Université Catholique de Louvain)

Abstract :

In the CMS data acquisition system, the readout unit is a fast buffering device for short term storage of event fragments. It interfaces front end devices and builder data network.

The current Readout Unit prototypes are based on two homegrown hardware boards, the Readout Unit Memory (RUM) and the Readout Unit I/O (RUIO). These boards are equipped with an IOP. Several OS environments for this processor are developed. The software running on those boards will have to setup and control the input and output processes. Fast IOP to host communications are experimented. A software test environment is specifically designed for test and validation of the complex memory management of the RUM.

Summary :

The RUIO and RUM prototypes both include a PLX IOP480, with a PowerPC core. Thoses IOPs are connected to the host (any PCI workstation) through a PCI bridge. The PCI bridge also allows communication from IOP to IOP.

The IOP processor needed an operating system. Therefore, VxWorks is ported to the RUIO environment, and to the RUM environment. An experimental Linux port is also in progress.

The purpose of the IOP is to setup and control the RUM board, and the link elements. In prototyping environments, the IOP on RUIO or RUM can simulate part of the data acquisition system, in order to test individual parts of the RU or event builder. In this context, the host can have a role, and therefore, fast communication between host and RUIO is tested thanks to the hardware FIFOs in the PCI part of the RUIO.

The test software is based on a generic pci board framework. This framework provides cross plateform development capabilities, with very little porting effort from plateform to plateform. An additional GUI is developed with Labview. The supported plateforms are, from now, MacOS, Linux and VxWorks

Id: 102
Corresponding Author: Danek KOTLINSKI
Experiment: CMS
Sub-system: Tracker
Topic: Electronics for Trackers

The CMS Pixel Detector

Danek Kotlinski, Paul Scherrer Institute, Switzerland

Abstract:

In the presentation the readout architecture of the CMS pixel detector will be discussed.
The data rate and volume expected at the full LHC luminosity and it's implication on the readout chip will be presented. The overall pixel readout system  and the integration with the CMS data acquisition system will be emphasized.
The first pixel detector layer will be placed at 4cm from the beam in a very high radiation environment. Some aspects of the radiation hardness and its impact on the readout design will be discussed.

Summary:

The CMS pixel detector consists of 3 barrel layers located at 4.3 cm, 7.2 cm and 11.0 cm. The barrel is 52 cm long and is supplemented by two endcap disks on each side. The detector is equipped with sensor modules which are 1.6 cm wide and 6.4 cm long. Each detector module is readout by 16 chips. The readout chips are organized in 26 double-columns, each consisting of 106 square 150*150 microns pixels.

When pixels in a double-column are hit by a charged particle the time-stamp of the event is recorded in the column time-stamp buffer. For all hit pixels the pixel address and the analog signal are transferred to the column periphery. There the data waits for the arrival of the 1st level trigger. Groups of 8 or 16 readout chips are connected to one readout link. In order to synchronize the data transmission a "token-bit" manager chip is used. This chip, through a token mechanism, controls the access of each double-column to the readout link. It formats data packets by sending a packet header and trailer and also monitors the system and signals errors. Pixel hits confirmed by the trigger are send through the readout link to the readout electronics (FEDs) 100 m away from the detector. For each hit pixel 6 analog signals are send, they include the analog amplitude, chip identification and column and row pixel addresses, with the digital information being analog coded. About 1000 links are used to readout the whole CMS pixel detector.

The clock, trigger and the reset/synchronization signals are send down to the detector from the control modules (FECs). A separate set of links is used for this purpose. These are also used to download various setup parameters (e.g. pixel thresholds) and to communicate slow control messages.

The finite space available on the readout and token-bit chips means that the size of all data buffers must be optimized for the LHC requirements. Extensive Monte Carlo simulations have been performed to select the right buffer sizes and to estimate the data losses. With out present design the total data loss at full LHC luminosity for the pixel barrel detector at 7 cm is about 4%. This includes the data lost due to buffer overflows in the readout chip, lost data packets due to too high trigger burst rates and the 2-clock column dead time. More details will be given during the presentation.

The pixel readout is integrated with the CMS DAQ through the readout unit (RU). The RU module has a detector specific part (FED) with 48 readout links connected to it. About 26 of such units are needed for the whole pixel detector. At the LHC high luminosity about 10000 pixels are hit every 25ns. The average pixel events size is about 50 Kbytes, which at 100 kHz trigger rate corresponds to a 5 Gbytes/s data flow.

The pixel hits can be used in a standalone pixel track finding and primary vertex finding algorithms. Such algorithms could be used in the CMS 2nd and 3rd level triggers.

Id: 105
Corresponding Author: Markus FRENCH
Experiment: CMS
Sub-system: Tracker
Topic: Electronics for Trackers

APVMUX, An analogue multiplexing chip for the CMS Tracker
M. French, P. Murray, L. Jone (Rutherford Appleton Laboratory)
M. Raymond (Imperial College)

Abstract:

A chip for multiplexing pairs of APV25 chip outputs onto differential analogue cable has been designed. The chip includes SEU tolerant logic to detect and control the APV signal phasing and termination resistors required by the APV25 chip. The termination impedance and switching phase are programmable by I2C and bond control respectively. The design and implementation is outlined and test results presented.

Summary:

The APV25 chip designed for the CMS tracker provides a differential analogue current signal. This must be terminated to ground and in order to match the numbers of optical inks in CMS, pairs of APV25s are required to multiplex onto individual fibres. The fibres are driven by separate driver chips that require a differential voltage input.
The purpose of the APVMUX chip is to provide this function. Each multiplexer chip can take up to eight APV25 signal inputs (the maximum for any hybrid in CMS) and multiplex them in pairs onto four differential lines that communicate to a separate laser driver module where the fibres are driven.
The phasing of the multiplexing function is derived from the trigger and 40MHz clock that drive the APV25s, this ensures the multiplexer is synchronous with the APV25 output signal. The relative phase is also controlled by two bond pads that either reverse the APV order or adjust the skew by half a clock cycle, this ensures that optimal timing may be achieved on the FE modules.
The termination impedance present in the MUX chips is programmable via the I2C interface on the APV module and allows trimming to control the voltage conversion for link gain optimisation.
In order to facilitate efficient use of the APV25 wafers the size of the MUX die was constrained in one dimension. This led to the inclusion of the PLL circuit, formerly presented as a separate chip, included in the same die. This reduced the number of different chips on each FE hybrid by integrating both functions together.
The design was submitted on the April2000 wafer run and results showing pairs of APV25 chips multiplexed together and the function of the phase and polarity control will also be presented.

Id: 106
Corresponding Author: Nancy MARINELLI
Experiment: CMS
Sub-system: Tracker
Topic: Electronics for Trackers

The CMS Tracker  front-end and  control electronics in an LHC like beam test

W.Beaumont(b), M.Bozzo(f), C.Civinini(e), J.Coughlan(k), F.Drouhin(h), P.Figueiredo(d), L.Fiore(c), A.Giassi(j), K.Gill (d), J.Gutleber(d), G.Hall(g), L.Latronico(f), C.Ljuslin(d), M.Loreti(i), C.Maazouzi(l), S.Marchioro(d), N.Marinelli(g), C. Paillard(d), T.Parthipan(k), P.Siegrist(d), L.Silvestris(c,d), I.Tomalin(k), A.Tsirou(d), P.G.Verdini(j), P.Walsham(g),
B.Wittmer(a), A.Zghiche(l,d), F.Vasey (d)

(a) RWTH, I. Physikalisches Institut, Aachen, Germany,
(b) Universitaire Instelling Antwerpen, Antwerpen, Belgium
(c) INFN, Sezione di Bari, Bari,  Italy
(d) CERN, 1211 Geneva 23, Switzerland
(e) INFN, Sezione di Firenze, Firenze,  Italy
(f) INFN, Sezione di Genova, Genova,  Italy
(g) Blackett Laboratory, Imperial College, London SW7 2AZ, United Kingdom
(h) Universite de l’Haute Alsace, Mulhouse, France
(i) INFN, Sezione di Padova, Padova,  Italy
(j) INFN, Sezione di Pisa, Pisa,  Italy
(k) Rutherford Appleton Laboratory, Didcot, OXON, OX11 0QX, United Kingdom
(l) Institut de Recherches Subatomiques, IN2PS-CNRS Strasbourg, France

Abstract:

A complete prototype of the CMS tracker read-out and control system has been built using components that are very close to the final design. The system is based on analogue amplifier and pipeline memory chips (APV), analogue optical links transmitting at 40Mbps and a VME digitisation and data handling board (FED), supplemented by a control system which sets and monitors the components of the system. This system has been successfully operated for the first time under LHC like beam conditions,  in a 25ns structured beam provided by the SPS at CERN,  mainly aiming  to  test the synchronisation of the system and pile-up effects in a high trigger rate environment.
Preliminary results are presented in this paper

Summary:

The CMS Tracker front-end electronics has been designed to operate at the 40MHz LHC machine frequency with low noise level while ensuring adequate bunch-crossing identification.  A first test in an LHC like beam has been successfully performed in order to check the system synchronisation and the effect on the data quality due to the high trigger rate
Four silicon strip detectors of the "standard" Tracker design have been put on the beam line equipped with a total  of 16 APV6 chips. Readout data have been transmitted through analogue optical link to the DAQ interface (two FED-PMC  8 channels ADC)  and data have then been stored in a high performance  objectivity database system
The fast control information (clock and trigger) provided by the global Timing, Trigger and Command system have been distributed by digital optical fibres from the VME mezzanine Front End Controller (FEC).  Local PLL ASICs  (one per silicone module)  allowed the  recovering of the encoded clock and trigger information and the synchronization of all modules, compensating for different cable lengths.  A local ring of controller  ASICs (CCUs) have been used to handle the transitions from high speed optical link to a number of industry standard I2C buses allowing the  decoding of slow control information hence the setting, control and monitoring of  all the parameters required for the proper operation of the front-end ASICs and their ancillary electronics.

Results
The synchronization of  12 APV6  out of  16 was successfully achieved by tuning the PLLs delays.  Synchronicity can be checked by looking online at the address of  the APV pipeline memory cells where data are stored in. When the APVs are synchronous they all show the same address. Four APV6, sitting on different detectors, turned out to be out of synchronization probably because of glitches on the clock or on the trigger line. Further details will  be available after completing the on-going offline data analysis.
Detailed measurements on each analogue optical link have been performed in order to determine the correct settings for the gain on the laser drivers.
The behavior of the APV6  with  triggers close in time has been checked. The APV6 has been designed to accept two consecutive triggers separated by at least two empty 25 ns buckets, commonly labeled "1001" trigger type, ie the minimal separation in time of two consecutive acceptable triggers is 75 ns. Such sequences, which have been measured to be present in 16% of the beam triggers, were selected, using fast logic triggering algorithm, and successfully read and recorded. The readout response of the APV6 to 2 consecutive triggers 75ns apart has been obtained and measured. This is the first observation of this very satisfactory response of electronic channels under the severe LHC like timing conditions.