LEB2000_Atlas

ATLAS EXPERIMENT

ID:6
Corresponding Author: Yasuo ARAI
Experiment: ATLAS
Sub-system: Muon
Topic: Electronics For Muon Detectors

Development of a 24 ch TDC LSI for the ATLAS Muon Detector

Yasuo Arai, KEK, National High Energy Accelerator Research Organization, Institute of Particle and Nuclear Studies
and
T. Emura, Tokyo University of Agriculture and Technology

Abstract:

To get a high resolution around 300 ps, an asymmetric ring oscillator and a PLL circuit are used. All the I/O signals which are active during measurement has LVDS interfaces. A JTAG interface is used for boundary scan and internal register setup. All the memory and control bits has parity bits so that a SEU can be detected. Radiation tolerance for Gamma-ray and Neutron are also reported.

Summary:

A TDC LSI for the ATLAS precision muon tracker (MDT) has been developed. A prototype chip(AMT-1) was processed in a 0.3 um CMOS Gate-Array technology. It contains full functionality of the final TDC; 24 input channels, 256 words level 1 buffer, 8 words trigger FIFO and 64 words readout FIFO. It also include trigger matching circuit which selects data according to the trigger ID. The selected data are transferred through 40~80 Mbps serial line with DS-Link protocol.

To get a high resolution around 300 ps, an asymmetric ring oscillator and a Phase Locked Loop(PLL) circuit are used. These time critical parts were routed in manually. All the input and output signals which are active during measurement has LVDS interfaces. A JTAG interface is used for boundary scan and internal register setup. All the memory and control bits has parity bits so that a Single Event Upset can be detected.

The chip is packaged in a 144 pins plastic QFP with 0.5 mm pin pitch and about 107k gates are used. Gamma-ray irradiation and Neutron exposure are planned. Performance of the TDC chip and radiation tolerance will be reported.

ID:8
Corresponding Author: Tony WEIDBERG
Experiment: ATLAS
Sub-system: Tracker
Topic: Optoelectronics And Data Transfer Systems

Single Event Upset Studies for the ATLAS SCT and Pixel Optical Links

D.G.Charlton, J.D.Dowell, R.J.Homer, P.Jovanovic, G.Mahout, H.R.Shaylor, J.A.Wilson
School of Physics and Astronomy, University of Birmingham,UK

R.L. Wastie, A.R. Weidberg
Physics Department, Oxford University, U.K.

J.K. troska, D.J. White
Rutherford Appleton Laboratory, U.K.

I-M Gregor
Physics Department, Wuppertal University, Germany.

Abstract:

The readout of the ATLAS SCT and Pixel detectors will use optical links. The radiation hardness of all the components has been extensively studied but this paper discusses the operation of these links in simulated LHC radiation environments. Nuclear interactions can deposit large amounts of energy in electronic components which can cause Single Event Upsets (SEU). The SEU rates have been measured with MIPS from a beta source, low energy neutrons, pions and protons at PSI. The dominant source of SEU effects is from energy deposition in the active region of the PIN diodes.

Summary:

Optical links will be used in the ATLAS SCT and Pixel detectors to transmit data from the detector modules to the off-detector electronics and to distribute the Timing, Trigger and Control (TTC) data from the counting room to the front-end electronics. The radiation hardness of the individual components has been extensively studied. The optical links have been shown to operate at very low Bit Error Rates (BER) in the laboratory. This paper reports on studies of the operation of the links in simulated LHC radiation environments. The flux of pions during high luminosity operation at the LHC will be up to 4 10**7/cm**2/s for the detector closest to the beam line (the Pixel B-layer). The particle flux falls of rapidly with perpendicular distance from the beam line. Nuclear interactions in the detector can deposit sufficient energy in the active volumes of the opto-electronics and electronics to cause bit errors. The rates of Single Event Upsets (SEU) have been studied by measuring the BER while irradiating the opto-electronics with different particles. Minimum Ionising Particles (MIPs) were produced with a Sr90 source, neutrons from deuteron stripping and (d,t) reactions. The SEU rates have also been measured with pions and protons in the momentum range 215 MeV/c to 465 MeV/c at the Paul Scherrer Institute. This momentum range is very similar to that of pions produced in minimum bias interactions at the LHC.

MIPs do not cause any measurable SEU. A significant rate of SEU has been measured for neutrons, pions and protons. The dominant source of this SEU is due to nuclear interactions in the active volume of the PIN diode which deposits sufficient energy to trigger the DORIC4 receiver ASIC. Hence from the point of view of the DORIC4, the energy deposition is effectively a genuine signal. The effective threshold can therefore be raised by increasing the amplitude of the TTC optical signal generated in the counting room. The rate of SEU is found to decrease strongly as the effective threshold is increased. The ASICs have been designed to avoid destructive effects and no evidence for such effects has been found.

The measured SEU data are compared with theoretical calculations. These calculations are then used to extrapolate the measured BER to LHC conditions and hence predict the bit error rate during LHC operation. Even for the highest particle fluxes at the B layer of the Pixel detector, the BER can be reduced to a level below 10**-9, by using a sufficiently large amplitude optical signal for the TTC data. Therefore the problem can be reduced to a rate which is acceptable for ATLAS operation.

ID: 9
Corresponding Author: Gilles MAHOUT
Experiment: ATLAS
Sub-system: Tracker
Topic: Optoelectronics And Data Transfer Systems

Radiation Hard Optical Links for the ATLAS SCT and Pixel Detectors

D. Charlton, J.D.Dowell, R.J.Homer, P. Jovanovic, G.Mahout, H.R.Shaylor, J.A.Wilson.
School of Physics and Astronomy, University of Birmingham, Birmingham, B15 2TT, UK

I.M. Gregor, R.Wastie, A.R. Weidberg
Physics Department, University of Oxford, Keble Road, Oxford, OX1 3RH, UK.

S.Galagedera, M.C.Morrissey, J.Troska, D.J.White.
CLRC Rutherford Appleton Laboratory, Chilton, Didcot, Oxon, OX11 0QX, UK.

A.Rudge
CERN, Geneva, Switzerland.

M.L.Chu, S.C.Lee, P.K.Teng
Institute of Physics, Academia Sinica, Taipei, Taiwan 11529, Republic of China.

Abstract:

A radiation hard optical readout system designed for the ATLAS Semi-conductor Tracker (SCT) is described. Two independent versions of the front-end optical package housing two VCSEL emitters and an epitaxial Si PIN photodiode have been irradiated with neutron fluences over 1015 n.cm-2, the level encountered in the ATLAS pixel detector. Environmental tests have been performed down to -20o C. Extensive radiation and lifetime tests have also been carried out on the opto-electronic components and the front-end VCSEL driver and timing/control ASICs. Bit error rate and cross-talk measurements using irradiated devices show that the system easily meets the performance specification.

Summary:

The ATLAS SemiConductor Tracker (SCT) and Pixel detectors will be read out using optical links. The Timing, Trigger and Control (TTC) data are delivered from the off-detector electronics to each detector module by a single optical fibre using an epitaxial Si PIN photodiode as the receiver. The binary data are transmitted using VCSELs operating at 850 nm. Two VCSELs and one photodiode are mounted in a low mass, non-magnetic optical package on each module. Several packaging technologies have been studied and so far two different packages have been successfully developed using different methods for optically coupling the optical fibres to the VCSELs and photodiodes. Radiation hard ASICs have been developed to drive the VCSELs (VDC chip) and to recover the 40 MHz clock and the TTC data from the photodiode signals (DORIC4 chip). Each component, as well as the complete packages, has been extensively tested after irradiation with neutrons and gammas.

Mitel VCSELs have been tested and show good recovery after a short annealing period following irradiation with 2.9x1015 1 MeV equivalent neutrons.cm-2, which is a typical fluence in the pixel detector after 10 years of LHC operation. The total light output before irradiation is typically 1 mW for a current of 10 mA. The main effect of neutron irradiation is to shift the threshold current upwards substantially, which reduces to about 1 mA after annealing, without changing the slope of the light output vs current. The PIN photodiodes (manufactured by Centronic) show a drop in responsitivity of about 30% to 0.3 A/W after irradiation up to 1015 n.cm-2 and an increase in dark current to 60 nA at room temperature which is negligible. Both VCSELs and photodiodes have undergone accelerated ageing tests at elevated temperatures after irradiation. They show excellent reliability (no failure) after several hundred equivalent LHC years corresponding to a failure rate of < 1% after 10 years of LHC operation.

The VDC and DORIC4 use bipolar npn transistors in the AMS 0.8 micron BiCMOS technology. Samples have been exposed to 2.5 1014 1 MeV equivalent neutrons/cm2 and 115 kGy of gamma radiation. All chips work correctly after irradiation. The circuits are designed to work with transistor beta values as low as 10. Measurements of beta before and after irradiation are presented. Accelerated ageing tests have been carried out at 100oC on a sample of DORIC4s under operational conditions without any failure, corresponding to a 0.3% upper limit (90% c.l.) on the failure rate after 10 years of LHC operation.

Bit error rate and cross talk measurements have been carried out using packaged devices after irradiation. The performance is well within specification (< 10-9 BER for an optical power of 200 muW). Single event upset measurements using neutrons and ionising radiation have also been performed and are reported in a separate paper.

The conclusions are that a successful readout scheme has been developed for the SCT, and that the optoelectronic components and packaging are also adequate for the higher radiation levels in the pixel detector.

ID:13
Corresponding Author: Pavol STRIZENEC
Experiment: ATLAS
Sub-system: Calorimetry
Topic: Electronics for Calorimeters

Calibration of the ATLAS Hadronic End-Cap Calorimeter

H. Brettel, W.D. Cwienk, L. Kurchaninov, H. Oberlack, P. Schacht
(Max-Plank-Institute for Physics, Munich, Germany)

A. Jusko, P. Strizenec
(Institute of Experimental Physics SAS, Kosice, Slovakia)

On behalf of the ATLAS HEC Collaboration

Abstract:

The calibration chain of the ATLAS HEC is described. A model based on detailed studies of all individual parts is presented.

The characteristics of the steering and data taking system for both the test-beam runs and for the acceptance tests of the HEC modules is summarized.

The calibration and signal reconstruction procedure is developed and results of the test-beam data are presented.

ID: 19
Corresponding Author: Kazumi HASUKO
Experiment: ATLAS
Sub-system: Trigger
Topic: Trigger Electronics

First-Level End-Cap Muon Trigger System for ATLAS

K. Hasuko, T. Kobayashi, T. Niki, D. Toya, Y. Katori (University of Tokyo)
O. Sasaki, M. Ikeno, T.K. Ohska (High Energy Accelerator Research Organization KEK),
C. Fukunaga, H. Kano (Tokyo Metropolitan University),
H. Sakamoto, S. Nishida (Kyoto University),
H. Kurashige and R. Ichimiya (Kobe University)

Abstract:

We present the first-level end-cap muon trigger system for ATLAS. The system has the main tasks which are to identify bunch crossings and to make trigger decisions for high transverse-momentum muon candidates. It is being developed under requirements on trigger electronics: e.g. trigger rate, latency, acceptable number of tracks, etc. Such the requirements, trigger scheme, and overview of trigger logic are shown in this presentation. Details of the logic are given in the following presentation.

Summary:

The first-level (LVL1) muon trigger system consists of synchronous pipelined processors running at the bunch-crossing rate of 40 MHz. Its main tasks are to identify bunch crossings and to make trigger decisions for high transverse-momentum (Pt) muon candidates. It has to be operated with Pt threshold in the rage of 6-35 GeV. The trigger rate is required to be limited up to 100 kHz at a high luminosity. The latency of trigger decisions at front-end electronics is required to be less than 2.5 us, including 0.5 us for contingency.

High-Pt muons are identified from Resistive Plate Chambers (RPCs) and Thin Gap Chambers (TGCs) in the barrel and end-caps respectively. The ATLAS has air-core toroidal magnets creating magnetic fields for muon detection. A muon is bent in the fields and the information on its charge and momentum is extracted from the deviation of the bending path with respect to the non-bending projection toward the interaction point.

The TGCs with totally about 320K channels are arranged in seven layers (one triplet and two doublets) in each side. A hit signal is read out in r and phi independently. A muon track is identified by requiring coincidence criteria for hits in layers. A track satisfying 3-out-of-4 coincidence in both doublets is labeled as a low-Pt track. If the track also satisfies 2-out-of-3 (1-out-of-2) in a triplet for r (phi), it is labeled as a high-Pt track. The end-cap region is divided into totally 144 trigger sectors. The two highest-Pt tracks should be selected in each trigger sector.

This trigger system consists of four parts, which we call Patch Panel (PP), Low Pt (or Slave Board; SLB), High Pt and Sector Logic (SL).

At first, PPs receive digitized TGC signals to identify the bunch crossing, adjust signal timing and construct trigger segmentation. SLBs follow the PPs to perform coincidence operations for low-Pt tracks.

The results of SLBs are sent to High-Pt Boards (HPBs) to be combined for high-Pt tracks for r and phi separately. The information on r and phi is sent to SL performing r-phi coincidence and final track selection. The results are sent to the rest of LVL1 trigger system to be combined with the information on barrel muon and calorimeter systems. A trigger signal is finally generated and distributed to the front-end readout electronics. All chamber hits are read out from pipeline-clocked buffers on SLBs with event information.

This system also has functionalities to set up various parameters on detectors and trigger logic. These functionalities are totally controlled from outside.

The core logics in PP, SLB and HPB are implemented with full-custom ASICs. SL is implemented with FPGAs so that the r-phi coincidence is fully programmable. This provides the required range of Pt thresholds. The total latency of the end-cap system is less than 2 us, satisfying the requirement.

We will explain the system overview in this presentation and details of the ASICs are given in the other. These two presentations will complete the explanation of the muon end-cap trigger system.

ID: 21
Corresponding Author: Per Gunnar GÄLLNÖ
Experiment: ATLAS
Sub-system: Trigger
Topic: Trigger Electronics

Timing, Trigger and Control distribution and dead-time control in ATLAS

Abstract:

The RD12 TTC system is the backbone for the timing, trigger and control distribution in ATLAS. The last developments of TTC modules as well as their use in ATLAS will be presented.

The strategy for the dead-time control of the experiment will also be presented.

Summary:

The ATLAS readout elements, such as the front-end electronics, the readout drivers (ROD) and possibly the readout buffers (ROB), need the bunch crossing signal (BC) and the level-1 accept signal (L1A). The Timing, Trigger and Control (TTC) system allows the timing and trigger signals to be distributed to the readout electronics elements. The timing signals comprise the LHC clock (BC) and the synchronisation signals (BCR, ECR). The trigger signals include the L1A, test and calibration triggers. The TTC allows the timing of these signals to be adjusted.

The ATLAS TTC system is based on the optical fan-out system developed within the framework of RD12 which allows signals to be distributed from one source to up to 1024 destinations. The system is partitionable and subdetectors can be running with the central ATLAS timing and trigger signals, or independently, with their specific timing and trigger signals. The TTC system receives the LHC 40 MHz clock (BC) and the ORBIT signal from the LHC, the L1A signal from the central trigger processor (CTP), and commands and data from either the CTP or subdetector-specific electronics. A proper encoding allows this information to be transmitted on a single optical link which is fanned out to up to 1024 destinations. At the receiving end, an ASIC decodes the incoming signal and makes available the BC clock, the L1A signal, the ECR and BCR signals, the L1ID and BCID and the user commands and data. Provision is made to adjust the timing of all the signals. The way the TTC system will be used in different subdetectors depends on the specific requirements of each of them. Most of the sub-systems will use more than one partition to allow concurrent running of different parts of the detector in different trigger modes during commissioning or calibration periods.

In ATLAS, the TTC system will be used in different ways:

- In normal running, each TTC partition receives its clock from the LHC and the L1A from the CTP. The BCR is derived from the LHC ORBIT signal. After each L1A, an 8-bit trigger type is forwarded to the destinations as well as (optionally) a 24-bit event ID. The trigger type is formed in the CTP and contains information on what gave rise to an L1A, while the 24-bit event ID is formed in the TTC VME interface (TTCvi). The TTC system can also transmit specific subdetector data and commands without introducing dead time, e.g. test pulses when there are no bunches (LHC gap), front-end parameters (e.g. delay values).

- During commissioning and for test and calibration runs, triggers can be injected locally in each TTC partition.

The ATLAS front-end electronics and readout systems contain many levels of buffering. Information may be lost at any of a number stages of the readout chain if buffers become saturated. Different strategies can be adopted to handle this situation, the two extreme ones being:

- introduce deadtime to avoid uncontrolled information loss;

- accept information loss and build a readout system able to accept incomplete events and possible loss of synchronization.

The first of these strategies has been chosen and it has been decided to introduce deadtime in the Central Trigger Processor in order to:

- easily control and monitor the deadtime of the experiment;

- have a relatively simple and safe readout system relying on the presence of data for every event;

- simplify the front-end electronics systems by imposing an upper limit on the event rate and a minimum time between consecutive events.

ID: 22
Corresponding Author: Hiroyuki KANO
Experiment: ATLAS
Sub-system: Trigger
Topic: Trigger Electronics

Custom chips developed for the trigger/readout system of the ATLAS end-cap muon chambers

H.Kano, C.Fukunaga, Tokyo Metropolitan University,
M.Ikeno, O.Sasaki, T.K.Ohska, KEK (National Organization for high energy accelerator physics),
R.Ichimiya, H.Kurashige, Kobe University,
S.Nishida, H.Sakamoto, Kyoto University,
K.Hasuko, Y.Katori, T.Kobayashi, T.Niki, and D.Toya, University of Tokyo

Abstract:

Three custom ASICs are now being developed for the trigger/readout system of the ATLAS end-cap muon chambers. Each chip is the master component in three out of four subparts of the system. Beside the standard circuitry as an ATLAS subsystem, several implementations have been devised in each chip, which are required from various physical and boundary conditions as an electronics system for the end-cap muon chambers. We discuss the implementation of the level-1 muon identification logic as well as these customarily developed data handling technology

Summary:

The trigger/data acquisition (TDAQ) system for the muon end-cap chamber of ATLAS (TGC) is required to be divided into several partitions. This requirement comes from the structure and characteristics of the TGC as a sub-detector of ATLAS. The partitions are installed just on either the detector surface or top of it. All signals are passed through these partitions of so-called Patch-panel, Low-Pt and Hi-Pt in turn to an upper stream.

We have developed three custom ASICs, each of which contains almost all functionality of a partition. By making ASICs for these partitions, we intended to simplify and lighten the overall electronics system. In this system TGC output is used to produce the ATLAS level-1 muon trigger, we must make a trigger generation logic with minimum latency. Thus we also expect to shorten the latency by implementing the trigger logic into ASICs.

The TGC trigger logic uses signals from three sets of total seven TGC layers, which are called triplet, middle-doublet and pivot-doublet from inside to outside. We identify a muon track with these three layers. In the first step we try to find muon with hit signals of both doublets of the pivot and middle. If a signal sequence passes this check, it is labeled as a low-Pt muon track. A check for Hi-Pt is followed using signals of the triplet and the Low-Pt output.

The TGC signals are input at first to the patch panel in which the patch panel ASIC converts the level from LVDS to TTL and adjusts the signal timing in sub-nanosecond precision with a variable delay accomplished by a DLL circuit. The chip also makes synchronization of the TGC signal with own bunch crossing signal.

TGC signals processed in the patch panel are relayed to the Low-Pt. The hit information of signals for relevant TGC layers are made matching with a coincidence matrix embedded in the ASIC. This ASIC contains also the readout system of the TGC data beside the trigger logic that consists of the standard pipeline and derandomizer buffer.

The Hi-Pt system accepts trigger signals produced by the Low-Pt and makes own muon identification with more-or-less the same algorithm with the Low-Pt ASICs. Each Hi-Pt chip recognizes up to six high-Pt tracks. Contrary to the Low-Pt system, the output signal of the Hi-Pt must be transferred over 80 m for further processes. The transfer is done with an optical link with the high speed serial transmission protocol (G-link). In order to reduce data volume to be transferred, we applied a zero suppression mechanism and send the information of max. two highest Pt tracks for the next trigger processing. In principle we can achieve this with two consecutive primary encoding logic clock by clock. Instead we have developed a quick method to select two highest track within a clock. This encoding logic contributes to both reduction of latency and data volume on the G-link.

In the presentation we explain in detail the functionality and necessity of each chip from physical volume, space and latency point of view. The evaluation of the chips must be presented through analyses of both simulation and actual measurement.

Id: 24
Corresponding Auhtor: Tony GILLMAN
Experiment: ATLAS
Sub-system: Trigger
Topic: Trigger Electronics

Study of LVDS Serial Links for the ATLAS Level-1 Calorimeter Trigger

G.Anagnostou, P.Bright-Thomas, J.Garvey, R.Staley, W.Stokes, S.Talbot, P.Watkins, A.Watson
University of Birmingham, Birmingham, UK

R.Achenbach, P.Hanke, D.Husmann, M.Keller, E.-E.Kluge, J.Krause, K.Mahboubi, R.Megele, K.Meier, U.Pfeiffer, V.Schatz, K.Schmitt, C.Schumacher, B.Stelzer, O.Stelzer, P.Stock, E.Ulses
University of Heidelberg, Heidelberg, Germany

B.Bauss, K.Jakobs, U.Schaefer, J.Thomas
University of Mainz, Mainz, Germany

E.Eisenhandler, W.R.Gibson, M.P.J.Landon
Queen Mary and Westfield College, London, UK

B.M.Barnett, I.P.Brawn, J.Edwards, C.N.P.Gee, A.R.Gillman, R.Hatley, K.Jayananda, V.J.O.Perera, A.A.Shah, T.P.Shah
Rutherford Appleton Laboratory, Chilton, Didcot, UK

C.Bohm, M.Engstrom, S.Hellman, S.B.Silverstein
University of Stockholm, Stockholm, Sweden

Abstract:

This paper presents an evaluation of the proposed LVDS serial data transmission scheme for the ATLAS level-1 calorimeter trigger. Approximately 7000 high-bandwidth links are required to carry data into the level-1 processors from the preprocessor crates. National Semiconductor's Bus LVDS serialiser/deserialiser chipsets offer low power consumption at low cost and synchronous data transmission with minimal latency. Test systems have been built to measure real-time bit error rates using pseudo-random binary sequences. Results show that acceptable error rates better than 10^-13 per link can be achieved through compact cable connector assemblies over distances up to 20m.

Summary:

The ATLAS level-1 calorimeter trigger requires approximately 7000 high-bandwidth serial links to transfer data from the preprocessor into the algorithmic processor systems. Each processor module must receive data in excess of 4 Gbyte/s over these links, with minimal latency and a bit error rate (BER) better than 10^-10 for each link.

It was originally proposed to use HP G-link chipsets, which have performed well in tests, but do lead to a very high power density on the processor modules. This high power dissipation would require serious attention to module and crate cooling. LVDS links offer much lower power consumption, and the National Bus LVDS serialiser/deserialiser chipsets DS92LV1021/DSLV1210 etc. are easily interfaced to the trigger system while transmitting data synchronously with minimal latency.

Three separate test systems were produced. These involved up to eight channels in parallel, and measured BERs over electrical links using various cable types with lengths from 10m to 20m. Test systems were designed to transmit and check pseudo-random and repetitive data patterns in real-time in order to achieve the statistics required for measurements of very low BERs.

Several types of cable and connector were also evaluated for use within the ATLAS environment. The processor modules will share data via a high-speed backplane, and the LVDS links will be connected through this backplane in order to allow easy installation and replacement of modules. Compact cable assemblies are needed because of the high channel count per module: up to 96 LVDS channels per module are required and each 9U processor module requires up to 830 backplane pins.

The final installation within ATLAS requires inter-crate links over distances of 10m to 15m, and a low BER is crucial for these links in order to minimise false triggers. For minimum latency, only error detection, not correction, is possible. To minimise the error rates, the cable assemblies being considered require some form of equalisation for the attenuation at high frequencies, as the raw data rate on each link is 480 Mbit/s. Both active and passive pre-compensation techniques at the transmitter have been investigated. BERs better than 10^-13 per link have been achieved with cable lengths from 10m to 20m even with simple and straightforward L-R equalisation.

Experience showed that use of these parts was not straightforward, operating as they are at the limit of their specified data rate. The causes of power supply noise must be kept to the minimum, and board layout is critical. In particular, it is important to ensure that the transmitter clock has a low level of jitter. However the problems encountered have been understood and solutions found.

In conclusion, the LVDS links form a viable scheme for transfer of large volumes of data, having the advantages of low latency, low power and low cost. They also offer high-density connectivity, which is essential for compact cable plant. Prototype processors are now being designed that will incorporate a large number of such links.

Id: 28
Corresponding Author: Ralf SPIWOKS
Experiment: ATLAS
Sub-system: Trigger
Topic: Trigger Electronics

A Demonstrator for the ATLAS Level-1 Muon Trigger Interface to the Central Trigger Processor

A. Corre, N. Ellis, P. Farthouat, Y. Hasegawa, G. Schuler, C. Schwick, R. Spiwoks
CERN

Abstract:

The Level-1 Muon Trigger Interface (MUCTPI) to the Central Trigger Processor (CTP) receives trigger information from the detector- specific logic of the muon trigger. This information contains up to two muon-track candidates per sector. The MUCTPI combines the information of all sectors and calculates total multiplicity values for each of six pT thresholds. It avoids double counting of single muons by taking into account that some of the trigger sectors overlap. The MUCTPI sends the multiplicity values to the CTP which takes the final Level-1 decision. For every Level-1 Accept the MUCTPI sends region-of-interest information to the Level-2 trigger and event data to the data acquisition system. A demonstrator of the MUCTPI has been built which has the performance of the final system but uses a simplified algorithm for calculating the overlap. The functionality and the performance of the demonstrator are presented.

Id: 29
Corresponding Author: Ralf SPIWOKS
Experiment: ATLAS
Sub-system: Trigger
Topic: Trigger Electronics

The Trigger Menu Handler for the ATLAS Level-1 Central Trigger Processor

N. Ellis, P. Farthouat, G. Schuler, R. Spiwoks
CERN

Abstract:

The role of the Central Trigger Processor (CTP) in the ATLAS Level-1 trigger is to combine information from the calorimeter and muon trigger processors, as well as from other sources, e.g. calibration triggers, and to make the final Level-1 decision. The information sent to the CTP consists of multiplicity values for a variety of pT thresholds, and of flags for ET thresholds. The algorithm used by the CTP to combine the different trigger inputs allows events to be selected on the basis of menus. Different trigger menus for different run conditions have to be considered. In order to provide sufficient flexibility and to fulfil the required low latency, the CTP will be implemented with look-up tables and programmable logic devices. The trigger menu handler is the tool that translates the human-readable trigger menu into the configuration files necessary for the hardware, stores several prepared configurations and down-loads them into the hardware on request. An automatic compiler for the trigger menu and a prototype of the trigger menu handler have been implemented.

Id: 33
Corresponding Author: Greg HALLEWELL
Experiment: ATLAS
Sub-system: Tracker
Topic: Grounding Shielding Cooling And Alignment

Development of Fluorocarbon Evaporative Cooling Recirculators and Controls for the ATLAS Pixel and Semiconductor Tracking Detectors

C. Bayer (Wuppertal), M. Bosteels (CERN), P. Bonneau (CERN), H. Burckhart (CERN), D. Cragg (RAL), R. English (RAL), G. Hallewell (RAL/CPPM), B. Hallgren (CERN), S. Kersten (Wuppertal), P. Kind (Wuppertal), K. Langedrag (Oslo), S. Lindsay (Melbourne), M. Merkel (CERN), S. Stapnes (Oslo), J. Thadome (Wuppertal), V. Vacek (CERN/Czech Technical University, Prague)

Abstract:

We report on the development of evaporative fluorocarbon cooling recirculators and their control systems for the ATLAS Pixel and Semiconductor Tracking (SCT) detectors. A prototype circulator uses a hermetic, oil-less compressor and C3F8 refrigerant. The mass flow rate to each circuit is individually tuned via feedback according to the circuit load variation, using dome-loaded pressure regulators in the liquid supply lines piloted with analog compressed air from DAC-driven voltage to pressure ("V2P") converters. Evaporated C3F8 exits each circuit through an analog air-piloted back-pressure regulator, which sets the circuit operating temperature. A hard-wired thermal interlock system automatically cuts power to individual silicon modules should their temperature exceed safe values.

All elements of the circulator and control system have been implemented in prototype form. Temperature, pressure and flow measurement in the circulation system uses standard ATLAS CanBus LMB ("Local Monitor Box") DAQ and CanBus interfaced DACs in a large (300 + channel) multi-drop Can network administered through a BridgeView user interface. Prototype 16 channel interlock modules have been tested.

The performance of the circulator under steady state, partial-load, and transient conditions is discussed and future developments are outlined.

Summary:

We report on the development of evaporative fluorocarbon cooling recirculators and their control systems for the ATLAS Pixel and Semiconductor Tracking (SCT) detectors.

The front-end electronics and silicon substrates of these detectors collectively dissipate around 50kW of heat, which must be removed from the ATLAS inner detector cavity through around 400 separate evaporative cooling circuits. For an operational lifetime of around 10 years in the high radiation field close to the LHC beams, the silicon substrates of these detectors must operate at a temperature below ~ -6 C, with only short warm-up periods each year for maintenance. Evaporative cooling is chosen since it offers minimal extra material in the tracker sensitive volume.

Following our studies of evaporatively-cooled Pixel and SCT thermo-structures (LEB 99), we have addressed the development of evaporative fluorocarbon recirculators and their control systems for use with per-fluoro-n-propane (C3F8) at an evaporation temperature (pressure) of ~-25 C (~1.7 bar abs).

A prototype circulator is centered around a hermetic, oil-less piston compressor operating at an aspiration pressure of ~ 1 bar abs and an output pressure of ~ 10 bar abs. Aspiration pressure is regulated via PID variation of the compressor motor speed from zero to 100%, based on the sensed pressure in an input buffer tank. High pressure C3F8 vapor is condensed and passed to the detectors in liquid form, with optional pre-cooling to a temperature of ~ -15 C.

Coolant liquid will be split into around 400 circuits in racks on the ATLAS service platforms. The mass flow rate to each circuit will be individually tuned via feedback according to the circuit load variation, using pressure regulators in the liquid supply lines. These regulators will operate in an inaccessible, high radiation, magnetic field environment, and will be dome-loaded, using analog compressed air delivered from DAC-driven voltage to pressure ("V2P") converters.

Evaporated C3F8 will exit each circuit through an analog air-piloted dome-loaded back-pressure regulator, which will determine the boiling pressure, and hence the operating temperature. Such individual temperature control is impossible in a parallel flow liquid cooling system.

A hard-wired thermal interlock system will automatically cut power to individual silicon modules should their temperature exceed safe values for any reason.

The performance of the circulator and the temperature distribution on powered silicon modules under steady state, partial-load, interlock-trip, start-up and shutdown conditions will be discussed. Finally, aspects of a full-scale demonstrator with ~ 25 cooling circuits and 6kW cooling capacity, currently undergoing commissioning, will be outlined.

Id: 35
Corresponding Author: Martin DENTAN
Experiment: ATLAS
Sub-system: General Interest
Topic: R/m Field Tolerant Electronics

Overview of the ATLAS Policy on Radiation Tolerant Electronics

Martin Dentan, CERN & CEA-DAPNIA
Philippe Farthouat, CERN

Abstract:

ATLAS Sub-systems will integer a very large quantity and variety of electronics boards which will be submitted to radiations ranging from few krads and few 1E10 n/cm2 to few 10 Mrads and few 1E14 n/cm2, and to energetic particles capable of producing SEE (Single Event Effects). ATLAS Technical Coordination has developed in collaboration with the Sub-systems a new policy on radiation tolerant electronics. It provides guidelines for the pre-selection and for the qualification of all the commercial electronics components that will be used in ATLAS, in order to make sure they will resist to the foreseen radiation constraints. This paper summarises the main guidelines given in the ATLAS Policy on Radiation Tolerant Electronics, and the benefits resulting from this policy.

Summary:

The first goal of ATLAS Policy on Radiation Tolerant Electronics is the general safety of the ATLAS materials and of the persons working on the experiment. Therefore, all the components or systems on which radiation effects can cause fire or induce high and long term radioactivity levels are not allowed.

The second goal of this policy is to help ATLAS Sub-systems to build electronics complying with the level of radiation tolerance which is necessary for their system. This level must be determined by the Sub-systems. It represents the minimum doses and fluences which must be tolerated by the electronics, and the maximum rate of soft, hard or destructive Single Event Effects (SEE) acceptable for the electronics. This level of reliability must be maintained during the 10 years of operation of the experiment. This can be obtained by qualifying ASICs developed with a radiation-hard technology that complies with the radiation tolerance required for 10 years of operation, or by selecting and qualifying standard electronics components (COTS) that comply with the radiation tolerance required for 10 years of operation, or by selecting less radiation tolerant COTS and making sure that it will be possible to replace them if necessary after their expected lifetime.

The third goal of this policy is to help Sub-systems to build electronics within the foreseen schedule. Therefore, it includes a strategy for pre-selection, qualification and purchase of components which is built with the aim of reducing procurement risks.

Id: 37
Corresponding Author: Bertrand LAFORGE
Experiment: ATLAS
Sub-system: Calorimetry
Topic: Electronics For Calorimeters

Implementation of a Serial Protocol for the Liquid Argon Atlas Calorimeter (SPAC)

F.Hubaut, B.Laforge, O.Le Dortz, D.Martin, Ph. Schwemling
LPNHE Paris

Abstract:

The Serial Protocol for the Atlas Calorimeter (SPAC) has been designed to provide the loading and reading of all parameters of the front-end boards of the ATLAS Liquid Argon Calorimeter.

This single master / multiple slaves serial protocol is designed to be transmitted optically and electrically, at up to 10 Mbits/s, and enables broadcast or individual transfers from the master to one or a set of slaves.

Some test results about the SPAC performance and its implementation within the ATLAS framework will be presented.

Summary:

The Serial Protocol for the Atlas Calorimeter (SPAC) has been designed to provide the loading and reading of all parameters of the front-end boards of the ATLAS Liquid Argon Calorimeter.

One SPAC network, controlling one front-end crate, includes one master module in the counting room and slave ASICs, made in DMILL technology and housed on each front-end board. The slaves integrate a I2C master interface and a parallel interface to be exploited by the boards.

Some test results about the SPAC performance and its implementation within the ATLAS framework will be presented.

Id: 40
Corresponding Author: Cornelius SCHUMACHER
Experiment: ATLAS
Sub-system: Trigger
Topic: Trigger Electronics

HDMC: An object-oriented approach to hardware diagnostics

V.Schatz, C.Schumacher University of Heidelberg, Heidelberg, Germany
M.P.J.Landon Queen Mary and Westfield College, London, UK

Abstract:

A software package has been developed, which provides direct access to hardware components for testing, diagnostics or monitoring purposes. It provides a library of C++ classes for hardware access and a corresponding graphical user interface. Special care has been taken to make this package convenient to use, flexible and extensible. The software has been successfully used in development of components for the pre-processor system of the ATLAS level-1 calorimeter trigger, but it could be useful for any system requiring direct diagnostic access to VME based hardware.

Summary:

Developing electronics involves a fair amount of testing, where direct access to hardware via a computer is required. In addition to low-level test tools like oscilloscopes or logic analysers higher level diagnostic facilties are essential for more complex tests. This includes software to access the developed hardware in an extensive and easy-to-use way to perform diagnostics and monitoring of individual or complete groups of components. Similar functionality is required for later integration in extended hardware and software frameworks.

The presented software package, called HDMC (Hardware Diagnostics, Monitoring and Control), addresses these needs. It provides a library of components for accessing hardware objects like registers, memories or FPGAs on VME modules or within devices not directly accessible to VME, but located on a VME module. It's also possible to access a VME bus via a network connection in a client/server configuration. A graphical user interface based on this library provides hardware access without requiring special knowledge about software development. The library can also be used for more direct access based on compiled or scripting programming languages for testing or integration into other software environments.

HDMC is implemented as a set of C++ classes, representing hardware components in a common framework. This is used to provide common ways to access similar components, to transmit data between components and to handle them in a uniform way. A simple and clean interface for direct hardware access is provided as well as a more abstract one for access through a graphical user interface. Register descriptions are loaded from human-readable configuration files in such a way that a lot of hardware development can be made without the necessity to recompile the software.

The graphical user interface allows construction, manipulation and access to VME modules and other components in a convenient and uniform way. Access to hardware configurations can be built using the interface and changed at run-time. There is also a plot and histogram component and facilities to present special views of hardware configurations like modules and crates.

HDMC supports a variety of UNIX platforms like Linux, Solaris and HP-UX, For VME access several VME single-board computer are supported, running Linux or LynxOS. Platform support could be extended to Windows without major rewrite and addition of other bus systems like CompactPCI is possible without change in the remaining framework or components.

For development of HDMC an open-source process is used. Source code and documentation is publicly available in the internet and it is open for contributions of any interested party.

The software package has proven to be a useful and reliable tool for diagnosing hardware. It has been used for the pre-processor system of the ATLAS level-1 calorimeter system, whose current development activities are based on a flexible VME test system, but other systems in need for a software tool for hardware diagnostic could also benefit from the HDMC software.

Id: 44
Corresponding Author: Julie PRAST
Experiment: ATLAS
Sub-system: Calorimetry
Topic: Electronics For Calorimeters

THE ATLAS LIQUID ARGON CALORIMETERS READ OUT DRIVERS

Julie Prast for the ATLAS Collaboration

Abstract:

The Read Out Driver (ROD) for the Liquid Argon calorimeters front-end electronics of the ATLAS detector is described. Those ROD modules are designed for the ATLAS electromagnetic, hadronic end-cap and forward calorimeters. Each ROD module receives data from two Front-End Boards (FEB). The FEB amplifies, shapes, samples and stores the signal from 128 calorimeters cells at the frequency of the LHC (40 MHz). Then, the data are digitized and sent to the ROD modules for each Level-1 trigger (maximum rate of 100 kHz). These data are transmitted by two 32 bits data optical links. The principal function of the ROD is to reconstruct the precise energy and timing of each cell signal from the time samples. In addition, the ROD checks and histograms the data. The treated data are then sent towards the Read Out Buffers (ROB), according to a defined format, where they are stored.

A demonstrator system consisting of a mother board and several daughter boards Processing Units (PU), is under development. The goal of the demonstrator is to prove the feasibility of the project and serve as an intermediate step towards the construction of the final ROD module for the ATLAS experiment. The design of the prototypes are presented here.

The mother board is a full size 9U VME module able to carry four daughter boards. It allows all the input/output connections with the FEB and ROB, the controls of the board and the VME interface. This board offers maximum modularity and allows the development and testing of different Processing Units (PU). Three PU are being studied. Two are designed with the Texas Instrument TMS320C6202 fixed point DSP, while the other one is designed with the Analog Devices 21160 floating point DSP. These PU present the same overall architecture. The example of the Analog Devices PU will be taken.

Each PU treats data from an half FEB (8 ADC). Each ADC digitizes signals from 8 calorimeters cells. Each channel is composed of five 12-bit samples. These FEB data enter an FPGA at the speed of 40 MHz They are parallelized, parity checked and formatted before being buffered into the internal FIFO of the FPGA. This FIFO is connected to the external memory bus of the DSP. Once the DSP finishes the processing of the event, the results are formatted according to the ROB format and then put into a FIFO. This output FIFO is read by the mother board Output Controller.

The PU also contains a communication port, through which all the control of the board is done. It uses the DSP link ports to communicate with the mother board VME interface. It is also used to send monitoring or debugging information to the local CPU. All the communications between the DSP and its peripheral are done by Direct Memory Access (DMA), thus being transparent for the DSP core.

Results for the different PU will be presented and compared (functioning, performance, DSP algorithm). The first tests have shown that the demonstrator board meets the ATLAS requirements in term of bandwidth and accuracy, although the DSP used are not the next generation of DSP foreseen for the final version of the board.

Id: 45
Corresponding Author: Yoshiaki SHIKAZE
Experiment: ATLAS
Sub-system: General Interest
Topic: Low voltage and high voltage distribution

Performance of a High Voltage Power Supply incorporating a Ceramic Transfomer

Yoshiaki Shikaze(Department of Physics, Faculty of Science, University of Tokyo), Masatosi Imori(ICEPP, University of Tokyo), Hideyuki Fuke(Department of Physics, Faculty of Science, University of Tokyo) Hiroshi Matsumoto(ICEPP, University of Tokyo), Takasi Taniguchi(National Laboratory for High Energy Physics(KEK))

Abstract:

This paper describes the performance of a high-voltage power supply incorporating a ceramic transformer. Since the transformer doesn't include any magnetic material the power supply can be operated under a strong magnetic field. In the article, the efficiency of the power supply is studied against various parameters. It was found that the efficiency reaches more than 50 percent when zero-voltage switching was realized. From a voltage source of 2V, the power supply can supply 3000V at a 21 megohm load. A voltage source of 5V is enough to supply 4000V at the same load.

Summary:

This paper describes the performance of a power supply incorporating a ceramic transformer which uses the piezoelectric effect to generate high voltage. By using the ceramic transformer and a air-core coil, the power supply can produce high voltage under a strong magnetic field. The output high voltage is stabilized by feedback. A feedback loop includes divider resistors, an error amplifier, a voltage controlled oscillator (VCO) and a driver circuit. An output high voltage is produced by a Cockcroft-Walton (CW) circuit. The driver circuit generates a sinusoidal carrier the frequency of which is genertaed by the VCO. The driver circuit drives the transformer, applying the sinusoidal carrier. The amplitude ratio of the transformer has dependence on the frequency, which is utilized by the feedback.

The transformer shows a sharp resonance in the vicinity of 120kHz. From a view point of efficiency, it is favorable to drive the transformer at efficient frequencies ranging from 120kHz to 124kHz. When 3V is supplied to the driver circuit, the power supply produces 1500--3000V at a 21 megohm load with the above efficient range of frequency. The driver circuit includes FETs and the air-core coils. The inductance of the coil and the input capacitance of the transformer composes a oscillation circuit, by which the sinusoidal carrier is produced. The inductace is adjusted so that the frequency of the oscillation can be in the efficient range. So the FETs are switched while the voltage applied to the FETs is zero. The zero-voltage switching of the FET was realized, which contributed to improving the efficiency.

On-resistance of the FET is important for the efficiency. Yet the efficiency depends on characteristics of the FET intricately. Several kinds of FET are tested. For each FET, many plots on the efficiency were drawn against various parameters such as output high voltage, frequency, inductance, and capacitors of CW circuit. The efficiency increases as the frequency moves to the resonant frequency, being saturated at the level of more than 50 percent at the frequency in the efficient range with zero-voltage switching. When the voltage supplied to the driver circuit is 2V, 3V and 4V and output high voltage is 2000V at a load of 21 megohm, the current to the driver circuit is about 200mA,130mA and 110mA, respectively.

The amplitude of the sinusoidal carrier is about three times the input voltage to the driver circuit. The output voltage of the transformer is furthermore multiplied by about six times in the CW circuit. When the voltage to the driver circiut is 1.5V, the maximum output high voltage of the power supply reaches 3000V at a load of 18 megohm. It can be seen that the amplitude ratio of the transformer reaches a hundred at the resonance frequency. So Feeding 5V to the driver circuit is enough to supply 4000V. Hence the power supply could be available for any of Thin Gap Chamber, Monitored Distributed Tube (MDT) and Resisted Plate Chamber (RPC) of ATLAS experiments.

Id: 46
Corresponding Author: Ulrich PFEIFFER
Experiment: ATLAS
Sub-system: Trigger
Topic: Trigger Electronics

The performance of a Pre-Processor Multi-Chip Module for the ATLAS Level-1 Trigger

Abstract:

We have built and tested a mixed signal Multi-Chip Module (MCM) to be used in the Pre-Processor of the ATLAS Level-1 Calorimeter Trigger. The MCM performs high speed digital signal processing on four analogue trigger input signals. Results are transmitted serially at a serial data rate of 800 MBd. Nine chips of different technologies are mounted on a four layer copper substrate. Analogue-to-digital converters and serialiser chips are the major consumers of electrical power on the MCM, which amounts to 7.5 Watts for all dies. Special cut-out areas are used to dissipate heat directly to the copper substrate. In this paper we report on design criteria, chosen MCM technology for substrate and die mounting, experiences with the MCM operation and measurement results.

Summary: The ATLAS experiment requires a highly selective trigger system with optimal efficiency. The event selection at ATLAS will be achieved by a three level trigger system. The first level trigger (Level-1) is a fast pipelined system for the selection of rare physics processes. It achieves a rate reduction from the 40 MHz LHC bunch crossing rate down to the Level-1 accept rate of 75 kHz (100 kHz upgrade). This is done by searching for trigger objects within a total Level-1 trigger latency of 2.0 us. The number of presummed analogue calorimeter signals which are used as input to the Level-1 trigger is about 7200.

Regarding the timing constraints and the large number of analogue signals, the Level-1 trigger needs a hard-wired front-end to perform fast signal processing on all analogue input signals in parallel. This system, which is referred to as Pre-Processor system, provides the input data for the Level-1 trigger algorithms and it performs the readout of data on which the Level-1 trigger has based its decision.

The motivation behind the usage of a Multi-Chip Module (MCM) technology inside the Pre-Processor system is the high number of channels, which must be processed by each Pre-Processor board (64 signals), and the high number of semiconductor devices per printed circuit board. Hence, a MCM technology is essential for the Pre-Processor system to realize a compact system architecture. MCMs represent a technique whereby bare dies and their interconnections are combined inside a single package. The MCM contains both analogue and digital devices. In total it comprises nine dies: two dual FADCs, four Front-End ASICs performing the pre-processing, one multipurpose level conversion ASIC (Finco), and two high speed gigabit transmitter dies from Hewlett Packard (Glink) running at 1.6 GBd.

The design process of the MCM multi-layer structure is based on an industrial available production technique for high density printed circuit boards. This process, called TwinFlex, is characterized by its usage of plasma drilled Micro-Vias for interconnection between layers and its combination of small feature sizes and prices.

One of the most challenging tasks in the MCM design is the thermal management. The increasing of the packaging density and the use of high power dies leads to the exponential nature of component failure rates with temperature. Therefore the dies on the MCM need different thermal resistance from the chip to the case. This difference has been achieved by using a thermal cutout for the gigabit serial transmitter and thermal vias for the FADCs. The total power consumption of the MCM is about 7.5 W.

We will present design criteria, chosen MCM technology for substrate and die mounting and experiences with the MCM operation. System measurements will demonstrate the performance of the Pre-Processor relying on this Multi-Chip Module technology.

Id: 50
Corresponding Author: Martin MANDL
Experiment: ATLAS
Sub-system: Tracker
Topic: Grounding Shielding Cooling And Alignment

Grounding and Shielding of the ATLAS TRT

Martin Mandl for the TRT collaboration

Abstract:

This paper addresses practical considerations for the engineering of the grounding and shielding system of the ATLAS-TRT.

Summary:

A ground system serves three primary functions: personnel safety, equipment and facility protection, and electrical-noise reduction. Defining the potential of each conductive material to be within certain margins achieves safety. A proper signal reference system together with shielding of sensitive as well as noisy parts provide noise reduction. Defining the potential of the conductive structures and building a signal-reference system inside the TRT, can be chosen within two philosophies: either strongly connecting everything together or trying to control the currents which flow in the system. The first one yields the lowest impedance between any two points of the system, but simultaneously allows loops and shield currents to flow inside the system. The second approach allows to break these loops and to ban shield currents from intruding the system through carefully provided low-impedance paths.

Each ATLAS sub detector has to follow "The ATLAS Policy on Grounding and Power Distribution" which gives the following guidelines:

• [...] electrical isolation of all detector systems, [...]

• [...] floating low-voltage power supplies, [...]

• [...] floating high-voltage power supplies, [...]

• [...] data transmission, clock and trigger distribution through optical links
or shielded twisted-pair cables, [...]

• [...] detector located inside a faraday cage. [...]

This negates the first philosophy at an intersystem level, but still allows it inside the sub detector. Only the final system will show all systematic effects which could not be predicted from a small prototype. Implementing provisions for both philosophies allows us to postpone the choice until more experience has been acquired. Therefore a way of realizing both approaches has been defined.

Id: 52
Corresponding Author: Holger SINGPIEL
Experiment: ATLAS
Sub-system: DAQ
Topic: Trigger Electronics

ATLANTIS - a modular, hybrid FPGA/CPU processor for the ATLAS Readout Systems

Christian Hinkelbein - Institute of Computer Science V, University of Mannheim, Germany Andreas Kugel - Institute of Computer Science V, University of Mannheim, Germany Reinhard Maenner - Institute of Computer Science V, University of Mannheim, Germany Matthias Mueller - Institute of Computer Science V, University of Mannheim, Germany Harald Simmler - Institute of Computer Science V, University of Mannheim, Germany Holger Singpiel - Institute of Computer Science V, University of Mannheim, Germany Lorne Levinson - Weizmann Institute of Science, Rehovot, Israel

Abstract:

ATLANTIS realizes a hybrid architecture comprising a standard PC platform plus different FPGA based modules for high performance I/O (AIB) and computing (ACB). CompactPCI provides the basic communication mechanism enhanced by a private bus. The system can be tailored to a specific application by selecting an appropriate combination of modules. Acceleration of computing intensive ATLAS LVL2 trigger tasks has been demonstrated with an ACB based system. The ATLAS RoD and RoB systems profit from the flexible and highly efficient AIB I/O architecture. Various high speed interface modules (S-Link/M-Link) are supported, allowing up to 28 links per CompactPCI crate.

Summary:

This paper introduces the hybrid FPGA/CPU based system ATLANTIS. Its utilization as a prototype system for investigating further ATLAS Readout Systems is described. The basic concept of ATLANTIS is to support flexibility and scalability on different levels. Due to this ATLANTIS is a modular system based on CompactPCI. Dedicated FPGA boards for computing (ACB) and I/O (AIB) plus a private backplane bus (AAB) for a data rate of up to 1 GB/s are part of the system. Programming of the FPGAs is done either with commercial VHDL tools or the C++ based HDL developed at Mannheim University. For a specific application a certain number and combination of ATLANTIS boards form the desired system. For investigating ATLAS Readout Systems one commercial host CPU along with up to 7 AIBs are used within a CompactPCI crate. Every AIB is able to carry up to four mezzanine I/O daughterboards. Two Xilinx VIRTEX(-E) FPGAs control the I/O ports. The nominal capacity of any of the four channels is 264 MB/s. Each AIB is equipped with 16 MByte SRAM controlled by the FPGAs. The two FPGAs of each AIB are connected both to the host CPU via the PCI bus and to every other AIB within one crate using the private bus. In the context of the ATLAS LVL2 trigger ATLANTIS has already shown its versatility and potential based on the ACB modules. Two further, high performance I/O applications in conjunction with the ATLAS Readout Systems utilizing the new AIB modules are presented in this paper: The use as a Readout Driver (RoD) and as a Readout Buffer (Rob Complex) prototype system. Both applications profit from the flexible and highly efficient ATLANTIS I/O architecture. The RoD acts as interface between detector and RoB. AIBs equipped with 2 SLinks/GLinks perform the I/O task with up to 160 MByte/s per link. Format conversion and zero-suppression is done "on the fly" by the FPGAs, prior to transmission. The AAB private bus is used for concentrating event data from different AIBs to one output port. The RoB Complex tasks are similar to the RoD tasks but more complex. Data fragments from a variable number of input links have to be assembled, temporarily stored and transmitted via a network interface upon request. A high speed buffer management is essential for this application and implemented on the AIB boards. The host CPU is used to steer the AIBs and to handle requests from the network. It may also provide additional computing power. To achieve a high density of links up to 4 M-Link interfaces can be used per AIB. Local control of the 4 input channels and collection of fragments per AIB help to decrease the frequency of control messages and data packets which significantly improves PCI bandwidth. Two ATLANTIS systems comprising ACB(s) and AAB modules plus a PC-compatible host CPU are available since autumn 1999. Also 4 M-Link modules are ready for use. Four AIBs are in manufacturing phase and expected to be available in June 2000.

Id: 53
Corresponding Author: Bernard DINKESPILER
Experiment: ATLAS
Sub-system: Calorimetry
Topic: Optoelectronics And Data Transfer Systems

Redundancy or GaAs ? Two different approaches to solve the problem of SEU (Single Event Upset) in a digital optical link optical

From SMU: Ryszard Stroynowski Bernard Dinkespiler Jingbo Ye Shouxuan Xie
From CPPM: Frederic Rethore
From ISN: Marie-Laure Andrieux Laurent Gallin-Martel
From KTH: Mark Pearce Johan Lundqvist Stefan Rydstrom

Abstract:

The fast digital optical links for the ATLAS Liquid Argon Calorimeter must survive in a high radiation environment with a total fluence of 2*1013 neutrons/cm2 and 800 Gy. The links based on Agilent Technologies -former HP- Glink chipset show a total dose radiation resistance to neutrons and gammas that would allow for 10 years of operation in the ATLAS detector. We have observed, however, an unacceptable rate of single event upsets (SEU) due to neutrons interacting in the silicon-based serializer. In order to solve this problem, we have developed two link systems. The first one - Dual-Glink-, is based on the principle of redundancy. Data are sent on two independent links. On the reception side, data are analyzed and error recovery is performed without dead time.

The second solution uses a GaAs serializer/deserializer chipset from TriQuint. This technology is intrinsically radiation hard. We expect a minimal number of SEU's and other radiation related problems. High speed of this chipset -2.5 Gb/s- allows for error recovery.

The design of the link, its performance in the laboratory environment and the results of the radiation tests will be presented for both systems.

Summary:

The ATLAS liquid argon calorimeter digital optical links are based on Agilent Technologies (former HP) Glink chipset. Although they show a total dose radiation resistance to neutrons and gammas that would allow for 10 years of operation in the ATLAS detector, they have an unacceptable rate of single event upsets due to neutrons interacting in the silicon based serializer. We developed a Dual-Glink system, composed of 2 independent links, each one sending the complete data set. On the reception side a smart switch realized in FPGA analyzes in real time the data streams from both links, detects errors and selects the link that is not affected by errors. The probability that an error occurs simultaneously on both links is negligible. The total latency of the switch is 20 clock cycles. This solution is more expensive than a simple link since all the hardware components are doubled.

In an attempt to make a cheaper solution, we also developed a digital optical link solution based on the recently available GaAs multiplexer/demultiplexer chipset TQ8123/8223 from TriQuint. The intrinsic radiation hardness of GaAs technology is expected to minimize the impact of radiation effects and of the single event upsets. Since the ATLAS LAr Calorimeter requires the 32 bit data transfer at 40 MHz, the very high speed of 2.5Gb/s provided by this chipset allows for sending the data twice over a single optical fiber. This permits an online error detection and error correction. The design of the link, its performance in the laboratory environment and the results of the radiation tests will be presented.

Id: 56
Corresponding Author: Piotr MALECKI
Experiment: ATLAS
Sub-system: Tracker
Topic: Electronics For Trackers

Multichannel system of fully isolated HV power supplies for silicon strip detectors

Edward Gornicki (Institute of Nuclear Physics, Cracow, Poland) Stefan Koperny (Faculty of Physics and Nuclear Techniques of UMM, Cracow} Piotr Malecki (Institute of Nuclear Physics, Cracow)

Abstract:

A multichannel system of power supplies providing a bias voltage in the range of 0 - 410 V for silicon micro-strip detectors is presented. All channels are fully isolated allowing for flexible detector segmentation. A wide range of functions including e.g. a programmable current trip limit as well as a ramp-up and rump-down control independent for each channel are also described.

Summary:

The system consists of cards each of which contains several single isolated channels.The system is build in two similar versions. The full VME version for laboratory applications in small centers testing modules of silicon strip detectors. In this version a standard 6U card consists of four independent power supplies. The version for the final detector system of the ATLAS experiment uses standards of VME mechanics but a custom backup plane and crate control. In this version 8 channels are packed on each card.

The system provides digitally controlled stable bias voltage in 0 - 410 V range and a precise measurement of the output current. A maximum load of each channel is 5 mA. A current trip limit can be set independently for every channel in the range from hundreds of nA to the maximum of 5 mA. Another parameter which can be selected individually for each channel is the ramping speed with which the nominal voltage change is to be executed. Ramping speeds can be selected from the range of 10 - 100 V/s.

Single channel functions are controlled by programmable microprocessor which communicates with a programmable card controller via fast serial link. Communication with the crate controller for the VME version uses standard addressing mode. In the final production version this communication is realized with a fast custom parallel link. Mutual reaction times of processors to various conditions like requirement of a new setting, over-current and over-voltage trips etc are well below 1 ms.

Id: 60
Corresponding Author: Kazuaki ANRAKU
Experiment: ATLAS
Sub-system: DAQ
Topic: Detector Control And Real Time Systems

Possibility of SR8000 Supercomputer for ATLAS DAQ Event Building and Event Filtering

ANRAKU, Kazuaki (ICEPP, Univ. of Tokyo), IMORI, Masatosi (ICEPP, Univ. of Tokyo)

Abstract:

We are investigating the possiblity of adapting the SR8000 supercomputer system by Hitachi for ATLAS DAQ event building and event filtering. The SR8000 system is comprised of a number (up to 128) of nodes, each of which has RISC microprocessors sharing a main memory, and of high speed "multi-dimensional" inter-node network. The maximum total processing power amounts to 1024 GFLOPS and a bidirectional transfer rate of the inter-node network is 2 Gbyte/s. An arbitrary number of nodes can have I/O adapters of HIPPI, ATM, Ethernet, and Fast Ethernet. These features seem to be suitable to both the ATLAS DAQ event builder and event filter.

Summary:

The "Supertechnical Server" SR8000 system by Hitachi, Ltd. is a parallel processing computer system comprised of a variable number (up to 128) of nodes, each of which has 64-bit RISC microprocessors sharing a main memory, and of high speed "multi-dimensional" inter-node network. Each node has a maximum processing power of 8 GFLOPS and a maximum main memory of 8 GB, resulting in the maximum total processing power amounts to 1024 GFLOPS. The nodes are connected to each other by three-dimensional "crossbar network" with an unidirectional transfer rate of 1 Gbyte/s and a bidirectional transfer rate of 2 Gbyte/s. A cooperative microprocessors architecture in each node and pseudo-vector processing in each processor, together with the high speed inter-node communication, realize the high performance.

The nodes are classified to three types; supervisory node (SVN) unique to the system and controlling the whole system, I/O node (ION) processing and input/output operating, and processing node (PRN) processing only. Any node except for the SVN can be selected to be an ION or a PRN. IONs and SVN are equipped with I/O adapters to connect to I/O devices and/or outer industrial standard networks; HIPPI, ATM, Fast Ethernet, and Ethernet.

By feeding the detector data fragments from the ReadOut Crates (ROCs) via EventBuilder Interfaces (EBIFs) into the corresponding I/O nodes and exchanging data between the processing nodes, the SR8000 system can possibly work well as an event builder instead of a switching network implemented in the DAQ/EF -1 prototype. In addition to the event building, the maximum total processing power of a single SR8000 system is supposed to well fulfil the estimated minimum required processing power of the event filtering of 10^6 MIPS.

Supposing the SR8000 system to be a promising candidate for the event builder and event filter, we are now investigating the possiblity and feasibility of adapting the SR8000 system for the DAQ system.

Id: 65
Corresponding Author: Christophe de la Taille
Experiment: ATLAS
Sub-system: Calorimetry
Topic: Electronics For Calorimeters

Overview of the ATLAS LAr front-end radiation tolerance

C. de La Taille (LAL Orsay)

Abstract:

The front-end electronics of the ATLAS liquid argon calorimeter must withstand a non-negligible radiation environment (20Gy/yr 5e11N/cm2/yr), in particular when various safety factors (simulation inaccuracies, lots variability or low dose rate effects) are put on top. The design of all the front end elements is now complete and has been tested on module0 on over 2,000 channels. Several key components have been extensively tested to radiation exposure (preamps, shapers, pipelines...) whereas other circuits (mostly digital) are being now migrated into DMILL. The results of these tests will be summarized and the design of the DMILL chips will be presented. The next milestone of the LAr collaboration is to have a final radiation hard complete front-end prototype by mid july.

Id: 67
Corresponding Author: Mitch NEWCOMER
Experiment: ATLAS
Sub-system: Tracker
Topic: Electronics For Trackers

Experience with DMILL technology in the Development of the ASDBLR ASIC

N. Dressnandt, N. Lam, F.M. Newcomer*, R.P. VanBerg, H.H. Williams
University of Pennsylvania, Philadelphia Pa.

Abstract:

An engineering prototype of the ASDBLR ASIC has been fabricated in the rad hard, BICMOS, DMILL process offered by Temic. This ASIC integrates eight channels of high speed low power and low noise straw tube readout on a single substrate. Bi-level signal detection for ionizing tracks and TR photons at rates as high as 20MHz is accomplished utilizing six hundred custom sized components per channel. A previous DMILL prototype showed strong sensitivity to hookup conditions manifested as unexpected harmonics. Steps taken to eliminate these harmonics, including improvement of the device models appear to have been successful. Measured performance of the recent prototype nearly exactly matches SPICE calculations. Results from neutron and proton exposures, beam tests with the companion DTMROC readout chip and plans to include custom devices that have been fabbed for us by TEMIC will be discussed.

Summary:

The ASDBLR ASIC is intended to provide the full signal processing chain, input to tri-level discriminator output for the 430,000 straw ATLAS TRT detector. Measurements of a first version of this ASIC fabricated in a bulk analog bipolar process served to qualify the circuit technique for use in the ATLAS TRT. We have since decided to develop a version in DMILL, a rad hard SOI, BICMOS process recently commercialized by Temic. A six channel ASIC was designed in DMILL and submitted for fabrication in the summer of 1997. Our first tests with packaged chips indicated a sensitivity to hookup which was ultimately traced to on chip crosstalk through the SOI substrate. A more complete discussion can be found in the LEB99 proceedings.

In August 1999 we submitted a revised version of the ASDBLR and it's companion timing and readout ASIC, the DTMROC, for an engineering run. Both chips are fully functional and match well with pre submission simulations. Harmonic oscillation in the ASDBLR specific to the DMILL design was addressed with the following modifications that appear to have successfully resolved the problem: 1) Use of CEA developed shielded input pads. 2) Addition of a differential stage prior to tail cancellation to reduce single ended capacitor driven cross talk to the back substrate. 3) Addition of global substrate grounding rings around all sensitive devices to fix the potential of unused areas of silicon above the SOI substrate. 4) Addition of a small preamp supply R-C filter network on each channel.

The following circuit embellishments were added to improve the general performance: 1) Addition of dynamic current sources on the buffer transistors that drive the baseline restorer to reduce quiescent current. 2) Addition of a fixed 4ns delay in the output of the low level discriminator to align the output of low and high outputs for a clean ternary sum. 3) Programmable tuning of the ion tail cancellation.

Test Devices -

Significant stray, to the substrate underlying the insulator in DMILL devices combined with the relatively high gain and bandwidth required for the ASDBLR amplifier and shaper circuit make it desirable to minimize stray capacitance of on chip devices at the input. Large area devices at the input include, input pads, input protection, and transistors. A shielded input pad designed by a CEA group has been approved for use by TEMIC and was incorporated successfully in the ASDBLR. In December 1998 TEMIC fabbed several custom test structures for us including two types of multi-striped NPN transistors for use as input transistors and an input protection structure consisting of a large number of parallel connected NPN transistors. Multi-striped NPN transistors offer the advantage of lower base resistance and lower stray capacitance for the same collector current density compared to single emitter stripe devices. Expanded geometry single stripe NPNs with collector and base shorted to a supply were used for input protection. In this configuration the collector acts as a shield to the back substrate and is shorted to the base which becomes the anode of the input protection structure. The emitter acts as the cathode and has the desirable benefit of a comparatively low stray capacitance. The reverse bias of this base emitter junction is well controlled under ordinary conditions by the single Vibe drop of the ASDBLR common emitter input configuration.

Test Structure Measurements - Two transistors on the input protection test structure were wired in common emitter configuration to mimic the ASDBLR input and a repetitive pulse was amplified and observed while the input protection was tested by discharging repeatedly a capacitor charged by a variable voltage through 24 ohms at the input. Reliable protection to 1500uJ was provided by this structure.

ASDBLR Measurements - The peaking time appears to be about 15% faster than the desired 7.5ns value while the absolute threshold is within 5% of the SPICE calculated value for both high (TR photon sensitive) and low (tracking) discriminators. The functional yield is ~75% but after applying channel to channel threshold matching requirements the yield is only 35%, about half of that of a design of similar complexity fabbed by us in a bulk process. Resistor matching results reported by the foundry indicate a larger than expected variation which can be responsible for the lower yield. We have carefully examined the circuit and find no other plausible explanation at this time.

Radiation tests - Unbiased ASDBLR's from this run were exposed to 10^14 neutrons/cm^2 at Prospero and no change in performance is observed. On chip resistors were tested and changes were less than 1%. Both multi-stripe and single stripe NPN devices from the test structures were also exposed and found to have a beta of ~60 at a current density of 3.3uA/um of emitter. Pre-rad beta was ~280.

Future Measurements ASDBLR's and their companion chips (DTMROC's) have been exposed under power to 10^14protons/cm^2 at CERN and are awaiting the return of these devices for post rad characterization. Beam tests using prototype modules and a high density readout with ASDBLR and DTMROC ASICS are planned to take place at the H8 beam line at CERN over the summer. Results of these tests should be available for the September LEB meeting.

Id: 69
Corresponding Author: Helio TAKAI
Experiment: ATLAS
Sub-system: Calorimetry
Topic: Radiation and magnetic field tolerant electronics systems

Switching Power Supply Technology for ATLAS LAr Calorimeter

H. Takai and J. Kierstead
(for the ATLAS Liquid Argon collaboration)
Brookhaven National Laboratory

Abstract:

The ATLAS liquid argon calorimeter is designing a switching power supply to be meet the harsh environmental requirements imposed by the location where they will be installed. In addition the design addresses the inaccessibility issue. We will present the design and available tests regarding radiation and magnetic field susceptibility.

The ATLAS liquid argon calorimeter is planning to install power supplies for the front end electronics in the gap region between the tile barrel and tile extended calorimeters. The required power for the overall electronics is approximately 150 kW. This requirement rules out the use of copper cables to bring the power to the crates. In this location the environmental and access issues are such that the design will have to follow very tight specifications. The environmental issues are twofold: magnetic field and nuclear radiation. The radiation in the location of the power supply is a mixture of particles from the tails of Hadronic showers. They include photons, hadrons, and electrons. The expected integrated dose over a period of ten years is of the order of 10 kRad, and the overall flux of 1 MeV equivalent neutrons 1x10^12.cm-2. The flux of neutrons above 1 MeV is estimated to be 5 kHz.cm-2. The magnetic field in the region of the power supplies is estimated to be 50 Gauss. The current maintenance schedule allows access to the volume including the power supplies only once a year, therefore reliability and remote monitoring and control is essential. The final requirement that we have to meet is a very limited space.

With these requirements in mind, we have established a strategy for the development of appropriate power supplies. Currently, we expect to have prototypes ready by the end of year 2000. The plan calls for a radiation tolerant and single event upset resistant power supply with remote operational capabilities. At the heart of the power supply blocks of DC-DC converters will be used. A number of these blocks will be connected in parallel to form an N+1 redundant system. Each block will be monitored during the operation for temperature, fatal failure, over-current, and over-voltage. At the present time two potential manufacturers have been identified, Vicor and Modular Devices Inc. Vicor modules meet the requirements for electronic noise, magnetic field, and limited radiation tolerance but have not been tested for single event effects. The DC-DC converter manufactured by Modular Devices is known to be radiation tolerant but has not been tested for magnetic field or SEE effects. The control circuits are designed to be radiation and SEE tolerant.

In spring 2000 we plan to initiate tests for SEE susceptibility using heavy ion beams, followed by tests using 100 MeV or greater protons. We are particularly concerned with SEB or SEGR in the power mosfets as well as possible latchups in the control logic. We will report on the progress on the development of the power supply. In particular preliminary tests as far as radiation is concerned will be discussed.

Id: 75
Corresponding Author: Peter LICHARD
Experiment: ATLAS
Sub-system: Tracker
Topic: Electronics for Tracker

The new ATLAS TRT read-out system

Peter Lichard CERN-EP

Abstract:

The ATLAS TRT detector is very demanding in terms of electronics performance because of the high occupancy of the detector. A new version of the full read-out system, including two new ASICs and the new back-end modules, has been designed and tested successfully at 40 MHz clock rate and high trigger rate on a detector prototype. A description of this system will be given, as well as test results and plan for future scaling.

Summary:

The ATLAS TRT is a gaseous detector consisting of 420000 straws covering the barrel and end cap regions. It aims at providing tracking information with a good resolution and electron identification. The large occupancy of the detector requires special care on the analogue signal processing to cancel the ion tail signal, data compression and use of high speed digital links. The drift time measurement performed on the front-end electronics is indispensable for good tracking resolution.
A new prototype of the read-out chain working at 40 MHz has been developed, constructed and tested. The on-detector electronics consists of an 8 channel analogue front end chip containing a fast preamplifier, a tail cancellation circuitry, base line restorer and two discriminators, followed by a 16 channel read-out chips including a 3ns time to digital converter, the level1 trigger pipeline and the readout protocol to extract the data corresponding to a level 1 trigger signal. The off-detector electronics consists of a new prototype of a scaled down ROD module, which concentrates the data from 832 channels, format the data and apply the zero suppression scheme and make the data available to the data acquisition system through S-LINK; and the new version of a TTC module with a new protocol for controlling the front-end electronics implemented.
A complete description of the different components of this chain is given, as well as test beam results.
A description of a new prototypes of TTC and ROD modules is presented, including data compression schemes and TTC protocol.

Id: 76
Corresponding Author : Wladyslaw DABROWSKI
Experiment : ATLAS
Sub-system : TRACK
Topic: Electronics for trackers

Progress in development of the readout chip for the ATLAS Semiconductor Tracker

W. Dabrowski, Faculty of Physics and Nuclear Techniques, UMM, Krakow, Poland
F. Anghinolfi, CERN, Geneva, Switzerland
A. Clark, University of Geneva, Switzerland
T. Dubbs, SCIPP, UCSC Santa Cruz, CA, USA
L. Eklund, CERN, Geneva, Switzerland
M. French, Rutherford Appleton Laboratory, Didcot, UK
W. Gannon, Rutherford Appleton Laboratory, Didcot, UK
A. Grillo, SCIPP, UCSC Santa Cruz, CA, USA
P. Jarron, CERN, Geneva, Switzerland
J. Kaplon, CERN, Geneva, Switzerland,
J. Kudlaty, MPI, Munich, Germany
C. Lacasta, IFIC, Valencia, Spain
D. LaMarra, University of Geneva, Switzerland
D. Macina, University of Geneva, Switzerland
I. Mandic, Jezef Stefan Institute, Ljubljana, Slovenia
G. Meddeler, Lawrence Berkeley National Laboratory, Berkeley, CA, USA
H. Niggli, Lawrence Berkeley National Laboratory, Berkeley, CA, USA
P.W. Phillips, Rutherford Appleton Laboratory, Didcot, UK
P. Weilhammer, CERN, Geneva, Switzerland
E. Spencer, SCIPP, UCSC Santa Cruz, CA, USA
R. Szczygiel, CERN, Geneva, Switzerland
A. Zsenei, University of Geneva, Switzerland

Abstract :

The development of the ABCD chip for the binary readout of silicon strip detectors in the ATLAS Semiconductor Tracker has turned into a pre-production phase, following comprehensive evaluation of the ABCD2T prototype chip. The ABCD2T design is one of the two options of the binary readout architecture which have been developed for the ATLAS SCT. It is manufactured in the DMILL process and comprises in a single chip all blocks of the binary readout architecture. In the paper we will present a summary of the ABCD2T performance as well as design issues and performance of the ABCD3T chip which is expected to be the final version for the ATLAS SCT detector.

Summary :

The development of the readout chip for silicon strip detectors in the ATLAS Semiconductor Tracker has entered into a pre-production phase, following comprehensive evaluation of the recent ABCD2T prototype chip. The ABCD2T design is one of the two options of the binary readout architecture which have been developed for the ATLAS SCT. It is manufactured in the DMILL process and comprises in a single chip all blocks of the binary readout architecture, the front-end circuits, discriminators, binary pipeline, derandomizing buffer, data compression logic, and the readout control logic as required for the ATLAS SCT. A significant improvement of the chip performance has been achieved by implementation of the individual threshold correction in each channel using a digital-to-analogue converter (TrimDAC) per channel.

Detailed evaluation of the ABCD2T design has been performed employing specific test procedures separately for the analogue and digital blocks. The design meets most of the specification, however, the test results indicate that some corrections and improvements are still possible. In particular, this applies to the TrimDAC circuit which is used for threshold correction in each channel. The response characteristics of this circuit exhibit significant non-linearity which degrades the final uniformity of the threshold. The source of the problem has been identified and corrected in the ABCD3T design.

In parallel to detailed evaluation the ABCD2T design the chips have been used extensively for building prototype SCT detector modules using various hybrid layouts and technologies. This work provided us with a complete evaluation of the chip performance.

The DMILL technology is qualified as a radiation resistant one, however, the radiation levels expected for the SCT detector in the ATLAS experiments are at the upper limits of those specified for the DMILL process, i.e. 10 Mrad of the ionising dose and 1E14 n/cm2 1 MeV eq. neutron fluence. In addition, if one takes into account very advanced requirements regarding the noise, speed and power consumption of the ABCD2T chip, it becomes obvious that radiation effects in the basic devices, although limited, can not be ignored.

Radiation hardness of the chip was evaluated in various tests which covered the total dose effects and the single event upset effects. The performed radiation tests indicated for some potentially weak points in the design. The two most important were a significant increase of the digital power consumption and decrease of the signal level in the token/data passing circuit after total ionising dose of 10 Mrad. Both problems have been traced down to particular circuit structure which are sensitive to drift of device parameters after irradiation. More robust solutions for these particular circuits have been elaborated and implemented in the ABCD3T chip.

In total, 16 wafers with the ABCD2T chips split in two different batches have been manufactured at TEMIC foundry. All the chips were fully tested at the wafer level and detailed analysis of yield and failure modes was performed.

In the paper we will present a summary of the ABCD2T performance as well as design issues and performance of the ABCD3T chip which is expected to be the final version for the ATLAS SCT detector.

Id: 79
Corresponding Author: Jan GODLEWSKI
Experiment: ATLAS
Sub-system: General Interest
Topic: Grounding Shielding Cooling And Alignment

Mono-phase cooling system for front-end electronics on the example of the ATLAS TRT detector

Magnus Andersson - Luleå University of Technology Sweden
Pierre Bonneau - CERN
Michel Bosteels - CERN
Jan Godlewski - INP Krakow Poland, CERN

Abstract :

The work presents the results of cooling tests performed for the ATLAS TRT electronics. The test installation and control equipment are described.

A model of a standard cooling unit designed for all ATLAS detectors is also presented together with its modifications corresponding to various limitations connected with experimental zone, magnetic field, limited access and localization of various detectors.

Summary:

The efficiency of cooling system for front-end electronics of TRT end-cap detector was studied both by Finite Element Analysis and experimental tests. A good agreement between the simulations and tests results was achieved. FEA model can predict the temperature of the electronics with a sufficient accuracy in a wide range of heat dissipation (better then 5ºC in 50 to 100 mW/channel range). A mono-phase cooling system was tested experimentally using a unit in which fluorocarbon was used as a coolant. The test results, which will be presented, made it possible to design a final installation.
In the next step various experiments will be included into the final configuration taking into account limitations of the experimental zone.The main goals are as follows: to install a minimum amount of active components in the cavern, to ensure safe and reliable functioning by using systems as simple as possible, enable a distant control and necessary action in the case of problems. The use of a very expensive liquid results also in the necessity of finding a reliable recuperation method.
A cooling unit is designed in such a way that it can function using any tape of liquid and at any temperature. In the ATLAS experiment one can define three distinct temperature zones cooled by mono-phase cooling liquid. On the one hand temperature screens isolating silicon detectors at about -10ºC and TRT at 14ºC, access to both of which is very limited which results in small pipes and as a consequence in high pressure drops. On the other hand, there are the remaining detectors operating at temperatures higher than the dew point in experimental cavern. The access here is less limited enabling the work at the low pressure. Depending on the localization of cooling units it is recommended to equip the pumps with hydraulic motors. Elements and the logic of control are described, while the complete design of a control system will be worked out basing on standards, which will be accepted by the whole ATLAS.

Id: 80
Corresponding Author: Paul O'CONNOR
Experiment: ATLAS
Sub-system: Muon
Topic: Electronics for muon detectors

Performance and Radiation Tolerance of the ATLAS CSC On-Chamber Electronics

A. Gordeev, V. Gratchev, A. Kandasamy, P. O'Connor, V. Polychronakos, V. Tcherniatine, K. Vetter
Brookhaven National Laboratory

J. Dailing, N. Drego, D. Hawkins, A. Lankford, Y. Li, S. Pier, M. Schernau, D.Stoker, B. Toledano
University of California, Irvine

Abstract:

The on-detector electronics for the ATLAS Cathode Strip Chamber (CSC) performs amplification, analog buffering, and digitization of the charge signals from individual cathode strips. Working in a high-rate environment (strip hit rate up to several hundred kHz) the system requires a signal-to-noise ratio of 200:1 and a dynamic range of 10 bits. Radiation conditions are: ionizing dose of 4.4 krad/yr and neutron flux of 7x10^12 n/cm^2/yr.
The system consists of 320 chamber-mounted ASM boards serving a total of over 61,000 channels. Performance and radiation tolerance of ASM prototypes will be discussed.

Summary:

The ATLAS Cathode Strip Chambers (CSCs) find the muon position by interpolation of the charge collected in 3 - 5- adjacent strips. The performance requirements are:

- position resolution in the r-theta plane: ~ 50 microns (implies a signal:noise > 200:1);
- position resolution in the r-phi plane: ~ 1.4 mm;
- dynamic range of 10 bits;
- overall rate per chamber: ~ 10^7 Hz;
- analog buffering during the L1 trigger latency;
- deadtimeless readout;
- radiation tolerance to 4.4 krad/yr and 7 x 10^12 n/cm^2/yr.

The on-chamber electronics is organized into 192-channel Amplifier-Storage Module (ASM) boards which have charge-sensitive preamplifier/shapers, switched capacitor array analog memories, analog-digital converters, data serializer/deserializers, current and temperature monitors, calibration, and fiber optic links. The ASMs occupy a volume of about 2300 cm^3, dissipate 30W of power, and generate 1.3 Gb/s of data at the expected maximum trigger rate.

The full system consists of 64 chambers having over 61,000 channels. Beam test results indicate that the required performance can be achieved, even in the presence of high background rates. Results of recent radiation tests will also be discussed.

Id: 81
Corresponding Author: Paul O'CONNOR
Experiment: ATLAS
Sub-system: Muon
Topic: Electronics for muon detectors

Off-Detector Electronics for a High-Rate CSC Detector

A. Gordeev, V. Gratchev, A. Kandasamy, P. O'Connor, V. Polychronakos, V. Tcherniatine, K. Vetter
Brookhaven National Laboratory

J. Dailing, N. Drego, D. Hawkins, A. Lankford, Y. Li, S. Pier, M. Schernau, D. Stoker, B. Toledano
University of California, Irvine

Abstract:

The off-detector electronics system for a high-rate muon Cathode Strip Chamber (CSC) is described. The CSC's are planned for use in the forward region of the ATLAS muon spectrometer. The electronics system provides control logic for switched-capacitor array analog memories on the chambers and accepts a total of nearly 37 Gbyte/s of raw data from 64 chambers. The architecture of the system is described as are some important signal processing algorithms and hardware implementation details.

Summary:

The described electronics system supports high-rate muon Cathode Strip Chambers (CSC's) planned for use in the forward region of the ATLAS muon spectrometer. Because the chambers are situated in a severe radiation environment, much of the control and data reduction electronics is located off-detector. All 960 channels of each chamber are read out on every level one trigger. With four 12-bit time samples per channel per trigger and a trigger rate of 75 kHz, the 64 chambers of the CSC system output a total of 27.6 Gbyte/s. A planned ATLAS trigger rate upgrade to 100 kHz pushes the data rate to 36.9 Gbyte/s.
The off-detector electronics performs several operations to reduce the CSC data rate. These operations are carried out in two custom-designed VME modules, the Sparsifier and the Readout Driver (ROD). The full system contains a total of 32 Sparsifiers and 8 ROD's.
The Sparsifier performs simple zero suppression and as well as rejection of pulses that are not aligned in time with the arrival of the level one trigger. The Sparsifier is also capable of applying corrections to the data, such as scaling and pedestal subtraction. The Sparsifier transmits reduced data to the ROD via moderate-rate serial connections. The ROD's principal function is to build a single ATLAS-standard event fragment containing data from all eight chambers it services. The ROD also provides extensive data monitoring and is capable of reducing the data rate, for example, by rejecting neutron hits.
Digital signal processors perform most of the data storage, transfer, and processing functions on both the Sparsifier and the ROD. A single DSP module design, containing a DSP, an FPGA, memory, and glue logic, is utilized in a variety of roles on both the ROD and the Sparsifier.

Id: 85
Corresponding Author: Dominique BRETON
Experiment: ATLAS
Sub-system: Calorimetry
Topic: Electronics for Calorimeters

HAMAC, a rad-hard high dynamic range analog memory for Atlas calorimetry

E. DELAGNES, P. BORGEAUD
CEA, DSM/DAPNIA SACLAY, 91191 GifsurYvette, France.

E. AUGE, D. BRETON, G. MARTINCHASSARD, V. TOCUT
LABORATOIRE DE L'ACCELERATEUR LINEAIRE, IN2P3CNRS et Université ParisSud, 91405 Orsay Cedex, France.

J. PARSONS, W. SIPPACH
NEVIS LABORATORIES, COLUMBIA UNIVERSITY, IRVINGTON, NY 10533, USA

Abstract:

An 12 channel analog memory dedicated to the readout of the Atlas liquid argon calorimeter has been developed. Its main function is to sample, at a 40 Mhz rate, the data coming from a three gain shaper, to store it, waiting for the level1 trigger decision, and then to send it more slowly (5MHz) towards a 12 bit ADC. For each trigger, the ADC will digitize 5 samples. As the system is supposed to present minimum dead time, the write operations will be unceasing even during the read phases. The chip can thus be seen as a simultaneous double random access analog memory array. The read and write addresses are generated by a separate controller chip and sent together with other control signals to the analog memory using lowvoltage swings.

In the ATLAS calorimetry, the electronics will have to withstand a total ionising dose higher than 20 krad over a 10 year lifetime. For reliability, the circuit may survive to a total dose of 100krad. Thus the chip has been developed in DMILL technology.

The presentation will highlight the amazing level of performance achieved by this circuit whose dynamic range is far in excess of 13 bits even while undergoing simultaneous write and read accesses.

Id: 86
Corresponding author: Mitch NEWCOMER
Experiment: ATLAS
Sub-system: Tracker
Topic: Electronics for Trackers

Implementation of a Digital Time Measurement Chip (DTMROC99)in DMILL for the ATLAS TRT

C. Alexander, F. Anghinolfi, R. Van Berg, N. Dressnandt, T. Ekenberg, Ph. Farthouat, P. T. Keener, N. Lam, D. Lamarra, J. Mann, F. M. Newcomer, V. Ryjov, M. Soderberg, R. Szczygiel, H.H. Williams

Abstract:

A 16 channel digital time measurement and readout chip, the DTMROC99, has been designed and built in DMILL, a BI-CMOS rad-hard process. This chip is designed to accept low level ternary inputs from the ASDBLR99, a companion analog front end chip, to record the time of arrival of avalanche signals from tracks with 1ns precision as well as to record the detection of Transition Radiation photons in a 144 bit data word. Data is stored in a 3.3us pipeline and transferred to a 13 deep buffer if a Level 1 trigger is decoded. In addition to its main readout function, the chip provides four threshold voltages and two test pulse outputs for the two ASDBLR's it reads out. Communication utilizes specially designed LVDS compatable, low power differential inputs and outputs.

DESCRIPTION OF CHIP:

The DTMROC99 is a digital time measurement and readout chip for the ATLAS TRT straw tube detector. It receives 16 channels of differential ternary encoded signals from two 8 channel ASDBLR99 chips. The ternary (3-level) signals are a composite of two binary discriminator output pulses: one unit of current indicating the presence of a charged particle track and a two unit pulse indicating that the track amplitude is large enough to be from transition radiation. (i.e. caused by an electron track.)

In the DTMROC99 chip, these ternary signals are decoded back into separate ``tracking" and ``transition" pulses by TERNARY RECEIVERS. The transition pulses' existence or absence is recorded at 25ns intervals timed by the 40MHz system clock (BC). The tracking pulse is essentially digitized by sampling for its presence or absence every 3.125ns and setting a bit accordingly. In this way an 8-bit word is generated defining the leading edge and width of the tracking pulse to a resolution of 3.125ns. Eight 40MHz clocks (BC1 - BC8) each delayed by the appropriate multiple of 3.125ns are derived from the system clock using a Delay-Locked-Loop (DLL).

This 8 bit time sample word plus the transition-radiation bit are formed into 9-bit words. All 16 channels then form 144 bits for each 25ns time period. This data is stored in a PIPELINE for 132 clock cycles during which time the decision whether or not to retain the data is made. If a trigger signal (Level 1 accept) is sent to the DTMROC99 chip, the data is stored in a DERANDOMIZER, and then read out of the chip as a serial 40MHz data stream under the control of the READOUT CONTROLLER.

All this is under the full control of a COMMAND DECODER which accepts an external serial bit stream and issues the appropriate control signals to the chip sub-blocks.

Special LVDS compatable RECEIVERS and DRIVERS are used to communicate with the outside world to avoid generation of noise near the sensitive ASDBLR99 chip inputs.

In addition, the DTMROC99 also provides two TESTPULSE and four THRESHOLDS for the two ASDBLR99 chips. Testpulse outputs provide a shaped signal to generate a current pulse similar the signal produced by the straw sensor when filled with the TRT optimized Xe/Ar/CO2 mixture. Both the amplitude and delay of these testpulses are programmable. Four six bit DACs provide a tracking and transition radiation threshold for each ASDBLR.

DESIGN METHODOLOGY

The chip is an assembly of analog and digital blocks contributed by five institutions and integrated at the chip level by a private firm. Analog block performance was confirmed using SPICE and digital blocks were confirmed (and in some cases designed) using Verilog. Subsequent to design, a Verilog representation for each analog block was written to allow a full hierarchical chip level connectivity representation. This verilog representation was used to perform basic functionality tests prior to submission and to develop test vectors used to drive the chip tester after fabrication.

VERIFICATION OF THE FINAL DESIGN

Verilog models were specified only for nominal process conditions. Derating factors were applied to account for changes due to process, supply voltage, temperature and radiation effects, but differences between SPICE and verilog calculations led to the conservative and time consuming approach of checking the design using SPICE on the extracted netlist. In practice large interconnected sections were simulated together and the internal parts of some blocks such as the the pipeline were carefully reduced in complexity to allow meaninnful simulation results to be available within a one week time frame. Using this process several several timing errors were identified and fixed prior to submission. In some cases, the timing was unacceptable only when two or more contitions were not nominal. These were noted and accepted in order to get
actual experience with the design.

CHIP FUNCTIONALITY

PERFORMANCE

The chip is fully functional and its performance is accurately predicted by simulation tools. Overall, the standard deviation of time bin width is measured to be less than 1ns for all working chips. Ternary input signals as short as 4ns have been reliably detected.

* RADIATION TESTS

No performance degradation was observed after exposure to 1E14 neutrons/cm**2. Proton irradiation to 1e14p/cm**2 has been performed and we are awaiting the return of the exposed parts. In addition, we expect to perform SEU tests in the late spring or summer.

* BEAM STUDIES

A board employing four DTMROC99 chips and eight ASDBLR99's has been designed at CERN to be compatible with the TRT wheel prototype. We intend to use this board to instrument a prototype wheel and test the full readout chain at the CERN H8 beamline this summer.

Id: 101
Corresponding Author: Jan KAPLON
Experiment: ATLAS
Sub-system: Tracker
Topic: Electronics for Trackers

Analogue Read-Out Chip for Si Strip Detector Modules for LHC Experiments
E. Chesi1, J. A. Clark2, V. Cindro3, W. Dabrowski4, D. Ferrere2, G. Kramberger3, J. Kaplon1, C. Lacasta5, J. Lozano1, M. Mikuz3, C. Morone2 S. Roe1, A. Rudge1, R. Szczygiel6, M.Tadel3, P. Weilhammer1, A. Zsenei2
1CERN, 1211 Geneva 23, Switzerland
2University of Geneva, Switzerland
3Jozef Stefan Institute, Ljubljana, Slovenia
4Faculty of Physics and Nuclear Techniques, UMM, Krakow, Poland
5IFIC, Valencia, Spain
6Institute of Nuclear Physics, Krakow, Poland

Abstract

We present a 128-channel analogue front-end chip SCT128A for readout of silicon strip detectors employed in the inner tracking detectors of LHC experiment. The architecture of the chip and critical design issues are discussed. The performance of the chip has been evaluated in detail in the bench test and is presented in the paper. The chip is used to read out prototype analogue modules compatible in size, functionality and performance with the ATLAS SCT base line modules. Several full size detector modules equipped with SCT128A chips has been built and tested successfully in the lab with b particles as well as in the beam test.

Summary:

The LHC operating conditions present a very big challenge to the front-end electronics of Si trackers for experiments designed for high luminosity physics. Historically most collider experiments have so far used full analogue readout front-ends for Si trackers and vertex detectors. This method allows individual treatment of data in each channel with optimised and adaptable software and thereby the most detailed control and monitoring of the whole system. Analogue readout is to a large extent immune to external electromagnetic pickup (common mode) since common mode noise can be fully eliminated with software. The price to pay for this safety is a heavier load on data transmission off the detector over optical links, both in bit rate and in the required number and quality of the links.

The ATLAS Semiconductor Tracker has adopted a binary scheme for the readout of silicon strip detectors as the baseline. The binary architecture allows a more compact design and has the advantage of a much reduced data transfer rate with more chips using a single optical link. This architecture is, however, not immune at all to the common mode noise and so it is very sensitive to the external electromagnetic interference.

In this paper the ATLAS back-up solution, the SCT128A chip will be presented. The SCT128A chip is an example of the analogue readout architecture for silicon strip detectors, which meets all basic requirements of the LHC experiments. It comprises five basic blocks: front-end amplifiers, analogue pipeline (ADB), control logic including derandomizing FIFO, command decoder and output multiplexer. The chip has been manufactured in the DMILL process, the same as used for the binary chip ABCD. The front-end is a fast transimpedance amplifier, using a bipolar input transistor and providing pulse shaping with peaking time of 25 ns.

The design and the performance of the chip will be presented. The basic chip performance have been evaluated in the test bench. Analogue prototype module consisting of two 6.4 cm x 6.3 cm ATLAS baseline detectors read out by 6 SCT128A chips has been built. The chips are mounted on a ceramic hybrid connected to the sensors in the end-tap configuration. The pitch adapter needed to match the strip pitch of 80 mm and the pitch of input pads on the chip, which is 60 mm, is integrated on the hybrid. The performance of the module, which has been tested with a Ru b- source and in a 100 GeV pion beam, will be discussed.

An optical link for transmission of data from the SCT128A chip using VCSELs is under development. Performance of the prototype analogue optical link used for read out of the analogue module will be presented and discussed.

Id: 103
Corresponding Author: Laurent BLANQUART
Experiment: ATLAS
Sub-system: Tracker
Topic: Electronics for Trackers

Front-End electronics for ATLAS Pixel detector

Abstract:

The electronics subgroup of the ATLAS pixel detector has pursued an iterative programme of design development over the last 3 years. The initial phase of this demonstrator programme was aimed at realizing ATLAS specification front-end chips using radiation-soft technologies, the designs of which could then easily be adapted for fabrication at rad-hard foundries. First realistic prototypes were designed in 2 parallel efforts (Europe and US) in 97/98, producing a rad-soft AMS prototype (FE-A/FE-C) and a rad-soft HP prototype (FE-B). Throughout 98/99, more than 60 single chip assemblies and 10 electrically functional modules were produced and have been studied extensively in lab and during 7 testbeam periods at SPS. All of the ATLAS requirement issues (except for the radiation hardness) were addressed in detail such as noise, threshold dispersion, timewalk, digital/analog crosstalk, power supply rejection...with very encouraging results. These measurements on both single chip assembly and module are presented. A unified design approach has been adopted for rad-hard front-end chips, i.e. all working on the same design to be implemented in 2 rad-hard processes. The rad-hard designs, namely FE-D for the DMILL process and FE-H for the Honeywell process, maintain the spirit of the demonstrator programme (i.e. pin compatibility, same pixel pitches...) and combine features of both FE-A/C and FE-B. FE-D has been received in Oct. 99 and FE-H will be submitted during summer 2000.

Id: 104
Corresponding Author: Riccardo VARI
Experiment: ATLAS
Sub-system: Muon
Topic: Trigger Electronics

RADIATION TOLERANCE EVALUATION OF THE ATLAS RPC COINCIDENCE MATRIX SUBMICRON TECHNOLOGY

E.Gennari, E.Petrolo, A.Salamon, R.Vari, S.Veneziano
INFN - Sezione di Roma
P.le Aldo Moro 2 - Rome - Italy

ABSTRACT:

The Coincidence Matrix ASIC is the central part of the ATLAS Level-1 Muon Trigger in the barrel region; it performs the trigger algorithm and data read-out. The ASIC will be mounted on dedicated boards on the Resistive Plate Chamber detectors. The chosen technology has to guarantee complete functionality in the ATLAS RPC radiation environment. Radiation tests have to satisfy the radiation tolerance criteria proposed by the ATLAS Policy on Radiation Tolerant Electronics. The ATLAS standard test methods has to be followed in order to guarantee both total dose and single event effects tolerance.
A frequency multiplier ASIC was used for technology evaluation and radiation tests. The chip is a low jitter programmable clock multiplier, realised in 0.25 micron CMOS technology. This frequency multiplier is intended to be used in the Coincidence Matrix ASIC as a macro, to perform the internal clock frequency multiplication. Radiation test results will be presented.

SUMMARY:

The ATLAS level-1 muon trigger in the barrel region makes use of the Resistive Plate Chamber dedicated detector (RPC). The triggering procedure is accomplished through a Low Pt and a High Pt trigger. The Low Pt trigger uses the information generated in the two Barrel Middle RPC stations, while the High Pt trigger uses the result of the Low Pt trigger and the information of the RPC Barrel Outer station. RPC data readout and level-1 triggering are performed by a dedicated chip, the Coincidence Matrix ASIC (CMA). About 4000 CMA chips will be installed on dedicated boards, that will be mounted on the RPC detectors. This chip performs almost all the most relevant functions needed for the barrel trigger algorithm and for the readout of the RPC strips. It makes the right timing settings of the signals, the coincidence and majority operations, the Pt cut on three different thresholds and it acts as level-1 latency memory and derandomizing buffer.
Electronics complete functionality has to be guaranteed in the ATLAS RPC radiation environment. The ATLAS Policy on Radiation Tolerant Electronics defines the minimum dose and fluences which must be tolerated by the electronics, and the maximum rate of soft, hard or destructive Single Event Effects acceptable for the electronics. This level of reliability must be maintained during 10 years of LHC operation. ATLAS standard radiation test methods have to be followed in order to compare test results with the calculated Radiation Tolerance Criteria defined in the ATLAS Policy, so as to qualify the ASIC technology, architecture and design.
A frequency multiplier ASIC was used for CMA technology evaluation and radiation tests. A chip containing the frequency multiplier was released by Fujitsu for test use. The CMA chip will make use of this frequency multiplier as a macro, for generating an internal 320 MHz clock from the external 40 MHz ATLAS clock. The frequency multiplier uses a low jitter Delay Locked Loop (DLL) to provide the output clock, which range is 40-400 MHz (a multiplying factor between 2 and 32 can be programmed). The chip is realised in 0.25 micron CMOS technology, and has a 2.5 V power supply.
Cobalt 60 gamma source and proton source were used for radiation tests. The chip showed a correct functionality during gamma irradiation up to a total dose of 300 kRad (lower then calculated RTC value). No hard or destructive errors were detected during proton irradiation. Only soft Single Event Upset errors were detected. The extrapolated foreseen rate of soft SEU in the RPC detectors is lower then the calculated RTC.
Test results will be presented, as well as radiation test strategies and comparison between different radiation facilities.