ID: 20
Corresponding Author: Jean-Claude SANTIARD
Experiment: ALICE
Sub-system:
Topic: Particle Identification
DILOGIC-2 A SPARSE DATA SCAN READOUT PROCESSOR FOR THE HMPID DETECTOR OF ALICE
H. Witters, IMEC vzw, 3001 Leuven, Belgium
(witters@imec.be)
J.C. Santiard, CERN, Geneva, Switzerland (jean-claude.santiard@cern.ch)
Paolo Martinengo, CERN, Geneva, Switzerland
(paolo.martinengo@cern.ch)
For the ALICE collaboration
Abstract:
Processing of analog information are always spoiled by additional DC level and noise given by the sensors or their additional readout electronic. The Dilogic-2 ASIC circuit has been developed in a 0.7um n-well CMOS technology to process the data given by Analog to Digital Converters, in order to eliminate the empty channels, to subtract the base line (pedestal) and store locally the true analog information.
Summary:
The Dilogic-2 can handle up to 64 channels by group of 16, 32, 48 or 64 channels. At the present time, the Gassiplex0.7-3 front-end analog circuit is used by group of 48 channels that are multiplexed on the same ADC. The processing has to be done in two steps, firstly pedestals and noise of each channels have to be measured and stored on the chip, then the normal operation can start, zeros will be eliminated and the on-chip memory will be loaded by true value information. The sparse data scan section is made of a digital comparator and a subtractor; the pedestal field has been limited to 8-bits while the data have 12-bits range. These two elements are fed on one side by the analog information and on the other side by the contents of two separate memories filled respectively for each channel by the chosen level of comparison (threshold) and the pedestal value. Calling PED(i) and SIG(i) the average and r.m.s. values of a pedestal distribution, the operating threshold of the channel (i) is defined as: TH(i) = PED(i) + N*SIG(i), where N is a selectable constant, usually =3.
Thresholds and pedestals are first measured and stored in a memory, for every channel; the channel address allows finding the right values of each channel during the processing. A BIT-MAP memory (64w x 16-bits) is filled with "1" for channels above threshold or "0" for channels below the threshold, while an analog data FIFO memory (512w x 18-bits) is loaded with the amplitude information (12-bits) and the address of the selected channels (6-bits). These two operations are performed in parallel at a clock speed of 10MHz. Each event readout is turned off by an End-Event word, which contains the number of good channels (7-bits) and the corresponding event number (11-bits). A presettable almost-full flag prevent over-writing the FIFO; an internal 4-bits controller has been implemented to perform the different front-end and back-end operations, particularly one, which is used to test the functionality of the chip by an outside processor. Finally, the Dilogic-2 can be daisy-chained to allow the readout of several hundreds of channels on the same bi-directional data bus at a maximum speed of 20MHz.
Id: 25
Corresponding Author: Giovanni MAZZA
Experiment: ALICE
Sub-system: Tracker
Topic: Electronics for Trackers
Test results of the ALICE SDD electronic readout prototypes
G. Mazza[INFNTo], G. Alberici[INFNTo],
G. Anelli[CERN], G.C Bonazzola[UniTo],
D. Cavagnino[UniTo], P.G. Cerello[INFNTo],
P. De Remigis[INFNTo],
D. Falchieri[INFNBo], A. Gabrielli[INFNBo],
E. Gandolfi[INFNBo],
P. Giubellino[INFNTo], M. Masetti[INFNBo],
L.M. Montano[INFNTo],
D. Nouais[INFNTo], A. Rivetti[CERN][UniTo],
F. Tosello[INFNTo],
A. Werbrouck[UniTo], R. Wheadon[INFNTo]
for the ALICE collaboration
Institutes :
[INFNTo]
INFN sezione di Torino, Italy
[INFNBo]
INFN sezione di Bologna, Italy
[UniTo]
Universita` di Torino, Italy
[CERN]
CERN, Geneve, Switzerland
Abstract:
The first prototypes of the front-end electronic of the ALICE silicon drift detectors has been designed and tested. The integrated circuits have been designed using state-of-the-art technologies and, for the analog parts, with radiation-tolerant design techniques. In this paper the test results of the building blocks of the PASCAL chip and the first prototype of the AMBRA chip are presented. The prototypes fully respect the ALICE requirements; owing to the use of deep-submicron technologies together with radiation-tolerant layout techniques, the prototypes have shown a tolerance to a radiation dose much higher than the one foreseen for the ALICE environment.
Summary:
The design of the readout electronic for the
ALICE silicon drift detector is a very challenging task, due on one side
to the huge amount of data produced by those detectors ( 256 10-bit words
for each detector anode, in the case of the ALICE SDDs ) and on the other
hand to the stringent constraints in term of space, power consumption and
radiation hardeness. The chosen architecture is based on 2 integrated circuit,
PASCAL and AMBRA. It works in two different phases : during the acquisition
phase the detector signal is amplified and stored into a fast analogue
memory; when the trigger signal validates the data, the readout phase starts
and the analogue informations in the memory are converted by an A/D converter
and transferred into a digital multi-event buffer. All the analogue functions
( amplification, storage and conversion ) are embedded in a single chip
( PASCAL ) while the digital event buffer plus most of the control logic
are on a separate chip ( AMBRA ). The analogue memory is of the write-voltage
read-voltage type; it uses MOS capacitors as storage elements in order
to save space. The intrinsec MOS capacitor non-linearity limits the dynamic
range to about 1.5 volts over a 2.5 power supply. The A/D converter is
of the switched-capacitor, successive approximation type; the 10 bit resolution
is obtained by an 8 bit main DAC followed by a 2 bit secondary DAC with
direct coupling. Prototypes of the analogue memory and the A/D converter
in a commercial 0.25 um technology with radiation tolerant design techniques
have been designed and tested. The results show that both prototypes fully
satisfy the ALICE requirements in terms of performances and power consumption.
Owing to the adopted radiation tolerant technique, the prototypes does
not show any significant degradation after a total dose up to 10 Mrads.
The first prototype of the PASCAL chip is currently under production. The
first prototype of the AMBRA chip has been designed and tested in a 0.35
um technology. The chip fully satisfy the ALICE requirements; radiation
test are ongoing in order to check the radiation tolerance of a fully digital
deep submicron technology without radiation tolerant layout techniques.
Id: 36
Corresponding Author: Angelo RIVETTI
Experiment: ALICE
Sub-system: Tracker
Topic: Electronics For Trackers
A MIXED SIGNAL ASIC FOR THE SILICON DRIFT DETECTORS OF THE ALICE EXPERIMENT IN A 0.25 UM CMOS
A. Rivetti (1,2), G. Anelli(1), F. Anghinolfi(1),
G. Mazza,(2) P. Jarron(1)
(1)CERN, CH-1211 Geneva 23, Switzerland
(2)INFN, Sezione di Torino, Via Pietro Giuria
1, 10125, Torino, Italy
Abstract:
A mixed signal integrated circuit developed for the read-out of Silicon Drift Detectors (SDDs) is presented.
The chip contains 32 channels and 16 ADCs. Each channel is made of an amplifier and an analog pipeline with 256 cells. One ADC is shared by two adjacent channels. The circuit is optimized to match the specifications of the SDDs of the ALICE experiment, where large dynamic range and low power consumption are key issues. The input noise is calculated to be 200 e- rms for an input capacitance of 3pF and a detector dark current of 10nA. The power consumption is 5mW/channel.
Summary:
Silicon Drift Detectors offer the advantage of a two-dimensional position measurement while requiring a very low amount of processing electronics. These detectors are well suited for experiments in which a very high particle density is coupled with a relatively low event rate, as is the case of heavy-ion experiments. For example, SDDs are used in the two intermediate layers of the Internal Tracking System (ITS) of the ALICE experiment. The constraints on material budget, power consumption and noise make the design of the front-end electronics for the SDDs in ALICE particularly challenging. In fact, in order to reach the required resolution (30 um in both coordinates) the noise should be limited below 250 e- rms. The maximum power consumption (including also the digitization of the data) must be kept below 5mW/channel. The electronics is DC coupled to the sensor and the baseline has to be stabilized against variations of the detector leakage current. Input signals up to 8 mips have to be correctly processed by the front-end.
We have developed an ASIC which is able to meet all of the previous requirements. The chip provides amplification of the input signal, temporary storage of the analog data in a 256 cells pipeline and a 10 bit analog-to-digital conversion.
All the operations are controlled by a digital unit implemented on chip. The chip has been implemented in a commercial 0.25 um CMOS technology, using radiation tolerant layout approach. This should guarantee immunity to radiation damage at least up to a total dose of 10 Mrad (SiO2).
The amplifier uses a charge integrating scheme, with pole-zero cancellation and CR-RC^2 shaping. The coupling between the preamplifier and the shaper is made with the help of an error amplifier. In this way, the value of the baseline can be regulated via an external voltage and is completely insensitive to the variations of the detector leakage current. The power consumption of the amplifier (including the output buffer) is 1.7mW/channel and the maximum signal swing is 1.4 Volt. The gain of the amplifier for a delta input signal is 170mV/mip.
In the analog memory gate capacitors are used in order to reach a satisfactory circuit density. A voltage-write voltage-read scheme has been selected to minimize the effect of the voltage dependence of these capacitors.
The 10 bits analog-to-digital converters is implemented using a switched capacitor charge redistribution scheme. Since in this circuit the capacitor linearity is crucial metal to metal capacitor are used. The ADC is able to perform a full conversion cycle (sampling +digitization) in 500 ns. Due to layout constraints one ADC is used to convert the data of two adjacent channels.
For the analog memory and the ADC we used preliminary circuits developed as analogue demonstrators in the framework of the CERN RD49 program. The tests performed on these building blocks have shown very satisfactory results; on both parts a resolution of 10 bits with very low power consumption (3.5mW/channel for the memory and 1mW/channelfor the ADC) has been measured.
Id: 41
Corresponding Author: Giovanna Di MARZO
SERUGENDO
Experiment: ALICE
Sub-system: Trigger
Topic: Trigger Electronics
Specification and Simulation of ALICE DAQ System
Giovanna Di Marzo Serugendo, CERN / Predrag
Jovanovic, School of Physics and Astronomy, University of Birmingham /
Pierre Vande Vyvre, CERN / Orlando Villalobos Baillie, School of Physics
and Astronomy, University of Birmingham
for the ALICE Collaboration.
Abstract:
The Trigger and Data Acquisition System of the ALICE experiment has been designed to support the high bandwidth expected during the LHC heavy ion run. A model of this system has been developed. The goal of this model is twofold. First, it allows to verify that the system-level design is consistent and behaves according to the requirements. Second, it is used to evaluate the theoretical system performances using the measurements done on sub-systems prototypes. This paper presents the specification and simulation of a model of the ALICE DAQ system using a commercial tool (Foresight). This specification is then executed to simulate the system behaviour.
Summary:
The ALICE Trigger and Data Acquisition System (DAQ) system is required to support an aggregate event building bandwidth of up to 2.5 GByte/s and a storage capability of up to 1.25 GByte/s to mass storage. The system must also be able to combine different types of physics events: a slow rate of central triggers generating the largest fraction of the total data volume, together with faster rates of dielectron and dimuon events.
The ALICE DAQ system has been decomposed in a set of hardware and software components. The detailed system design is going on in parallel with the development of prototypes of these components. We wish to verify this design in order to check that it can reach the expected behaviour and the target performances.
However, such a complex system happens to be difficult to verify manually, since there is no corresponding mathematical description. A tool that enables to define a model of the system, and to perform its verification is therefore an extremely valuable help.
This paper presents the formal specification and simulation of the DAQ of the ALICE experiment. The tool used is a modelling and simulation tool, called Foresight. It allows to specify the system by successive decomposition. It enables to describe the system in an abstract manner in order to focus on the functionality and also to refine it by adding the details of its implementation.
The Foresight specification is made of hierarchical data flow diagrams, finite state diagrams, and pieces of a procedural modelling language. The specification provides a unambiguous description of the system. The semantics of the specification provides a model of the system whose behaviour is very close to the behaviour of the system. The verification process is performed during the simulation. It demonstrates the functional correctness of the system.
The Foresight simulation consists of the execution of the specification.
It offers debugging functions like animation of diagrams, breakpoints, and monitor windows. The simulation is used to evaluate the theoretical system performances using the measurements done on sub-systems prototypes. It also enables to perform some analysis such as the system sensitivity to some key parameters. One can also explore other algorithms, and new architectures. This is useful when he final architecture has not yet been defined (as it is the case for ALICE), since it helps to compare architectures or implementation choices.
The current ALICE specification describes the functionality of the whole experiment and of the major sub-systems: Trigger, Trigger Detectors, Tracking Detectors, DAQ, Permanent Data Storage.
Till now focus has been given to the trigger system. The trigger system performance (trigger types rates) has been simulated under different conditions (different buffer sizes for the detectors, and different bandwidth to the DAQ). This has shown the upper limit of each trigger type rate.
Future work will focus on the DAQ performances and the investigation of different architectural choices. The model will be enriched with a more detailed specification of some existing DAQ components such as the ALICE Detector Data Link (DDL) or the DAQ software framework (DATE).
Id: 48
Corresponding Author: Eduard ATKIN
Experiment: ALICE
Sub-system: General Interest
Topic: R/m Field Tolerant Electronics
HIGH-SPEED COMPARATOR IC WITH LOW TIME DISPERSION
E.V.Atkin
Abstract:
The high-speed comparator for fast time reference is represented. It can be used as a leading edge discriminator or as a core for building constant fraction discriminator and can be useful for the development of time-of-flight systems.
It is manufactured with a bipolar process. Its main feature is a small time dispersion of output signal (200 ps) at the presence of a wide dynamic range of input signals (overdrives from 10 mV to 1V).
This paper describes the approach to the design of the new version of a low time dispersion comparator. The structure of such a comparator, features of schematics of its separate stages and its parameters are described.
Summary:
The paper reflects the results of the activities, being the continuation of the MEPhI group's efforts on developing precise timing discriminators [1].
The cost effective high-speed comparator IC for fast time reference is represented. It can be used as a leading edge discriminator or as a core for building constant fraction discriminator. It can be useful for the development of time-of-flight systems (such as ALICE TOF), providing a time reference accuracy at the order of tens of picoseconds.
It is manufactured on the basis of an application specific semicustom array with a bipolar process [2].
This paper describes the approach to the design of the new version of a low time dispersion comparator. The structure of such a comparator and its schematics were designed to make it a functional analog of the well-known IC AD96685 from Analog Devices.
The comparator contains three symmetrical differential stages and is added by the circuits of built-in hysteresis (from 0 to 4 mV) control and output signal logic variation. Its main peculiarity consists in the fact, that the small time dispersion of output signal (~200 ps) is specified for a wide dynamic range of input signals (overdrives from 10 mV to 1V) and for a temperature range from 0 to 70 °C. The propagation delays were defined with a 100 mV pulse.
The mentioned parameters were achieved at the expense of using: · non-standard differential stages built as current amps; · dynamic nonlinear loads, providing the compression of input signals.
Especial attention was paid to minimize the static errors and intrinsic noise of the comparator. The following table presents certain comparator parameters.
Parameter Value Units
Input bias current 20 max uA
Input offset current 2.0 max uA
Input offset voltage 2.0 max mV
Input voltage range ±2.5 V
Intrinsic input noise 1.0 rms mV
Outputs provide complementary digital signals fully compatible with ECL 10K logic families. The output signal logic variation is provided by applying a control potential to a separate IC pin.
Power consumption of the comparator does not exceed 150 mW at standard supply voltages of ±5V.
References
1P.Khlopkov et al. A discriminator PCB for precise timing signal generation. Third Workshop on Electronics for LHC experiments, London, Sept. 22-26, 1997, CERN/LHCC/97-60, p. 497-499.
2A.Goldsher et al. A semicustom array chip for creating high-speed front-end LSICs. Same as previous, p. 257-259.
Id: 63
Corresponding Author: Jean-Robert LUTZ
Experiment: ALICE
Sub-system: Tracker
Topic: Electronics For Trackers
FEE tracker module developments for ALICE and STAR
Abstract:
Assessments of the front-end module developments in the frame of ALICE and STAR trackers in relation with the radiation effects on detectors and chips. Production of similar modules for the STAR SVT.
Id: 82
Corresponding Author: Paulo FONTE
Experiment: Alice
Sub-system: Trigger
Topic: Particle Identification
A simplified and accurate front-end electronics chain for timing RPCs
A.Blanco(1), N.Carolino(1), P.Fonte
(1,2), R. Ferreira-Marques (1,3), A.Gobbi (4)
(for the ALICE collaboration)
1-LIP, Coimbra, Portugal.
2-ISEC, Quinta da Nora, Coimbra, Portugal.
3-Departamento de Física da
Universidade de Coimbra, Coimbra, Portugal.
4-GSI, Darmstadt, Germany.
Abstract :
Recent advances in electronics and construction techniques have pushed the timing resolution of Resistive Plate Chambers below 50 ps sigma with detection efficiencies close to 99% for MIPs. In this paper we describe a new front-end electronics chain for accurate time and charge measurement in these devices, having in view a possible application in ALICE's T0 counter.
The circuit is built solely from commercially available and inexpensive integrated circuits, featuring a reduced number of components. It includes a fast (2 GHz bandwidth) two-stage amplifier that feeds a fixed threshold discriminator followed by an external TDC. The amplified signal is also buffered into an external ADC for charge digitization.
The chain was tested with realistic test signals from an RPC, yielding a timing resolution around 10 ps sigma for signal charges above 100 fC and a charge resolution of 5 fC.
Summary :
The recent development of timing Resistive Plate Chambers (RPCs) opened the possibility to build large, high-resolution, TOF arrays at a low cost per channel. Previous work has shown timing accuracies below 50 ps sigma at 99% efficiency for single four-gap chambers [1] and an average timing accuracy of 88 ps sigma at and average efficiency of 97% for a 32 channel system [2].
In this paper we describe a new, streamlined, front-end electronics chain for accurate time and charge measurement in these devices. The circuit will be used in future developments aimed to extend the detector size, to include a position sensitive readout and to achieve better timing resolution and rate capability.
The circuit is made solely from commercially available and inexpensive integrated circuits, featuring a reduced number of components. It includes a fast (2.5 GHz bandwidth) two-stage amplifier that feeds a fixed threshold discriminator followed by an external TDC. The amplified signal is also buffered into an external ADC for charge digitization. A full schematic and PCB layout will be included in the final report.
The test setup included a single-gap RPC as a realistic signal source, feeding in parallel two front-end circuits. The time difference between both timing signals was measured by a TDC constituted by an ORTEC 286 TAC, followed by a shaping amplifier whose output was digitized by a LeCroy 2249B peak-sensing ADC. The amplifier gain was adjusted to give to the TDC a 3 ps bin width and a 6 ns time range. The measured time resolution of the TDC was 3.5 ps sigma. The analogue outputs of both channels were digitized by a LeCroy 2249w charge-sensitive ADC. The fast (electron) component of the signal was selected by a 40 ns gate width. The system was calibrated by injection of a set of know charges using one of the test inputs, yielding a sensitivity of 3.3 fC per ADC bin, a digitization range of 6 pC and a charge resolution of 5 fC (1.5 bins) sigma.
The timing accuracy of the system was measured by slicing the charge distribution in several regions, applying a linear slewing correction to each slice and doing a gaussian fit to the corrected time distribution of each slice. The results show that the electronic timing accuracy is close to 10 ps for fast signal charges above 100 fC and it is degraded for smaller charges.
Further tests using electronically generated signals injected into single timing channels were performed to compare the present to the previous version of the front-end circuit (used in [1]), based on a pre-amplifier made with discrete components. The results shown an evident advantage of the new design for the smaller charges.
[1] P. Fonte, R. Ferreira Marques, J. Pinhão, N. Carolino, A. Policarpo, "High Resolution RPCs for Large TOF Systems", preprint CERN-EP/99-115, to be published in Nucl. Instr. And Meth. in Phys. Res.
[2] A. Akindinov et al., "A four-gap glass-RPC time-of-flight array with 90 ps time resolution",. preprint CERN-EP/99-166, submited to the IEEE Trans. Nucl. Sci.
Id: 89
Corresponding Author: Giacinto De CATALDO
Experiment: ALICE
Sub-system: DAQ
Topic: Detector Control And Real Time Systems
The Detector Control System for the HMPID in ALICE Experiment at LHC
G. De Cataldo for the ALICE collaboration,
INFN Bari, Italy
(email: giacinto.de.cataldo@cern.ch)
Abstract:
The Detector Control System (DCS) of
ALICE at LHC will allow a hierarchical consolidation of the participating
sub-detectors to obtain a fully integrated detector operation.
The High Momentum Particle Identification
Detector (HMPID), based on a Ring Imaging Cherenkov, is one of the ALICE
sub-detectors. Its DCS has to ensure the detector configuration, operation
in standalone mode for maintenance, monitoring, control and integration
in the ALICE DCS.
In this paper a status report of the
HMPID DCS is presented. Costs and merits of its implementation in function
of the chosen HV and LV systems will also be reported.
Summary:
The detector for LHC experiments will be installed in underground caverns. This removes the possibility of local interventions during the operation of the LHC accelerator. Consequently remote access becomes a primary condition, and in order to operate and control such complex detector an efficient DCS will be mandatory.
From the DCS point of view, the HMPID
consists of 4 sub-systems, each one with parameters to be set and/or read
out. These sub-systems are:
- LV power supply system,
- HV power supply system,
- Gas system for the multiwire proportional
chamber,
- Liquid circulating system for the
Cherenkov radiators.
The HMPID DCS, is structured in three
well defined layers: process layer, control layer and supervisory layer.
The first one consist of sensors, actuators and custom hardware (FEE, LV..);
the second consists of digital-analogue modules interfacing the process
layer and supervised by control computer equipment of type PLC (Programmable
Logic Controller) connected by a dedicated general purpose LAN, i.e. Ethernet
and TCP/IP. The third one consists of a software system based on a server/client
model. It is finalised to configure, control and operate the HMPID either
integrated in the ALICE DCS or in standalone mode for maintenance and upgrading
of the detector.
Since the high number of parameters
to deal with in the ALICE DCS, according to the JCOP recommendations, the
supervisory software should be based on an industrial product (under selection)
running on workstation with NT or LINUX O.S.. Consequently the HMPID DCS
will be also based on the same product in order to import it easily in
the ALICE DCS.
Whilst we are already running DCS prototypes
of the liquid and gas systems, at present the crucial sub-system to be
integrated in the HMPID DCS is the LV power supply system.
Some reliable commercial solutions
with an OPC server, supporting TCP/IP protocol and matching the electronics
power consumption are available, but their costs seems to be rather high
if compared with a custom solution.
In the last case however, the custom
auxiliary electronics to ensure voltage, current sensing and LV channel
switching, would require a non-standard maintenance compared to what is
ensured on long term operation by companies which supply crates with proper
connectivity and LV modules with complete remote control. Therefore after
a market survey we are inclined to adopt a commercial solution based on
the CAEN SY1527 (or 527) system as HV-LV power supply system.
Id: 90
Corresponding Author: Cristoforo MARZOCCA
Experiment: ALICE
Sub-system: Tracker
Topic: Electronics for Tracker
Design and Characterization of a DAC for the Slow Control of the Pixel Chip
F. Corsi (*), R. Dinapoli (*)(#), P. Lamanna(*),
C. Marzocca(*)
* Dipartimento di Elettrotecnica ed Elettronica
- Poltecnico di Bari
# INFN - Sezione di Bari
Abstract :
A digital to analog converter for slow control of pixel front end chip has been designed in a 0.35 um standard CMOS technology to prove the effectiveness of the chosen circuit structures for this application. The DAC provides a total output current variation of about 15uA with an accuracy of 8 bits (LSB=60nA).
The DAC is based on a PMOS current bank (an
NMOS of a reasonable size would operate in the weak inversion region for
these current levels and would hence be unsuitable for accurate current
sources). The bit value determines whether the current corresponding to
these bit is switched to the output or not.
The occupied area is about 300um x 300um and
total power dissipation is 85uW. The results of the test measurements
performed on the 36 fabricated prototypes show that statistical fluctuations
of the output current due to mismatch are negligible compared to the desired
accuracy for all the input configurations.
Summary :
To ensure uniformity of all channels in a pixel
system containing many readout chips, the bias of each chip has to be controlled
individually. This is readily done using on-chip DACs for biasing. This
also allows to re-optimize the settings for every chip regularly to compensate
for radiation induced variations.
The main specifications for this current output
digital to analog converter include area occupation and power dissipation,
radiation hardness and accuracy which must be guaranteed in presence of
device mismatch and significant irradiation dose.
The proposed DAC structure has been implemented
in a standard 0.35 um deep-submicron CMOS technology with special layout
techniques to obtain radiation tolerance. The core of the circuit is an
array of 2^n-1 elementary current sources realized with PMOS transistors
suitably biased and dimensioned to deliver the current Ibit corresponding
to the least significant bit of the DAC. Starting from the power available,
the desired output current variation, expressed as a fraction of the maximum
output current, and the needed accuracy set the value of Ibit and the number
of bits of the DAC. For a minimum area design, W=Wmin has been chosen.
The value of the length L and, thus, the overdrive
Vgst, have been defined considering the matching properties of the transistors
employed as a function of W and L.
The variance of the output current has been expressed in terms of the matching parameters of the technology used and, imposing that this variance is less than Ibit, the minimum length of the elementary current source has been derived. Of course the dimensions of the current source array must be compatible with the total area available, otherwise the number of bits must be reduced.
Global variations of the MOS threshold voltage are compensated by means of an all-PMOS bias circuit based on a threshold extractor. The 2^n-1 elementary current sources are suitably summed in order to obtain the n bit currents, scaled as the powers of two. The DAC configuration is set by means of n PMOS deviators, which send the related bit current toground or to the output stage of the circuit. This stage is needed to rescale the current delivered by the source array to the value required by the application, in our case 10uA, and is based on the concept of current reflector.
Up to now measurement tests have been performed on 22 out of the 36 prototypes manufactured of the 8 bit DAC. The results show that the absolute differential non-linearity error is always less than one half of the minimum output step Ilsb, whose average value is 60nA, thus achieving the 8 bit accuracy. The following table summarizes the main measurement results.
Average offset error 274nA
Gain variance 2.2 %
Max Integral Nonlinearity Error 118nA
Max Differential Nonlinearity Error 27nA
Measurements on the remaining prototypes are still in progress and radiation hardness characterization of the DAC will take place soon after.
Id: 91
Corresponding Author: Michael BURNS
Experiment: ALICE
Sub-system: Tracker
Topic: Electronics for Tracker
The ALICE Silicon Pixel Detector Readout System
Federico ANTINORI (1), Jaroslav BAN
(2), Michael BURNS (1), Michael CAMPBELL (1), Peter CHOCHULA (1, 3), Fabio
FORMENTI (1), Tullio GRASSI (4), Alexander KLUGE (1), Pierluigi LISCO (5),
Franco MEDDI (1, 6), Michel MOREL (1), Giorgio STEFANINI (1), Kennith WYLLIE
(1)
for the ALICE collaboration.
(1) CERN, 1211 Geneva 23, Switzerland
(2) Institute of Experimental Physics,
04353 Kosice, Slovakia
(3) Institute of Experimental Physics,
84215 Bratislava, Slovakia
(4) Formerly CERN, 1211 Geneva 23,
Switzerland
(5) Universita degli Studi di Bari,
I-70126 Bari, Italy
(6) Universita di Roma La Sapienza,
I-00185 Roma, Italy
Abstract:
The ALICE SILICON PIXEL DETECTOR (SPD) is located within the Inner Tracking System (ITS) and is the detector with the highest active channel density and closest to the point of interaction.
Approximately 10 million active electronic channels, contained in a volume of 34 litres, have to be read out and controlled.
Such a high density in an inaccessible position has imposed a high degree of multiplexing to reduce the amount of cabling to a minimum.
This paper will describe the proposed architecture of the readout and control paths.
Summary:
The basic building block of the ALICE SPD is the ladder consisting of a Pixel detector matrix flip-chip bonded to five front end readout chips.
Four ladders are aligned in the beam direction, glued and wire bonded onto a bus to form a 33cm long stave. Two pilot chips are located at the extremities of this bus to perform the readout and control functions and transmit the digital data to a remote Router which will assemble the data for transmission to the DAQ.
Six staves, two from the inner layer and four from the outer, are mounted on a carbon fibre support and cooling sector. Ten such sectors are then mounted together around the beam pipe to close the full barrel. In total there will be 60 staves, 240 ladders, 1200 chips, 9.83 * 10^6 cells or active channels of read out.
Each front end readout chip contains a mixture of analogue and digital circuitry for the readout of 8192 detector cells which are arranged in a matrix of 256 rows by 32 columns. Each cell comprises of a preamplifier/shaper, discriminator, trigger latency delay line, a four event de-randomising buffer and an output shift register.
Acquisition and readout are independent activities which are performed in parallel. Both are controlled by the Pilot chip. The front end chips run as slave devices. The Pilot chip, on receipt of a L1 trigger signal will cause the detector hit pattern to be stored in the first free location of the de-randomising buffer buffer of the front end chip. The L2 decision will determine whether the front end chip is read out or not. A L2Y will cause each Pilot chip to initiate a read out cycle by a sequential addressing of its own ten front end chips. The data from the addressed de-randomising buffer are shifted out of the front end chip into the Pilot chip and serialised for transmission over an optical fibre link to the Router module which will be located outside of the ALICE detector. A L2N will cause the data from the de-randomising buffer to be ignored. In each case the de-randomising buffer location is freed for future use.
Each Router will receive the data from six optical fibre links. Each Router input stage will perform, on the fly, zero suppression of the redundant data before formatting for insertion into the DAQ via the ALICE DDL. The controls for the pilot chips and readout chips will be issued by the Router on reception of the trigger system decisions. The Router also monitors the readout chip de-randomising buffer usage and issues the appropriate busy to the DAQ control. Additional memory is contained to provide multi-event buffering. An additional data path has been supplied to enable spying on the event data.
The control, parameter loading and testing of the front end chip is realised by JTAG. A JTAG controller is incorperated in the Router module. Currently two solutions for making the JTAG connection between the Router module and Pilot chip are under evaluation. Either to use a short copper link of <50 metres or employing a second optical fibre link which would not have such a length constraint.
Id: 92
Corresponding Author: Orlando VILLALOBOS
BAILLIE
Experiment: ALICE
Sub-system: Trigger
Topic: Trigger Electronics
Updated Design for the ALICE Central Trigger
I.J. Bloodworth [1], G. Di Marzo [2], D. Evans
[1], P. Jovanovic [1],
A. Jusko [3], J.B. Kinson [1], A. Kirk [1],
V. Lenti [4], M. Luptak [3],
L. Sandor [3], P. Vande Vyvre [2] and O. Villalobos
Baillie [1]
for the ALICE collaboration.
1. School of Physics and Astronomy, The University of Birmingham, Edgbaston, Birmingham, UK B15 2TT
2. CERN, European Organization for Nuclear Research, CH-1211 Geneva 23, Switzerland.
3. Dipartimento di Fisica dell' Universita and Sez. INFN, Bari, Italy
4. Institute of Experimental Physics, Slovak Academy of Sciences, Kosice, Slovakia.
Abstract:
The trigger and data acquisition systems in
the ALICE experiment have undergone significant changes in the last year.
This is (i) in response to the incorporation of new detectors, (ii) the
result of the use of front-end buffering schemes in the ALICE sub-detectors,
and (iii) because of new more pessimistic estimates of the data volume
generated by the Time Projection Chamber (TPC). In this report, we review
the specification for the updated ALICE Central Trigger and examine how
it might be implemented using currently available electronics components.
The User Requirement Document and the Technical
Specification for this system are being discussed by the ALICE collaboration.
Summary:
The original trigger concept for the ALICE experiment, as described in the ALICE Technical Proposal, has undergone substantial modifications over the last year as a result of new requirements. These include the addition of new detectors, the decision by the sub-detector groups to use front-end buffering as a means of reducing peak data flow rates to the data-acquisition system, and new, more pessimistic estimates of the data volume from the TPC.
The first step towards a new description of the trigger system came in 1999 with the definition of the signal sequence for communication between the Central Trigger and the sub-detectors. Since then, a much more detailed description of the logical operation of the trigger system has been prepared. Triggers are defined in terms of trigger "classes", the function of which can be explained with a few examples. A trigger class is identified by a given pattern of trigger inputs, and specified that, if it is activated, a trigger should be sent to a specified set of sub-detectors.
The trigger system in ALICE includes a provision
for past-future protection for each sub-detector, to avoid event pile-up.
Each sub-detector has a specific time window inside which past-future protection
should be applied. Past-future protection can be applied uniformly
to a trigger class, since the failure of any detector in a class
invalidates the whole class.
The ALICE trigger is based on three trigger
levels: L0, L1 and L2. The L0 trigger is the earliest, and is issued
so as to arrive at the front-end electronics for each sub-detector at the
latest 1.2 microseconds after the interaction has taken place. The
latency is fixed. It is sent by the quickest possible method, namely a
dedicated coaxial cable. The L1 and L2 decisions are sent using the
RD-12 TTC system; L1 uses channel "A", again with a fixed latency,
and L2 is sent as a broadcast using channel "B". The normal operation
of the TTC allows for the transmission of a trigger number following a
channel "A" trigger pulse. In ALICE, this is set to be the orbit number
and the bunch crossing number, in order to have an event identifier which
is
common for all sub-detectors.
Calibration triggers are also being considered. In most cases, calibrations which cannot be performed outside normal physics runs must nonetheless take place when there can be no collision. The simplest way to ensure this is to schedule them to take place in the large gap in the LHC bunch structure, when no collisions take place. Calibration requests can be made, which define a special trigger class, typically consisting of just one detector, and the triggers can be flagged so as to allow the front-end electronics to perform special tasks, e.g. to suspend zero suppression. The method for communicating a calibration request to the Central Trigger is under discussion.
Id: 99
Corresponding Author: Bernardo MOTA
Experiment: ALICE
Sub-system: Tracker
Topic: Electronics for Trackers
Digital Implementation of a Tail Cancellation Filter for the Time Projection Chamber of the ALICE Experiment
R.E.Bosch, B. Mota, L. Musa
CERN, Geneva (Switzerland)
FOR THE ALICE COLLABORATION
Abstract:
In the ALICE TPC, the readout chambers are conventional multiwire proportional chambers with cathode pad readout. The pad signal has a rather complex shape, which depends on the details of the chamber and the pad geometry, characterized by a long tail due to the motion of the positive ions. Since the zero suppression has to be done before the data transfer, the high channel occupancy calls for a very precise tail suppression. In order to be compatible with the required dE/dx resolution, a suppression to 0.1% or better of the maximum pulse height, is required. We present a digital implementation of a shortening filter based on the approximation of the tail by the sum of exponential functions.The hardware implementation of the filter is described and the results analyzed.
Summary:
The ALICE TPC, of cylindrical shape, will be 500cm long, subdivided into two drift spaces of 250cm by a central plane, and extends in the radial direction from 84cm radius out to 247cm. The image charge is detected by 570 000 pads located on two readout planes at the cylinder end-caps. The readout planes are based on conventional multiwire proportional chambers with cathode pad readout. The chambers deliver on their pads a current signal with a fast rise time (less than 1ns), and a long tail due to the motion of the positive ions. For every pad, the current is integrated and subsequently shaped by a shaping amplifier. The pulse-height spectrum covering a maximal drift time of 88us is sampled at about 6MHz. The large granularity of the ALICE TPC (about 3 x 10^8 pixels) leads to a large event size (300MByte) and a data volume in the front-end that, at a trigger rate of 200Hz required for the ALICE physics program, is far beyond the limit of the present data handling techniques. Therefore, the zero suppression has to be done in the front-end electronics before the data is transferred to the DAQ system. Moreover, the ALICE TPC will cope with an extremely high charged particle multiplicity. A typical central Pb-Pb event, for instance, will produce about 3x10^4 tracks in the detector acceptance, which correspond to an occupancy of 40% in the inner most regions of the TPC. Therefore, in order to perform effectively the zero suppression, the pile-up effects have to be minimized and, consequently, the long signal tail has to be suppressed very precisely. In order to be compatible with the required dE/dx resolution, a suppression of 0.1% of the maximum pulse height, is required.
The pad signal has a rather complex shape that depends on the details of the chamber and the pad geometry. The 1/t tail behavior from a closed proportional tube is replaced by a bipolar signal due to the particular motion of the positive ions relative to the pad and wire planes. The negative undershoot reaches several per mille of the peak pulse height and falls into the normal drift time regime of a TPC. The measured TPC signal can be fitted, with the required accuracy, by the sum of N exponential functions. The latter can be expressed as the convolution of the initial impulse charge and a signal transfer function corresponding to the sum of the exponential terms. The cancellation of the tail is then realized by deconvolution filtering technique.
The accuracy of the filter realized as analog
network is limited by the tolerance of its components. Owing to the poor
precision in the matching of the passive elements, provided by the actual
integrated circuit technologies, an analog implementation of the filter
cannot reach an accuracy of 0.1% if the use of external tunable components
has to be avoided. On the other hand, a digital system allows much better
control of the accuracy requirements by choosing the word length and type
of arithmetic (fixed point versus floating point). Furthermore, a digital
system allows flexibility in reconfiguring the digital signal processing
operations by changing programmable coefficients. This is indeed extremely
important, considering that the exact shape of the signal is known with
high accuracy only when the detector is operated. Moreover, this allows
some flexibility in the choice of the gas composition and drift field depending
on first running experiences. A N-1 order digital filter can be deduced
in a way that N-1 of the poles of the signal transfer function are cancelled.
The remaining exponential is the fastest and it allows the output to reach
0.1% of the maximum pulse height after 1 to 2 microseconds. Since the digital
filter is part of the front-end electronics, it has to be fast, in order
to process a new sample each 6MHz clock cycle, and sufficiently small for
cost and power consumption reasons. A 16-bit words and fixed-point arithmetic
is consistent with the 0.1% accuracy. Preliminary synthesis of a 2nd order
filter with the standard cells library of a 0.35um CMOS process leads to
a circuit of about 1500 gates, and a propagation delay below 100ns.
This circuit showed the required accuracy
on measured detector signals
Id: 100
Corresponding Author: Jacques LECOQ
Experiment: ALICE
Sub-system: Trigger
Topic: Trigger Electronics
A front end ASIC for the Dimuon arm trigger of the ALICE experiment
Laurent Royer, Gerard Bohner, Jacques
Lecoq
For the ALICE collaboration
LPC Clermont-Ferrand
A first prototype of the front-end ASIC dedicated to the trigger detector of the dimuon arm of ALICE has been designed and tested in the Laboratoire de Physique Corpusculaire of Clermont-Ferrand.
This setup is based on the Resistive Plate Chamber (RPC), a gaseous detector which can be operated either in streamer or avalanche mode. The streamer mode has the advantage of providing large signals that can be discriminated without amplification whereas the avalanche mode presents a better rate capability and time resolution with conventional discrimination techniques.
Since we proposed to operate the RPCs in streamer mode in ALICE, we have studied a new discrimination technique in order to obtain a time resolution better than 2ns in this mode. The method used in this dedicated circuit is described, performances and tests results are given, as well as the evaluation done in the test beam of summer 2000.
Summary:
The trigger system of the dimuon arm of the ALICE/LHC detector has to select events containing two muons from the decay of heavy resonances like J/Y or ¡, amongst all background sources. The setup is composed of 72 Resistive Plate Chambers (RPC), a gaseous detector where the electrical charge produced by the crossing of a charged particle is collected on 1-4 cm wide, 35-70 cm long, strip lines. Almost 21 000 readout channels are necessary to cover the whole detector area.
RPCs are operated in streamer mode in ALICE and no amplification of the analog signal is needed. The analog signal picked up on the strips has to be discriminated and then shaped with a width of about 20 ns. The output signals of all readout channels are sent in parallel through 20 m long cables to the trigger electronics. A sampling at the LHC clock frequency (40 MHz) is performed at this level before the dimuon trigger decision is issued.
Using conventional discrimination techniques, the time resolution is better when using RPC in avalanche mode (commonly 1ns), unless the RPC is operated in streamer mode at quite high running voltages that is not suitable. In order to improve the time resolution in streamer mode, a new discrimination technique called "ADULT" has been studied.
The observation of RPC pulse shapes in streamer mode shows that the streamer signal itself is preceded by a smaller signal, called "avalanche precursor". The streamer signal exhibits important time fluctuations while the avalanche precursor is almost stable.
The ADULT technique exploit this good timing property of the avalanche precursor with the validation by the large streamer signal which is well above any source of noise. The technique makes use of two discriminators, with a low threshold (typically 10 mV/50 ohms) at the level of the avalanche precursor and a high threshold (typically 80 mV/50 ohms) at the level of the streamer. It is followed by a coincidence of the two outcoming signals with the time reference given by the low threshold one.
This dedicated discrimination technique has been implemented in a front end chip developed in the "Laboratoire de Physique Corpusculaire" of Clermont-Ferrand. The chosen technology is AMS BiCMOS 0.8mm.
The chip prototype is composed of one
channel including the "ADULT" discrimination technique and additional functions
:
-an "one-shot" system which prevents
the chip from re-triggering during 100ns,
-a remote delay with a range of 50ns,
-a shaper to obtain a 20 ns logical
output signal,
-an ECL buffer to drive a 20 m twisted
pair cable.
Five packaged chips were delivered
in middle of May 2000. The tests in laboratory have shown that each stage
of the chip works perfectly. The power consumption is still a little bit
high (140mW per channel) but will be decreased by replacing the ECL driver
by a LVDS one.
The low threshold discriminator gives
the time reference until the delay between the avalanche precursor and
the streamer signals reaches 11 ns, which is enough regarding the actual
detector pulses.
The 20 ns ECL output signal can be
delayed in a range of about 60 ns and the one-shot protection is a little
bit longer (138 ns ) than the designed value.
A RPC equipped with 8 of these chips has been tested at the CERN/PS beam area at the beginning of July 2000. First results are presented in this paper, as well as possible improvements and foreseen developments of the chip.