Trigger Throttling System for CMS DAQ

A. Racz / CERN-EP

Abstract:

This document is a first attempt to define the basic functionnalities of the TTS in the CMS DAQ. Its role is to adapt the trigger pace to the DAQ capacity in order to avoid congestions and overflows at any stage of the readout chain. The different possibilities for the TTS to measure the load on parts of the chain are examined. It clearly appears that one part of the chain needs fast reaction time (few tens of useconds) whereas the rest of the chain can afford longer reaction time, available to nowadays processors.

First evaluation of neutron induced Single Event Effects on the CMS barrel muon electronics

S. Agosteo(1), L. Castellani(2), A. Favalli(1), I. Lippi(2), R. Martinelli(2) and P. Zotto(3)
1) Dip. di Ingegneria Nucleare (CESNEF) del Politecnico di Milano, Italy
2) Dip. di Fisica dell'Universit and sez. INFN, Padova, Italy
3) Dip. di Fisica del Politecnico di Milano and sez. INFN di Padova, Italy

Abstract:

Neutron irradiation tests of the currently available electronics for the CMS barrel muon detector were performed using thermal neutrons and fast neutrons at E < 11MeV. The Single Events Upset on the Static RAM was measured, while upper limits are derived for devices having experienced no failure. The results are used to guess the upper limits on the mean time between failures in the whole barrel muon detector.

SEU tests of an 80Mbit/s optical receiver

F. Faccio, K. Gill, M. Huhtinen, A. Marchioro, P. Moreira, F. Vasey
CERN, CH-1211 Geneva 23, Switzerland

G. Berger
Cyclotron Research Center, UCL, B-1348 Louvain-la-Neuve, Belgium

Abstract:

The sensitivity to SEU is presented for a rad-hard 80Mbit/s receiver developed for the CMS Tracker digital optical link. Bit Error Rate (BER) measurements were made while irradiating with 59MeV protons and 62MeV neutrons, for different angles to the beam and for a wide range of optical power in the link. The photodiode is the most sensitive element to SEU. Direct ionisation can explain the SEU rate for protons incident at high angles of incidence and nuclear interactions explain the SEU rate for incident neutrons, as well as for protons for the low angles of incidence and higher optical power.

Status of the 80Mbit/s Receiver for the CMS digital optical link

F. Faccio, C. Azevedo, K. Gill, P. Moreira, A. Marchioro, F. Vasey
CERN, CH-1211 Geneva 23, Switzerland

Abstract:

The first prototype of the 80Mbit/s optical receiver for the CMS digital optical link has been manufactured in a 0.25µm commercial CMOS process. Its performance satisfies the low power, wide dynamic range, and speed specifications. The required sensitivity (BER of 10^-12 for an optical power of -20dBm) is easily achieved, since this BER is obtained already at -27dBm. The radiation hardness has been verified irradiating the diode with 6 MeV neutrons (up to 6.5·10^14n/cm2) and the receiver circuit with 10KeV X-rays (up to 20 Mrad). Neither type of irradiation did sensibly modify the BER performance of the receiver.

LHC machine timing distribution for the experiments

B.G. Taylor, CERN for the RD12 Collaboration

Abstract:

At the LHC the 40.079 MHz bunch crossing clock and 11.246 kHz machine orbit signal must be distributed from the Prevessin Control Room (PCR) to the TTC systems of the 4 LHC experiments, to the test beam facilities in the West and North areas and to beam instrumentation around the ring.

To achieve this, a single high-power laser transmitter with optical fanout to all the destinations has been installed at the PCR. A standard TTC machine interface (TTCmi) has been developed which receives the signals and can deliver very low jitter timing signals to LHC experiment TTC distribution systems with multiple trigger partitions.

Development of a 24 ch TDC LSI for the ATLAS Muon Detector

Yasuo Arai, KEK, National High Energy Accelerator Research Organization, Institute of Particle and Nuclear Studies
and
T. Emura, Tokyo University of Agriculture and Technology

Abstract:

A TDC LSI for the ATLAS precision muon tracker (MDT) has been developed. A prototype chip (AMT-1) was processed in a 0.3 um CMOS Gate-Array technology. It contains full functionality of the final TDC.

To get a high resolution around 300 ps, an asymmetric ring oscillator and a PLL circuit are used. All the I/O signals which are active during measurement has LVDS interfaces. A JTAG interface is used for boundary scan and internal register setup. All the memory and control bits has parity bits so that a SEU can be detected. Radiation tolerance for Gamma-ray and Neutron are also reported.

Implementation of Sorting Schemes in a Programmable Logic

Mikhail Matveev (Rice University, Houston, TX 77005)

Abstract:

Trigger systems of each CMS muon subdetector (Cathode Strip Chambers, Drift Tubes, Resistive Plate Chambers) will have a muon sorter unit in their upper parts. We report on a design and simulation results for the following sorting schemes: "3 objects out of 18", "4 objects out of 8", "4 objects out of 24" and "4 objects out of 36". All designs are targeted to a single chip implementation based on Altera 20KE Programmable Logic Devices (PLD). The PLD internal sorting latency varies between 1 and 3 cycles of 40MHz clock frequency. Proposed schemes can be used for the fast sorting at the CMS Muon subsystems as well as other trigger systems at LHC experiments.

Single Event Upset Studies for the ATLAS SCT and Pixel Optical Links

D.G.Charlton, J.D.Dowell, R.J.Homer, P.Jovanovic, G.Mahout, H.R.Shaylor, J.A.Wilson
School of Physics and Astronomy, University of Birmingham,UK

R.L. Wastie, A.R. Weidberg
Physics Department, Oxford University, U.K.

J.K. troska, D.J. White
Rutherford Appleton Laboratory, U.K.

I-M Gregor
Physics Department, Wuppertal University, Germany.

Abstract:

The readout of the ATLAS SCT and Pixel detectors will use optical links. The radiation hardness of all the components has been extensively studied but this paper discusses the operation of these links in simulated LHC radiation environments. Nuclear interactions can deposit large amounts of energy in electronic components which can cause Single Event Upsets
(SEU). The SEU rates have been measured with MIPS from a beta source, low energy neutrons, pions and protons at PSI. The dominant source of SEU effects is from energy deposition in the active region of the PIN diodes.

Radiation Hard Optical Links for the ATLAS SCT and Pixel Detectors

D. Charlton, J.D.Dowell, R.J.Homer, P. Jovanovic, G.Mahout, H.R.Shaylor, J.A.Wilson.
School of Physics and Astronomy, University of Birmingham, Birmingham, B15 2TT, UK

I.M. Gregor, R.Wastie, A.R. Weidberg
Physics Department, University of Oxford, Keble Road, Oxford, OX1 3RH, UK.

S.Galagedera, M.C.Morrissey, J.Troska, D.J.White.
CLRC Rutherford Appleton Laboratory, Chilton, Didcot, Oxon, OX11 0QX, UK.

A.Rudge
CERN, Geneva, Switzerland.

M.L.Chu, S.C.Lee, P.K.Teng
Institute of Physics, Academia Sinica, Taipei, Taiwan 11529, Republic of China.

Abstract:

A radiation hard optical readout system designed for the ATLAS Semi-conductor Tracker (SCT) is described. Two independent versions of the front-end optical package housing two VCSEL emitters and an epitaxial Si PIN photodiode have been irradiated with neutron fluences over 1015 n.cm-2, the level encountered in the ATLAS pixel detector. Environmental tests have been performed down to -20o C. Extensive radiation and lifetime tests have also been carried out on the opto-electronic components and the front-end VCSEL driver and timing/control ASICs. Bit error rate and cross-talk measurements using irradiated devices show that the system easily meets the performance specification.

Measurements of Radiation Effects on the Timing, Trigger and Control Receiver (TTCrx) ASIC

Thomas Toifl, Paulo Moreira, Alessandro Marchioro
CERN

Abstract:

The Timing, Trigger and Control Receiver Asic (TTCrx) receives and distributes the clock, the trigger decision, and other synchronisation signals. In this paper the radiation-hard version of the TTCrx, manufactured in DMILL technology, is discussed. First, the architecture of the circuit is described, where we concentrate on the changes to the existing prototype and on the measures taken to increase robustness with respect to single event upsets (SEU). In the second part we will present measurements of the circuit characteristics before and after irradiation with gammas and neutrons. In the last part we will then show measurements of the SEU behavior.

The CMS DT Muon DDU: a PMC based interface between frontend and data-acquisition

F.Benotto, F.Bertolino, R.Cirio, G.Dellacasa
INFN Torino

Abstract:

CMS will use gas drift tubes as active part of the barrel muon sub-detector. In total 200.000 wires will be readout by TDCs and signals will be sent to data acquisition. The entrance door to the standard CMS DAS will be a board (Detector Dependent Unit - DDU) that will be specific to each sub-detector. We have built a PMC based prototype of the DT muon DDU that features two input channels with Optolink, data check and reconstruction with FPGA and PCI slave output through a FIFO. A description of the board and the FPGA schematics will be given and results from lab tests will be shown.

Project status of the CMS tracker optical links

F. Vasey, C. Azevedo, T. Bauer(1), B. Checucci(2), G. Cervelli, K. Gill,
R. Grabit, F. Jensen, A. Zanet
CERN, Geneva (Switzerland)
(1)HEPHY, Vienna (Austria)
(2)INFN, Perugia (Italy)

Abstract:

The development phase of the optical data transfer system for the CMS tracker is now complete. This paper will present the project status and review the preparation for production. In particular, it will focus on the results of the market surveys for front-end components, and on the performance evaluation of a close-to-final readout chain.

Calibration of the ATLAS Hadronic End-Cap Calorimeter

H. Brettel, W.D. Cwienk, L. Kurchaninov, H. Oberlack, P. Schacht
(Max-Plank-Institute for Physics, Munich, Germany)

A. Jusko, P. Strizenec
(Institute of Experimental Physics SAS, Kosice, Slovakia)

On behalf of the ATLAS HEC Collaboration

Abstract:

The calibration chain of the ATLAS HEC is described. A model based on detailed studies of all individual parts is presented.

The characteristics of the steering and data taking system for both the test-beam runs and for the acceptance tests of the HEC modules is summarized.

The calibration and signal reconstruction procedure is developed and results of the test-beam data are presented.

Radiation Test of CMS Endcap Muon Front-end Electronics with 63 MeV Protons

T.Y. Ling

Abstract:

After brief overview of the CMS EMU electronics system, results on Single Event Effects, TID and Displacement Effects due to neutron and ionizing radiation will be reported. These results are obtained by irradiating the front-end electronics boards with 63 MeV protons. During the irradiation, the electronics board was fully under power, all ASICs and COTS on the board were active and the data was readout in the same way as designed for CMS.

Silicon DAQ based on FPDP and RACEway

PHOBOS collaboration

Abstract:

DAQ for Si-detector of PHOBOS setup (RHIC) with Scalable Power for read out and Zero Suppression is described. Data from VA-HDR chips with analog multiplexor, are digitized by FADC. Digital buffers are multiplexed by DMU modules at speed 100 MBytes/sec and transmitted through FPDP and virtual extender of FPDP to fiber (FFI).

At the receiver end (in counting house) data from fiber are distributed between a number of dedicated processors (in RACEway multiprocessor frame) for Zero Suppression. After ZS data are concatenated and transmitted to Event Builder.

Optical Data Transmission from the CMS Cathode Strip Chamber Peripheral Trigger Electronics to Sector Processor Crate

N.Adams, M.Matveev, T.Nussbaum, P.Padley (Rice University)
J.Hauser, V.Sedov (UCLA)

Abstract:

Data representing three muons will be sent from each sector of the CMS Cathode Strip Chambers to the Sector Processor crate residing in the counting room 100 m apart of the detector. We report on the data transmission scheme based on Agilent HDMP-1022/1024 serializer/deserializer chipset and Methode MDX-19 optical transceivers. Six chipsets and six pairs of optical modules are needed in order to transmit 120 bits of data every 25 ns of the main LHC frequency from the peripheral Muon Port Cards to Sector Receiver modules. Results of prototyping, laboratory tests as well as a possible future options for data transmission are discussed.

Recent Progress in Field-Programmable Logic

Peter Alfke, Director, Applications Engineering, Xilinx, Inc

Abstract:

1. Programmable logic for ultra-low power applications. CPLDs operating with a few microamps of supply current, and FPGAs retaining configuration and register content with less than 100 microamps of supply current. An autoranging 400 MHz six-digit frequency counter consumes <2 mA in idle, <40 mA at 400 MHz input frequency.

2. FPGAs with > 1 Mbit of dual-ported on-chip RAM. FIFOs up to 1024 deep, 64 bits wide ( or wider), clocked at >150 MHz with independent read and write clocks

3. LVDS and LVPECL interfaces running at 622 MHz data rate, and recent developments at GHz serial data I/O.

4. Recent and ongoing experiments with radiation-hardened FPGA.

Performance of a Prototype Track-Finding Processor for the Level-1 Trigger of the CMS Endcap Muon System

D. Acosta, A. Madorsky, B. Scurlock, S.M. Wang, University of Florida
A. Atamanchuk, V. Golovtsov, B. Razmyslovich, St. Petersberg Nuclear Physics Institute

Abstract:

We report on the development and performance of a prototype track-finding processor for the Level-1 trigger of the CMS endcap muon system. The processor links track segments identified in the cathode-strip chambers of the endcap muon system into complete three-dimensional tracks. It then measures the transverse momentum of the best track candidates from the sagitta induced by the magnetic bending. The processor logic for the prototype is implemented in high-density FPGAs and SRAM memory. It receives approximately 3 gigabytes of data every second from a custom backplane operating at 280 MHz. Test results of the prototype are consistent with expectation.

First-Level End-Cap Muon Trigger System for ATLAS

K. Hasuko, T. Kobayashi, T. Niki, D. Toya, Y. Katori (University of Tokyo)
O. Sasaki, M. Ikeno, T.K. Ohska (High Energy Accelerator Research Organization KEK),
C. Fukunaga, H. Kano (Tokyo Metropolitan University),
H. Sakamoto, S. Nishida (Kyoto University),
H. Kurashige and R. Ichimiya (Kobe University)

Abstract:

We present the first-level end-cap muon trigger system for ATLAS. The system has the main tasks which are to identify bunch crossings and to make trigger decisions for high transverse-momentum muon candidates. It is being developed under requirements on trigger electronics: e.g. trigger rate, latency, acceptable number of tracks, etc. Such the requirements, trigger scheme, and overview of trigger logic are shown in this presentation. Details of the logic are given in the following presentation.

DILOGIC-2 A SPARSE DATA SCAN READOUT PROCESSOR FOR THE HMPID DETECTOR OF ALICE

H. Witters, IMEC vzw, 3001 Leuven, Belgium (witters@imec.be)
J.C. Santiard, CERN, Geneva, Switzerland (jean-claude.santiard@cern.ch)
Paolo Martinengo, CERN, Geneva, Switzerland (paolo.martinengo@cern.ch)
For the ALICE collaboration

Abstract:

Processing of analog information are always spoiled by additional DC level and noise given by the sensors or their additional readout electronic. The Dilogic-2 ASIC circuit has been developed in a 0.7um n-well CMOS technology to process the data given by Analog to Digital Converters, in order to eliminate the empty channels, to subtract the base line (pedestal) and store locally the true analog information.

Timing, Trigger and Control distribution and dead-time control in ATLAS

Abstract:

The RD12 TTC system is the backbone for the timing, trigger and control distribution in ATLAS. The last developments of TTC modules as well as their use in ATLAS will be presented.

The strategy for the dead-time control of the experiment will also be presented.

Custom chips developed for the trigger/readout system of the ATLAS end-cap muon chambers

H.Kano, C.Fukunaga, Tokyo Metropolitan University,
M.Ikeno, O.Sasaki, T.K.Ohska, KEK (National Organization for high energy accelerator physics),
R.Ichimiya, H.Kurashige, Kobe University,
S.Nishida, H.Sakamoto, Kyoto University,
K.Hasuko, Y.Katori, T.Kobayashi, T.Niki, and D.Toya, University of Tokyo

Abstract:

Three custom ASICs are now being developed for the trigger/readout system of the ATLAS end-cap muon chambers. Each chip is the master component in three out of four subparts of the system. Beside the standard circuitry as an ATLAS subsystem, several implementations have been devised in each chip, which are required from various physical and boundary conditions as an electronics system for the end-cap muon chambers. We discuss the implementation of the level-1 muon identification logic as well as these customarily developed data handling technology

Readout system for the CMS RPC Muon Trigger

Krzysztof Kierzkowski a), Ignacy M. Kudla a), Esko Pietarinen b), Michal Pietrusilski a), Krzysztof Pozniak c)
a) Warsaw University, Institute of Experimental Physics,
b) Univ.of Helsinki Fac.of Science, Helsinki Institute of Physics HIP,
c) Warsaw University of Technology, Institute of Electronics Systems

Abstract:

The CMS detector will have a dedicated subdetector (RPC chambers) to identify muons, measure their transverse momenta pt, and determine the bunch crossing from which they originate. Trigger algorithm is based on muon track search and classification in raw data from the RPC chambers. Trigger system can be built in the control room (far away from detector) where all trigger data are concentrated. Dedicated synchronous compression/decompression algorithm is used to sent all data for each bunch crossing via optical links. Readout system uses the same data as Trigger system and will be placed in Trigger Rack. The idea of readout system and its limitations are discussed. Paper includes description of prototype boards and test results on synchronous CERN test beam.

Study of LVDS Serial Links for the ATLAS Level-1 Calorimeter Trigger

G.Anagnostou, P.Bright-Thomas, J.Garvey, R.Staley, W.Stokes, S.Talbot, P.Watkins, A.Watson
University of Birmingham, Birmingham, UK

R.Achenbach, P.Hanke, D.Husmann, M.Keller, E.-E.Kluge, J.Krause, K.Mahboubi, R.Megele, K.Meier, U.Pfeiffer, V.Schatz, K.Schmitt, C.Schumacher, B.Stelzer, O.Stelzer, P.Stock, E.Ulses
University of Heidelberg, Heidelberg, Germany

B.Bauss, K.Jakobs, U.Schaefer, J.Thomas
University of Mainz, Mainz, Germany

E.Eisenhandler, W.R.Gibson, M.P.J.Landon
Queen Mary and Westfield College, London, UK

B.M.Barnett, I.P.Brawn, J.Edwards, C.N.P.Gee, A.R.Gillman, R.Hatley, K.Jayananda, V.J.O.Perera, A.A.Shah, T.P.Shah
Rutherford Appleton Laboratory, Chilton, Didcot, UK

C.Bohm, M.Engstrom, S.Hellman, S.B.Silverstein
University of Stockholm, Stockholm, Sweden

Abstract:

This paper presents an evaluation of the proposed LVDS serial data transmission scheme for the ATLAS level-1 calorimeter trigger. Approximately 7000 high-bandwidth links are required to carry data into the level-1 processors from the preprocessor crates. National Semiconductor's Bus LVDS serialiser/deserialiser chipsets offer low power consumption at low cost and synchronous data transmission with minimal latency. Test systems have been built to measure real-time bit error rates using pseudo-random binary sequences. Results show that acceptable error rates better than 10^-13 per link can be achieved through compact cable connector assemblies over distances up to 20m.

Test results of the ALICE SDD electronic readout prototypes

G. Mazza[INFNTo], G. Alberici[INFNTo], G. Anelli[CERN], G.C Bonazzola[UniTo],
D. Cavagnino[UniTo], P.G. Cerello[INFNTo], P. De Remigis[INFNTo],
D. Falchieri[INFNBo], A. Gabrielli[INFNBo], E. Gandolfi[INFNBo],
P. Giubellino[INFNTo], M. Masetti[INFNBo], L.M. Montano[INFNTo],
D. Nouais[INFNTo], A. Rivetti[CERN][UniTo], F. Tosello[INFNTo],
A. Werbrouck[UniTo], R. Wheadon[INFNTo]
for the ALICE collaboration

Institutes :
[INFNTo]        INFN sezione di Torino, Italy
[INFNBo]        INFN sezione di Bologna, Italy
[UniTo]         Universita` di Torino, Italy
[CERN]          CERN, Geneve, Switzerland

Abstract:

The first prototypes of the front-end electronic of the ALICE silicon drift detectors has been designed and tested. The integrated circuits have been designed using state-of-the-art technologies and, for the analog parts, with radiation-tolerant design techniques. In this paper the test results of the building blocks of the PASCAL chip and the first prototype of the AMBRA chip are presented. The prototypes fully respect the ALICE requirements; owing to the use of deep-submicron technologies together with radiation-tolerant layout techniques, the prototypes have shown a tolerance to a radiation dose much higher than the one foreseen for the ALICE environment.

Low Noise Amplifier

J.D. Schipper, NIKHEF R. Kluit,NIKHEF

Abstract:

As a design study for the LHC experiments a 'Low Noise Amplifier Shaper' for capacitive detectors is developed. This amplifier is designed in 0.6 um technology from AMS. The goal was to design an amplifier with a noise contribution of 250 electrons, a 12 electrons per pF contribution from the input capacitor and a relative high gain. A test chip with two versions of the amplifier, a 'radiation tolerant' (gate-around FET's) and a 'normal' version has been fabricated and is now under test. These designs and there characteristics, simulated and measured, will be compared and discussed.

Single Event Upset measurements on the Resistive Plate Chambers Front-End chip for the Compact Muon Solenoid experiment

S. Altieri(1), G. Bruno(1), F. Loddo(2), A. Ranieri(2), P. Vitulo(1)
(1)Dipartimento di Fisica Nucleare e Teorica dell'Università di Pavia e I.N.F.N. Sezione di Pavia
(2)Dipartimento Interateneo dell'Università di Bari e I.N.F.N. Sezione di Bari

Abstract:

A measurement of irradiation damaging has been made on the analog front-end electronics of the RPC detector in the CMS experiment. The measurements were performed according to the estimated neutron fluence foreseen in the most irradiated area of the apparatus. The test results are shown, considering all the possible irradiation effects on the custom RPC front-end electronics, encouraging us on the use of the 0.8m Bi-CMOS technologies from AMS, chosen for such type of application.

A Demonstrator for the ATLAS Level-1 Muon Trigger Interface to the Central Trigger Processor

A. Corre, N. Ellis, P. Farthouat, Y. Hasegawa, G. Schuler, C. Schwick, R. Spiwoks
CERN

Abstract:

The Level-1 Muon Trigger Interface (MUCTPI) to the Central Trigger Processor (CTP) receives trigger information from the detector- specific logic of the muon trigger. This information contains up to two muon-track candidates per sector. The MUCTPI combines the information of all sectors and calculates total multiplicity values for each of six pT thresholds. It avoids double counting of single muons by taking into account that some of the trigger sectors overlap. The MUCTPI sends the multiplicity values to the CTP which takes the final Level-1 decision. For every Level-1 Accept the MUCTPI sends region-of-interest information to the Level-2 trigger and event data to the data acquisition system. A demonstrator of the MUCTPI has been built which has the performance of the final system but uses a simplified algorithm for calculating the overlap. The functionality and the performance of the demonstrator are presented.

The Trigger Menu Handler for the ATLAS Level-1 Central Trigger Processor

N. Ellis, P. Farthouat, G. Schuler, R. Spiwoks
CERN

Abstract:

The role of the Central Trigger Processor (CTP) in the ATLAS Level-1 trigger is to combine information from the calorimeter and muon trigger processors, as well as from other sources, e.g. calibration triggers, and to make the final Level-1 decision. The information sent to the CTP consists of multiplicity values for a variety of pT thresholds, and of flags for ET thresholds. The algorithm used by the CTP to combine the different trigger inputs allows events to be selected on the basis of menus. Different trigger menus for different run conditions have to be considered. In order to provide sufficient flexibility and to fulfil the required low latency, the CTP will be implemented with look-up tables and programmable logic devices. The trigger menu handler is the tool that translates the human-readable trigger menu into the configuration files necessary for the hardware, stores several prepared configurations and down-loads them into the hardware on request. An automatic compiler for the trigger menu and a prototype of the trigger menu handler have been implemented.

Development of HERA-B high-pT level-0 trigger logic system

H.Riege, J.Schutt, R.van Staa
II Institut fur Experimentalphysik Universitat Hamburg, Germany

V.Popov
Institute for Theoretical and Experimental Physics, Moscow, Russia

Abstract:

High-pt trigger has been developed for the HERA-B fixed target experiment as complementary option to the basic trigger. It increases considerably the number of B mesons decay channels detectable by the experiment. The high-pt trigger performs fast and effective selection of particles with high transverse momenta. Trigger system includes three layers of gaseous chambers placed in the magnetic field with 19000 readout channels. Hit information is being transfered from the chambers to the trigger logic via high-speed optical link lines. Selection algorithm is performed by the dedicated logic electronics which allows to select O(107) events out of 1012combinations per second. Pretrigger logic consists of a number of sections. Selection capability of the pretrigger logic is on average 16 events from 192000 combinations each 96 ns (time interval between two consequent bunches). Various tests of hardware prototypes have been done. The commissioning of the high-pt trigger logic system is on-going.

PERFORMANCE AND RADIATION TESTING OF A LOW NOISE SWITCHED CAPACITOR ARRAY FOR THE CMS ENDCAP MUON CHAMBERS

R.E. Breedon, B. Holbrook, Winston Ko, D. Mobley, P. Murray, S.M. Tripathi
University of California, Davis, CA 95616 USA

Abstract:

The 16-channel, 96-cell per channel switched capacitor array (SCA) ASIC developed for the cathode readout of the cathode strip chambers (CSC) in the CMS endcap muon system is ready for production. For the final full-sized prototype, the Address Decoder was re-designed and LVDS Receivers were incorporated into the chip package. Under precision testing, the chip exhibits excellent linearity within the 1V design range and very low cell-to-cell pedestal variation. Performance of the SCA during beam tests of a fully-instrumented chamber and results from radiation testing at a 63.3 MeV proton cyclotron will be presented.

Instrumentation amplifiers and voltage controlled current sources for LHC cryogenic instrumentation

J. A. Agapito(3), F. M. Cardeira(2), J. Casas(1), A. P. Fernandes(2), F. J. Franco(3), P. Gomes(1), I. C. Goncalves(2), A. Hernandez Cachero(3), J. Lozano(3), M. A. Martin(3), J. G. Marques(2), A. Paz(3), A. J. G. Ramalho(2), M. A. Rodriguez Ruiz(1) and J. P. Santos(3).
1 CERN, LHC Division, Geneva, Switzerland.
2 Instituto Tecnol¢gico e Nuclear (ITN), Sacav‚m, Portugal.
3 Universidad Complutense (UCM), Electronics Dept., Madrid, Spain.

Abstract:

Two different topologies for the basic instrumentation amplifier have been studied. Both amplifier and current source circuits have been designed, constructed and tested under radiation. All radiation campaigns have been carried out in ITN (Portugal) research nuclear reactor. A new facility for neutron beam extraction has been constructed. On line measurements of the offset voltages, offset currents, closed loop gain, and bias currents have been performed on the two structures for two different operational amplifiers, OPA124 & TLE2071. A study of the influence of each individual parameters to the whole has been carried out. Three voltage controlled current sources have been made with every instrumentation amplifier. Three values of current for each set of amplifiers have been fixed, adjusted to the different ranges of measurement of the cold mass temperature sensor. On line measurements of the currents are presented as a function of neutron radiation. And finally on line measurements of commercial voltage references are presented as a function of radiation.

Development of Fluorocarbon Evaporative Cooling Recirculators and Controls for the ATLAS Pixel and Semiconductor Tracking Detectors

C. Bayer (Wuppertal), M. Bosteels (CERN), P. Bonneau (CERN), H. Burckhart (CERN), D. Cragg (RAL), R. English (RAL), G. Hallewell (RAL/CPPM), B. Hallgren (CERN), S. Kersten (Wuppertal), P. Kind (Wuppertal), K. Langedrag (Oslo), S. Lindsay (Melbourne), M. Merkel (CERN), S. Stapnes (Oslo), J. Thadome (Wuppertal), V. Vacek (CERN/Czech Technical University, Prague)

Abstract:

We report on the development of evaporative fluorocarbon cooling recirculators and their control systems for the ATLAS Pixel and Semiconductor Tracking (SCT) detectors. A prototype circulator uses a hermetic, oil-less compressor and C3F8 refrigerant. The mass flow rate to each circuit is individually tuned via feedback according to the circuit load variation, using dome-loaded pressure regulators in the liquid supply lines piloted with analog compressed air from DAC-driven voltage to pressure ("V2P") converters. Evaporated C3F8 exits each circuit through an analog air-piloted back-pressure regulator, which sets the circuit operating temperature. A hard-wired thermal interlock system automatically cuts power to individual silicon modules should their temperature exceed safe values.

All elements of the circulator and control system have been implemented in prototype form. Temperature, pressure and flow measurement in the circulation system uses standard ATLAS CanBus LMB ("Local Monitor Box") DAQ and CanBus interfaced DACs in a large (300 + channel) multi-drop Can network administered through a BridgeView user interface. Prototype 16 channel interlock modules have been tested.

The performance of the circulator under steady state, partial-load, and transient conditions is discussed and future developments are outlined.

Design and test of a readout chip for LHCb

Niels van Bakel, Jo van den Brand, Hans Verkooijen (Free University of Amsterdam / NIKHEF Amsterdam)

Daniel Baumeister, Werner Hofmann, Karl-Tasso Knoepfle, Sven Loechner, Michael Schmelling, Edgar Sexauer (Max-Planck-Institute for Nuclear Physics, Heidelberg)

Martin Feuerstack-Raible (University of Heidelberg)

Neville Harnew, Nigel Smale (University of Oxford)

Abstract:

For the LHCb experiment a first prototype of a 128 channel analogue pipeline chip, named Beetle, has been developed and submitted in a standard 0.25 um CMOS process.

It integrates 128 channels with charge sensitive preamplifiers and shapers, whose outputs are sampled with 40 MHz into an analogue pipeline with a maximum latency of 160 sampling intervalls. A comparator behind the shaper provides a binary signal. The 128 channels can be multiplexed on either 4, 2 or 1 outputs. The bias settings are programmable and monitorable via a standard I2C-interface. The architecture of the chip is described as well as simulation and test results are presented.

Overview of the ATLAS Policy on Radiation Tolerant Electronics

Martin Dentan, CERN & CEA-DAPNIA
Philippe Farthouat, CERN

Abstract:

ATLAS Sub-systems will integer a very large quantity and variety of electronics boards which will be submitted to radiations ranging from few krads and few 1E10 n/cm2 to few 10 Mrads and few 1E14 n/cm2, and to energetic particles capable of producing SEE (Single Event Effects). ATLAS Technical Coordination has developed in collaboration with the Sub-systems a new policy on radiation tolerant electronics. It provides guidelines for the pre-selection and for the qualification of all the commercial electronics components that will be used in ATLAS, in order to make sure they will resist to the foreseen radiation constraints. This paper summarises the main guidelines given in the ATLAS Policy on Radiation Tolerant Electronics, and the benefits resulting from this policy.

A MIXED SIGNAL ASIC FOR THE SILICON DRIFT DETECTORS OF THE ALICE EXPERIMENT IN A 0.25 UM CMOS

A. Rivetti (1,2), G. Anelli(1), F. Anghinolfi(1), G. Mazza,(2) P. Jarron(1)
(1)CERN, CH-1211 Geneva 23, Switzerland
(2)INFN, Sezione di Torino, Via Pietro Giuria 1, 10125, Torino, Italy

Abstract:

A mixed signal integrated circuit developed for the read-out of Silicon Drift Detectors (SDDs) is presented.

The chip contains 32 channels and 16 ADCs. Each channel is made of an amplifier and an analog pipeline with 256 cells. One ADC is shared by two adjacent channels. The circuit is optimized to match the specifications of the SDDs of the ALICE experiment, where large dynamic range and low power consumption are key issues. The input noise is calculated to be 200 e- rms for an input capacitance of 3pF and a detector dark current of 10nA. The power consumption is 5mW/channel.

Implementation of a Serial Protocol for the Liquid Argon Atlas Calorimeter (SPAC)

F.Hubaut, B.Laforge, O.Le Dortz, D.Martin, Ph. Schwemling
LPNHE Paris

Abstract:

The Serial Protocol for the Atlas Calorimeter (SPAC) has been designed to provide the loading and reading of all parameters of the front-end boards of the ATLAS Liquid Argon Calorimeter.

This single master / multiple slaves serial protocol is designed to be transmitted optically and electrically, at up to 10 Mbits/s, and enables broadcast or individual transfers from the master to one or a set of slaves.

Some test results about the SPAC performance and its implementation within the ATLAS framework will be presented.

A FAST BINARY FRONT-END IMPLEMENTED IN A 0.25 UM CMOS TECHNOLOGY USING A NOVEL CURRENT-MODE TECHNIQUE

D. Moraes(1), F. Anghinolfi(1), P. Deval(2), P. Jarron(1), A. Rivetti(1).
(1)CERN, CH-1211 Geneva 23, Switzerland.
(2)MEAD Microlectronics S.A., Venoge 7, 1025 St. Sulpice, Switzerland.

Abstract:

A prototype of an IC has been developed with a very fast and low noise preamplifier, using a 0.25micron CMOS technology. The prototype contains a low- and high gain version of the preamplifier. It was designed to have an input impedance below 10 Ohms and an peaking time of 10ns at an input capacitance of 20pF. The low gain version was specially developed to be used on the Cathode Pad Chambers of the LHCb Muon System, where a very low threshold combined with high speed and low noise are required in order to obtain high efficiency and good time resolution.

Developments for Rdaiation Hard Silicon Detectors by Defect Engineering - Results of the CERN RD48 (ROSE) Collaboration

Gunnar Lindstroem (cospokesman of RD48) on behalf of the RD48 collaboration

Abstract:

The success of the Oxygen enrichment of FZ silicon as a highly powerful defect engineering technique and its optimization with various commercial manufacturers are reported. Major focus is on the changes of the effective doping concentration (depletion voltage). Other aspects (reverse current, charge collection) are covered too. Diode characteristics of test pad- and LHC-strip detectors are compared. The RD48 model for the dependence of radiation effects on fluence, temperature and operational time is verified; projections to operational scenarios for main LHC experiments demonstrate vital benefits. Present microscopic understanding of damage effects including differences caused by charged and neutral hadrons are discussed too.

HDMC: An object-oriented approach to hardware diagnostics

V.Schatz, C.Schumacher University of Heidelberg, Heidelberg, Germany
M.P.J.Landon Queen Mary and Westfield College, London, UK

Abstract:

A software package has been developed, which provides direct access to hardware components for testing, diagnostics or monitoring purposes. It provides a library of C++ classes for hardware access and a corresponding graphical user interface. Special care has been taken to make this package convenient to use, flexible and extensible. The software has been successfully used in development of components for the pre-processor system of the ATLAS level-1 calorimeter trigger, but it could be useful for any system requiring direct diagnostic access to VME based hardware.

Specification and Simulation of ALICE DAQ System

Giovanna Di Marzo Serugendo, CERN / Predrag Jovanovic, School of Physics and Astronomy, University of Birmingham / Pierre Vande Vyvre, CERN / Orlando Villalobos Baillie, School of Physics and Astronomy, University of Birmingham
for the ALICE Collaboration.

Abstract:

The Trigger and Data Acquisition System of the ALICE experiment has been designed to support the high bandwidth expected during the LHC heavy ion run.  A model of this system has been developed. The goal of this model is twofold. First, it allows to verify that the system-level design is consistent and behaves according to the requirements.  Second, it is used to evaluate the theoretical system performances using the measurements done on sub-systems prototypes. This paper presents the specification and simulation of a model of the ALICE DAQ system using a commercial tool (Foresight). This specification is then executed to simulate the system behaviour.

The nonlinear behaviour of p-i-n diode in high intense radiation fields

P.K.Skorobogatov, A.S.Artamonov, B.A.Ahabaev Specialized electronic systems

Abstract:

The dependence of p-i-n diode ionizing current amplitude vs dose rate is defined using twodimensional software simulation. It is shown that analyzed dependence becomes nonlinear beginning with relatively low dose rates near 107 rad(Si)/s. This effect is connected with the modulation of p-i-n diode intrinsic region by irradiation. As a result the distribution of electric field becomes non-uniform that leads to decrease of excess carriers collection. The ionizing current pulse form becomes more prolonged because of delayed component contribution. It is necessary to take into account when p-i-n diode is used as dose rate dosimeter.
The p-i-n diodes are widely used for the measurements of ionizing radiation dose rates. The high electric field in its intrinsic region provides the full and fast excess carriers collection. As a results the ionizing current pulse waveform repeats the ionization pulse with the accuracy of several nanoseconds. To investigate the p-i-n diode possibilities at high dose rates the original software simulator "DIO-DE-2D" [1] was used. The "DIODE-2D" is the fundamental system of equations two-dimensional solver. It takes into account carrier generation, recombination and transport, optical effects, carrier's lifetime and mobility dependencies on excess carriers and doping impurity concentrations. The typical p-i-n diode with 380 micrometers intrinsic region width under 300 V reverse bias was investigated. The simulation of p-i-n diode structure have shown that linear dependence between dose rate and ionizing current is valid only at relatively low dose rates up to 107 rad(Si)/s. In the field of high dose rates this dependence becomes non-linear and ionizing current increases more slowly than dose rate. The reason of non-linearity is connected with the modulation of p-i-n diode intrinsic region by excess carriers. Because of low level of initial carriers concentration the modulation takes place at relatively low dose rates. As a result of modulation the distribution of electric field in the intrinsic region becomes non-uniform that leads to decrease of excess carriers collection. The behavior of p-i-n diode becomes similar to that of ordinary p-n junction with prompt and delayed components of ionizing current. The prompt component repeats the dose rate waveform. The delayed component is connected with the excess carriers collection from regions with low electric fields. As a result the ionizing current pulse form becomes more prolonged and dose not repeat the dose rate waveform. The numerical results were confirmed by experimental measurement of p-i-n diode ionizing reaction in wide range of ionizing radiation dose rates. The non-linear character of behavior and prolonged reaction must be taken into account when p-i-n diode is used as dose rate dosimeter.
References [1]. The "DIODE-2D" Software Simulator Manual Guide, SPELS, 1995.

Use of external resistor to prevent radiation induced latch-up in commercial CMOS IC's

P.K.Skorobogatov, A.Y.Nikiforov, A.A.Demidov Specialized electronic systems

Abstract:

It is shown that in the case of external resistor usage to prevent radiation induced latch-up in commercial CMOS IC's we have the increase of IC recovery time up to tens of microsecond due to deep saturation of parasitic bipolar transistors. Under numerical calculations it was found that there is an optimal value of external resistor that provides the minimal recovery time of IC.
The usage of commercial CMOS IC's in radiation environment is restricted by the possibility of its latch-up behaviour under irradiation. The external resistor in power supply circuit is a well-known way to prevent latch-up. This method is found on the restriction of IC power supply current to the level lower than latch-up holding current. The experiments were shown however that in this case we unfortunately have the increase of IC recovery time up to tens of microsecond. Under numerical calculations it was found that this effect is connected with deep saturation of parasitic bipolar transistors on the external resistance. It was found that there is an optimal value of external resistor that provides the minimal recovery time of IC. In the case of low resistance the large recovery time is connected with deep level of parasitic transistors saturation. In the case of high resistance value the recovery time is defined by well-substrate p-n junction ionizing current delayed component voltage drop on the external resistance that increases with resistance growth. For CMOS IC's under investigation the optimal value was near 80 Ohm. This effect must be taken into account when commercial CMOS IC's are used in radiation environment.

THE ATLAS LIQUID ARGON CALORIMETERS READ OUT DRIVERS

Julie Prast for the ATLAS Collaboration

Abstract:

The Read Out Driver (ROD) for the Liquid Argon calorimeters front-end electronics of the ATLAS detector is described. Those ROD modules are designed for the ATLAS electromagnetic, hadronic end-cap and forward calorimeters. Each ROD module receives data from two Front-End Boards (FEB). The FEB amplifies, shapes, samples and stores the signal from 128 calorimeters cells at the frequency of the LHC (40 MHz). Then, the data are digitized and sent to the ROD modules for each Level-1 trigger (maximum rate of 100 kHz). These data are transmitted by two 32 bits data optical links. The principal function of the ROD is to reconstruct the precise energy and timing of each cell signal from the time samples. In addition, the ROD checks and histograms the data. The treated data are then sent towards the Read Out Buffers (ROB), according to a defined format, where they are stored.
A demonstrator system consisting of a mother board and several daughter boards Processing Units (PU), is under development. The goal of the demonstrator is to prove the feasibility of the project and serve as an intermediate step towards the construction of the final ROD module for the ATLAS experiment. The design of the prototypes are presented here.
The mother board is a full size 9U VME module able to carry four daughter boards. It allows all the input/output connections with the FEB and ROB, the controls of the board and the VME interface. This board offers maximum modularity and allows the development and testing of different Processing Units (PU). Three PU are being studied. Two are designed with the Texas Instrument TMS320C6202 fixed point DSP, while the other one is designed with the Analog Devices 21160 floating point DSP. These PU present the same overall architecture. The example of the Analog Devices PU will be taken.
Each PU treats data from an half FEB (8 ADC). Each ADC digitizes signals from 8 calorimeters cells. Each channel is composed of five 12-bit samples. These FEB data enter an FPGA at the speed of 40 MHz They are parallelized, parity checked and formatted before being buffered into the internal FIFO of the FPGA. This FIFO is connected to the external memory bus of the DSP. Once the DSP finishes the processing of the event, the results are formatted according to the ROB format and then put into a FIFO. This output FIFO is read by the mother board Output Controller.
The PU also contains a communication port, through which all the control of the board is done. It uses the DSP link ports to communicate with the mother board VME interface. It is also used to send monitoring or debugging information to the local CPU. All the communications between the DSP and its peripheral are done by Direct Memory Access (DMA), thus being transparent for the DSP core.
Results for the different PU will be presented and compared (functioning, performance, DSP algorithm). The first tests have shown that the demonstrator board meets the ATLAS requirements in term of bandwidth and accuracy, although the DSP used are not the next generation of DSP foreseen for the final version of the board.

Performance of a High Voltage Power Supply incorporating a Ceramic Transfomer

Yoshiaki Shikaze(Department of Physics, Faculty of Science, University of Tokyo), Masatosi Imori(ICEPP, University of Tokyo), Hideyuki Fuke(Department of Physics, Faculty of Science, University of Tokyo) Hiroshi Matsumoto(ICEPP, University of Tokyo), Takasi Taniguchi(National Laboratory for High Energy Physics(KEK))

Abstract:

This paper describes the performance of a high-voltage power supply incorporating a ceramic transformer. Since the transformer doesn't include any magnetic material the power supply can be operated under a strong magnetic field. In the article, the efficiency of the power supply is studied against various parameters. It was found that the efficiency reaches more than 50 percent when zero-voltage switching was realized. From a voltage source of 2V, the power supply can supply 3000V at a 21 megohm load. A voltage source of 5V is enough to supply 4000V at the same load.

The performance of a Pre-Processor Multi-Chip Module for the ATLAS Level-1 Trigger

R.Achenbach, P.Hanke, D.Husmann, M.Keller, E.-E.Kluge, J.Krause, K.Mahboubi, R.Megele, K.Meier, U.Pfeiffer, V.Schatz, K.Schmitt, C.Schumacher, B.Stelzer, O.Stelzer, P.Stock, E.Ulses
University of Heidelberg, Heidelberg, Germany

Abstract:

We have built and tested a mixed signal Multi-Chip Module (MCM) to be used in the Pre-Processor of the ATLAS Level-1 Calorimeter Trigger. The MCM performs high speed digital signal processing on four analogue trigger input signals. Results are transmitted serially at a serial data rate of 800 MBd. Nine chips of different technologies are mounted on a four layer copper substrate. Analogue-to-digital converters and serialiser chips are the major consumers of electrical power on the MCM, which amounts to 7.5 Watts for all dies. Special cut-out areas are used to dissipate heat directly to the copper substrate. In this paper we report on design criteria, chosen MCM technology for substrate and die mounting, experiences with the MCM operation and measurement results.

Fiber Optic based readout for BTeV's Pixel Detector

Gustavo I. E. Cancelo*, Sergio Zimmermann*, Sergio Vergara**, Peter Denes*, Guilherme Cardoso*, Bob Downing*, Jeff Andresen* * Fermilab, **University of Puebla, Mexico

Abstract:

The current paper describes the design of BTeV's Fiber Optics Pixel Detector readout. The pixel detectors will be located as close as 6mm from the accelerator's beam into the vacuum pipe. The readout electronics will be located at about 6cm from the beam, imposing strong constrains regarding radiation, mass, power dissipation, vacuum and size. This paper includes an analysis of the convenience of using a fiber optic based readout versus alternative solutions. Since the current design will place several components in a high dose proton and gamma radiation environment the fiber optic based readout will need some radiation hardened custom components, which are here specified. Furthermore, test results on optoelectronic devices are provided along with future plans to complete the design.

HIGH-SPEED COMPARATOR IC WITH LOW TIME DISPERSION

E.V.Atkin

Abstract:

The high-speed comparator for fast time reference is represented. It can be used as a leading edge discriminator or as a core for building constant fraction discriminator and can be useful for the development of time-of-flight systems.
It is manufactured with a bipolar process. Its main feature is a small time dispersion of output signal (200 ps) at the presence of a wide dynamic range of input signals (overdrives from 10 mV to 1V).
This paper describes the approach to the design of the new version of a low time dispersion comparator. The structure of such a comparator, features of schematics of its separate stages and its parameters are described.

A BiCMOS discriminator interface for the SPD

A. Diéguez, S. Bota Departament d'Electrònica, Sistemes d'Instrumentació i Comunicacions, Universitat de Barcelona, C/Martí Franquès, 1, E-08028, Barcelona. Spain

D. Gascón, L. Garrido Departament d'Estructura i Constituents de la Matèria, Universitat de Barcelona, C/Martí i Franques 1, E-08028 Barcelona. Spain.

M. Roselló Departament d'Electrònica, Enginyeria i Arquitectura La salle, Universitat Ramon Llull, Pg. Bonanova 8, E-08022, Barcelona. Spain.

Abstract:

A prototype chip for the analogue readout of the SPD in the LHCb Calorimeter is presented. The chip has been designed using the 0.8mm-BiCMOS technology of AMS and optimised for minimum size and maximum performance at the required frequency of operation in LHC experiments. It consists of a dual structure formed by two integrators, two track and hold circuits, two substractors, two comparators and a multiplexer. The die size occupied by one discriminator circuit is approximately 1720 mm x 330 mm.

Grounding and Shielding of the ATLAS TRT

Martin Mandl for the TRT collaboration

Abstract:

This paper addresses practical considerations for the engineering of the grounding and shielding system of the ATLAS-TRT.

A data driven high-resolution Time-to-Digital Converter

J. Christiansen, A. Marchioro, P. Moreira, M. Mota, V. Ryjov CERN, CH-1211 Geneva, 23 Switzerland
S. Débieux Engineering School of Geneva, Microelectronics Lab, Geneva, Switzerland

Abstract:

A data driven multi-channel Time-to-Digital Converter (TDC) circuit with programmable resolution (25ps - 800ps binning) has been implemented in a 0.24um CMOS technology. An on-chip PLL is used for clock multiplication up to 320MHz from an external 40MHz reference. A 32 element Delay Locked Loop (DLL) performs time interpolation down to 97.5ps. Finally, finer time interpolation is obtained using an on-chip RC delay line. Time measurements are processed and buffered in a data driven architecture based on time tags. This results in a highly flexible triggered or non-triggered TDC which can be used in many different experiments.

ATLANTIS - a modular, hybrid FPGA/CPU processor for the ATLAS Readout Systems

Christian Hinkelbein - Institute of Computer Science V, University of Mannheim, Germany Andreas Kugel - Institute of Computer Science V, University of Mannheim, Germany Reinhard Maenner - Institute of Computer Science V, University of Mannheim, Germany Matthias Mueller - Institute of Computer Science V, University of Mannheim, Germany Harald Simmler - Institute of Computer Science V, University of Mannheim, Germany Holger Singpiel - Institute of Computer Science V, University of Mannheim, Germany Lorne Levinson - Weizmann Institute of Science, Rehovot, Israel

Abstract:

ATLANTIS realizes a hybrid architecture comprising a standard PC platform plus different FPGA based modules for high performance I/O (AIB) and computing (ACB). CompactPCI provides the basic communication mechanism enhanced by a private bus. The system can be tailored to a specific application by selecting an appropriate combination of modules. Acceleration of computing intensive ATLAS LVL2 trigger tasks has been demonstrated with an ACB based system. The ATLAS RoD and RoB systems profit from the flexible and highly efficient AIB I/O architecture. Various high speed interface modules (S-Link/M-Link) are supported, allowing up to 28 links per CompactPCI crate.

Redundancy or GaAs ? Two different approaches to solve the problem of SEU (Single Event Upset) in a digital optical link optical

From SMU: Ryszard Stroynowski Bernard Dinkespiler Jingbo Ye Shouxuan Xie
From CPPM: Frederic Rethore
From ISN: Marie-Laure Andrieux Laurent Gallin-Martel
From KTH: Mark Pearce Johan Lundqvist Stefan Rydstrom

Abstract:

The fast digital optical links for the ATLAS Liquid Argon Calorimeter must survive in a high radiation environment with a total fluence of 2*1013 neutrons/cm2 and 800 Gy. The links based on Agilent Technologies -former HP- Glink chipset show a total dose radiation resistance to neutrons and gammas that would allow for 10 years of operation in the ATLAS detector. We have observed, however, an unacceptable rate of single event upsets (SEU) due to neutrons interacting in the silicon-based serializer. In order to solve this problem, we have developed two link systems. The first one - Dual-Glink-, is based on the principle of redundancy. Data are sent on two independent links. On the reception side, data are analyzed and error recovery is performed without dead time.
The second solution uses a GaAs serializer/deserializer chipset from TriQuint. This technology is intrinsically radiation hard. We expect a minimal number of SEU's and other radiation related problems. High speed of this chipset -2.5 Gb/s- allows for error recovery.
The design of the link, its performance in the laboratory environment and the results of the radiation tests will be presented for both systems.

The Detector Control Unit: an ASIC for environmental monitoring in the CMS central tracker

Guido Magazzu' - INFN Sezione di Pisa
Alessandro Marchioro - CERN EP-MIC
Paulo Moreira - CERN EP-MIC

Abstract:

The readout system of the CMS central tracker performs several functions: readout of the data from the front-end ASICs, distribution of the timing and trigger signals, distribution and collection of the slow control and status information and collection of local environmental parameters. The DCU (Detector Control Unit) is an integrated circuit which monitors parameters such as the leakage current in the silicon detectors, local voltages and temperatures. All these measurements can be performed by one analog multiplexer followed by a A/D converter interfacing to the slow control system. Such functions could easily be performed by a number of commercial devices, but the constraints of radiation tolerance, low power and maximum integration lead us to design a special integrated circuit which will be here described.

The Muon Pretrigger System of the HERA-B Experiment

M.Adams (Universitaet Dortmund), P.Bechtle (Universitaet Dortmund), P.Buchholz (Universitaet Dortmund), C.Cruse (Universitaet Dortmund), U.Husemann (Universitaet Dortmund), E.Klaus (Universitaet Dortmund), N.Koch (Universitaet Dortmund), M.Kolander (Universitaet Dortmund), I.Kolotaev (ITEP Moscow and Universitaet Dortmund), H.Riege (Universitaet Hamburg), J.Schuett (Universitaet Hamburg), B.Schwenninger (Universitaet Dortmund), R.van Staa (Universitaet Hamburg), D.Wegener (Universitaet Dortmund)

Abstract:

The muon pretrigger system of the HERA-B experiment is used to find muon track candidates as one of the inputs of the first level trigger. Due to the interaction rate of 40 MHz required to achieve an accuracy of 0.17 on sin(2beta) the total input of the muon pretrigger system is about 10 GBytes/s. The latency to define muon track candidates should not exceed 1 microsecond. Therefore the muon pretrigger is implemented as about 100 large size VME modules in a highly parallelized architecture.
We will present the system as well as performance studies and first physics results.

Multichannel system of fully isolated HV power supplies for silicon strip detectors

Edward Gornicki (Institute of Nuclear Physics, Cracow, Poland) Stefan Koperny (Faculty of Physics and Nuclear Techniques of UMM, Cracow} Piotr Malecki (Institute of Nuclear Physics, Cracow)

Abstract:

A multichannel system of power supplies providing a bias voltage in the range of 0 - 410 V for silicon micro-strip detectors is presented. All channels are fully isolated allowing for flexible detector segmentation. A wide range of functions including e.g. a programmable current trip limit as well as a ramp-up and rump-down control independent for each channel are also described.

First Level Trigger for H1, using the latest FPGA generation

M. Urban, A. Rausch, U. Straumann Physikalisches Institut Universitaet Heidelberg

Abstract:

To cope with the higher luminosities after the HERA upgrade, H1 builds a set of new MWPCs, which provide information to distinguish between beam background and true ep interactions. The first level trigger uses the latest 20K400 APEX FPGAs with 500 user IO pins to find tracks in 10000 digital pad signals. It allows to reconstruct the vertex and cut on its position. The system works deadtime free in a pipelined manner using 40 MHz clock frequency. The pipelines needed for data acquisition are also programmed into the same FPGAs. Test results including timing stability will be shown.

TDC based Readout for High-Rate Drift Tubes and Wire Chambers

H. Fischer*, J. Franz, A. Grunemaier, F.H. Heinsius, L. Hennig, K. Konigsmann, M. Niebuhr, T. Schmidt, H. Schmitt, H.J. Urban Fakultat fur Physik, Universitat Freiburg, 79104 Freiburg, Germany

Abstract:

The tracking system for the COMPASS experiment at CERN will consist of about 40000 drift tubes. In our report we discuss the design of and the practical experience with the drift-tube readout system which we set up during the year 2000 detector commissioning run.
The front-end board for the electronic processing of the signals produced by the drift tubes contains 64 preamplifiers, shapers, discriminators and time-to-digital converters. For the analog processing of the signals the ASD8b chip has been selected. For the COMPASS experiment we have developed a new TDC (F1) which comprises an asymmetric ring oscillator controlled by a phase locked loop. The digitised signals are transmitted via serial links to readout-driver modules. This 9U VME unit interfaces up to 16 front-end data-links to one optical S-LINK. Besides local event building the FPGA-based module covers front-end board initialisation, trigger distribution and data flow surveillance

An FPGA-based implementation of the CMS Global Calorimeter Trigger

J. Brooke (University of Bristol) D. Cussans (University of Bristol) G. Heath (University of Bristol) A. J. Maddox (Rutherford Appleton Laboratory) D. Newbold (University of Bristol, Corresponding Author) P. Rabbetts (Rutherford Appleton Laboratory)

Abstract:

We present a new design for the CMS Level-1 Global Calorimeter Trigger, based upon FPGA and commodity serial link technologies. For each LHC bunch-crossing, the GCT identifies the highest pt electron, photon and jet candidates; calculates scalar and vector total transverse energies; performs jet-counting, and provides real-time luminosity estimates. The pipelined system logic is implemented using 0.18um Xilinx FPGAs. The traditional system backplane is replaced by fast serial links for trigger data, and Ethernet for control. These technologies allow an improvement in system flexibility and a considerable reduction in cost, complexity and design time compared to an ASIC/VME-based solution.

Possibility of SR8000 Supercomputer for ATLAS DAQ Event Building and Event Filtering

ANRAKU, Kazuaki (ICEPP, Univ. of Tokyo), IMORI, Masatosi (ICEPP, Univ. of Tokyo)

Abstract:

We are investigating the possiblity of adapting the SR8000 supercomputer system by Hitachi for ATLAS DAQ event building and event filtering. The SR8000 system is comprised of a number (up to 128) of nodes, each of which has RISC microprocessors sharing a main memory, and of high speed "multi-dimensional" inter-node network. The maximum total processing power amounts to 1024 GFLOPS and a bidirectional transfer rate of the inter-node network is 2 Gbyte/s. An arbitrary number of nodes can have I/O adapters of HIPPI, ATM, Ethernet, and Fast Ethernet. These features seem to be suitable to both the ATLAS DAQ event builder and event filter.

CMS REGIONAL CALORIMETER TRIGGER HIGH SPEED ASICs

P. Chumney, S. Dasu, M. Jaworski, J. Lackey, W.H. Smith

University of Wisconsin - Madison

Abstract:

The CMS regional calorimeter trigger system detects signatures of electrons/photons, taus, jets, and missing and total transverse energy in a deadtimeless pipelined architecture. This system contains 19 crates of custom-built electronics. Much of the processing in this system is performed by five types of 160 MHz digital ASICs. These ASICs have been designed in the Vitesse submicron high-integration gallium arsenide gate array technology. The five ASICs perform data synchronization and error checking, implement board level boundary scan, sort ranked trigger objects, identify electron/photon candidates and sum trigger energies. The design and simulation of these ASICs and prototyping results are presented.

Design of a comparator in a 0.25µm CMOS technology

Niels van Bakel, Jo van den Brand (Free University of Amsterdam / NIKHEF Amsterdam), Hans Verkooijen (NIKHEF Amsterdam), Daniel Baumeister, Werner Hofmann, Karl-Tasso Knoepfle, Sven Loechner, Michael Schmelling, Edgar Sexauer (Max-Planck-Institute for Nuclear Physics, Heidelberg) Martin Feuerstack-Raible (University of Heidelberg), Neville Harnew, Nigel Smale (University of Oxford)

Abstract:

A comparator for the LHC-B vertex detector front-end chip, the Beetle, has been designed in a 0.25µm CMOS technology and is sent for fabrication. To improve threshold uniformity, each comparator has a 3 bits DAC. The comparator can handle positive and negative inputsignals. A polarity signal changes the polarity of the threshold voltage and makes the outputsignal always positive when active. The outputsignal is latched by a 40MHz clock and is selectable between time-over-threshold (in 25ns bins) or active for one clockcycle. Simulation- and measurement results will be discussed.

FEE tracker module developments for ALICE and STAR

Abstract:

Assessments of the front-end module developments in the frame of ALICE and STAR trackers in relation with the radiation effects on detectors and chips. Production of similar modules for the STAR SVT.

Comparative study of current-mode versus voltage-mode analog memory in a 0.25um CMOS technology

F.VAUTRIN, J.MICHEL, F.BRAUN

Abstract:

The aim of this work is the study of switched-current and voltage-mode memory cells in order to develop a model including non-ideal effects such as charge injections,non-linear capacitance and readout system influence. These models will allow non-linearity control regard to surface, speed and power criteria in digital dedicated submicronic technology. Such models lead to a memory cell optimization in order to include it in an analog memory for LHC experiments.

Overview of the ATLAS LAr front-end radiation tolerance

C. de La Taille (LAL Orsay)

Abstract:

The front-end electronics of the ATLAS liquid argon calorimeter must withstand a non-negligible radiation environment (20Gy/yr 5e11N/cm2/yr), in particular when various safety factors (simulation inaccuracies, lots variability or low dose rate effects) are put on top. The design of all the front end elements is now complete and has been tested on module0 on over 2,000 channels. Several key components have been extensively tested to radiation exposure (preamps, shapers, pipelines...) whereas other circuits (mostly digital) are being now migrated into DMILL. The results of these tests will be summarized and the design of the DMILL chips will be presented. The next milestone of the LAr collaboration is to have a final radiation hard complete front-end prototype by mid july.

Design Considerations of Low Voltage DC Power Distribution for CMS Sub-Detectors

B.Allongue, F. Fontaine, F. Szoncso, G. Stefanini CERN Switzerland S. Lusin, P. Robl University of Wisconsin, Madison, USA J. Elias Fermilab, USA C. Rivetta ETH Zurich/CERN Switzerland

Abstract:

A distinguishing feature of LHC detectors is the enormous number of front-end electronics (FE) channels in all of the sub-detectors. Low-voltage power supply systems in the range of multi-kilowatts are required to bias such electronic read-outs. Several configurations has been proposed and analyzed by the different groups showing particular advantages and disadvantages. For the CMS detector, the Hadronic Calorimeter (HCAL) and the Muon End-caps (EMU) have proposed a DC power distribution system based on DC-DC power switching converters.
The topology of this DC power distribution is as follows: AC/DC converters in the control room are used to rectify the three phase mains and generate the primary 311 VDC voltage. Each rectifier supplies several DC-DC converters located in the cavern near the FE. The switching regulators convert the high voltage into appropriated low voltages that are locally distributed to the detector read-outs. Local regulation is performed in the FE at the board level using special linear low-dropout voltage regulators developed by CERN RD-49 collaboration.
The main advantage of this topology is the reduction in volume of the distribution cables due to the relative low primary currents. Locating the DC-DC converters in the hostile environment of the detector cavern is a disadvantage due to the presence of magnetic fields and radiation. Analysis and tests are necessary to characterize the behavior of those units under such conditions and find acceptable solutions. Also, further studies and tests are necessary to mitigate the radiated and conducted noise generated by the switching converters, to ensure stability of multi-converter systems against interactions between units, etc.
In this paper, tests conducted to validate the application of commercial units are reported and future tests are described. Also, an analysis of the overall system performance is presented along with guidelines for design and selection of the components are presented.

Experience with DMILL technology in the Development of the ASDBLR ASIC

N. Dressnandt, N. Lam, F.M. Newcomer*, R.P. VanBerg, H.H. Williams
University of Pennsylvania, Philadelphia Pa.

Abstract:

An engineering prototype of the ASDBLR ASIC has been fabricated in the rad hard, BICMOS, DMILL process offered by Temic. This ASIC integrates eight channels of high speed low power and low noise straw tube readout on a single substrate. Bi-level signal detection for ionizing tracks and TR photons at rates as high as 20MHz is accomplished utilizing six hundred custom sized components per channel. A previous DMILL prototype showed strong sensitivity to hookup conditions manifested as unexpected harmonics. Steps taken to eliminate these harmonics, including improvement of the device models appear to have been successful. Measured performance of the recent prototype nearly exactly matches SPICE calculations. Results from neutron and proton exposures, beam tests with the companion DTMROC readout chip and plans to include custom devices that have been fabbed for us by TEMIC will be discussed.

Statistical performance estimation and optimization of the CMS tracker optical links

F. Jensen, C.S Azevedo, G.Cervelli, K.Gill, R.Grabit, F.Vasey
CERN, Geneva, Switzerland

Abstract:

A significant number of analogue performance measurements have been carried out on the CMS tracker optical links with components selected to be close the final system. The measurements form the basis for an estimation of the expected analogue performance of the final tracker links. In particular the typical S/N and linearity performance will be estimated. Realistic performance limits based on estimations of the performance spread of the final 50000 links are also deduced. Finally we discuss ways to further optimize the analogue performance of the optical links using offline processing.

Switching Power Supply Technology for ATLAS LAr Calorimeter

H. Takai and J. Kierstead
(for the ATLAS Liquid Argon collaboration)
Brookhaven National Laboratory

Abstract:

The ATLAS liquid argon calorimeter is designing a switching power supply to be meet the harsh environmental requirements imposed by the location where they will be installed. In addition the design addresses the inaccessibility issue. We will present the design and available tests regarding radiation and magnetic field susceptibility.
The ATLAS liquid argon calorimeter is planning to install power supplies for the front end electronics in the gap region between the tile barrel and tile extended calorimeters. The required power for the overall electronics is approximately 150 kW. This requirement rules out the use of copper cables to bring the power to the crates. In this location the environmental and access issues are such that the design will have to follow very tight specifications. The environmental issues are twofold: magnetic field and nuclear radiation. The radiation in the location of the power supply is a mixture of particles from the tails of Hadronic showers. They include photons, hadrons, and electrons. The expected integrated dose over a period of ten years is of the order of 10 kRad, and the overall flux of 1 MeV equivalent neutrons 1x10^12.cm-2. The flux of neutrons above 1 MeV is estimated to be 5 kHz.cm-2. The magnetic field in the region of the power supplies is estimated to be 50 Gauss. The current maintenance schedule allows access to the volume including the power supplies only once a year, therefore reliability and remote monitoring and control is essential. The final requirement that we have to meet is a very limited space.
With these requirements in mind, we have established a strategy for the development of appropriate power supplies. Currently, we expect to have prototypes ready by the end of year 2000. The plan calls for a radiation tolerant and single event upset resistant power supply with remote operational capabilities. At the heart of the power supply blocks of DC-DC converters will be used. A number of these blocks will be connected in parallel to form an N+1 redundant system. Each block will be monitored during the operation for temperature, fatal failure, over-current, and over-voltage. At the present time two potential manufacturers have been identified, Vicor and Modular Devices Inc. Vicor modules meet the requirements for electronic noise, magnetic field, and limited radiation tolerance but have not been tested for single event effects. The DC-DC converter manufactured by Modular Devices is known to be radiation tolerant but has not been tested for magnetic field or SEE effects. The control circuits are designed to be radiation and SEE tolerant.
In spring 2000 we plan to initiate tests for SEE susceptibility using heavy ion beams, followed by tests using 100 MeV or greater protons. We are particularly concerned with SEB or SEGR in the power mosfets as well as possible latchups in the control logic. We will report on the progress on the development of the power supply. In particular preliminary tests as far as radiation is concerned will be discussed.

CHARACTERISATION OF THE APVD READ-OUT CIRCUIT FOR DC-COUPLED SILICON DETECTORS (Final report)

J.D. Berst, C.Colledani, Y.Hu, R.Turchetta, LEPSI, IN2P3/ULP,
23 rue du Loess, BP20, F-67037 Strasbourg, France

G.Deptuch, U.Goerlach, C. Hu-Guo, P.Schmitt, IReS, IN2P3/ULP,
23 rue du Loess, BP20, F-67037 Strasbourg, France

M.Dupanloup, S.Gardien, IPNL IN2P3/CNRS, F-69622 Villeurbanne, France

Abstract:

The APVD integrated circuit for the front-end electronics of DC-coupled silicon detectors for CMS has been developed and produced in the radiation-hard process DMILL.The APVD_DC contains, like other members of the APV family 128 identical analog channels, each composed of a low noise preamplifier, a CR-RC shaper, an analog pipeline of 160 cells and a signal processing stage. A current compensation circuit is added in every preamplifier to sink the leakage current coming from the detector.
We report on the final test results: the complete circuit has been tested and measured also in the presence of significant leakage currents up to 11 microampere which do not deteriorate the analog performance of the circuit like pulse shape dynamic range and adding about 300 ENC to the noise.
Previous APVD circuits suffered from an instability problem in the analog stage of the circuit occurring at nominal bias values. The analog baseline of the new modified circuit is absolutely stable also under extreme operation conditions, like high bias currents demonstrating that the implemented solution stops indeed the oscillation of the circuit as we previously claimed based on extensive simulations of the circuit.

A Novel Monolithic Active Pixel Sensor for Charged Particle Tracking and Imaging using Standard VLSI CMOS Technology

J.D. Berst, B.Casadei, G.Claus, C.Colledani, W.Dulinski, Y.Hu, D.Husson,
J.P.Le Normand, R.Turchetta, J.L.Riester LEPSI, IN2P3/ULP,
23 rue du Loess, BP20, F-67037 Strasbourg, France

G.Deptuch, U.Goerlach, S.Higueret, G.Orazi, M.Winter IReS, IN2P3/ULP,
23 rue du Loess, BP20, F-67037 Strasbourg, France

Abstract:

A novel Monolithic Active Pixel Sensor (MAPS) for charged particle tracking made in a standard CMOS technology is proposed. The sensor is a photodiode with a special structure, which allows the high detection efficiency required for tracking applications. The partially depleted thin epitaxial silicon layer is used as a sensitive detector volume. A first prototype has been designed and fabricated using a standard sub-micron 0.6 um CMOS process. It is made of four arrays each containing 64 times 64 pixels, with a readout pitch of 20 um in both directions. Extensive tests made with soft X-ray source ( 55 Fe) and minimum ionising particles (15 GeV/c pions) fully demonstrate the predicted performances, with the individual pixel noise below 20 electrons(ENC) and the Signal-to-Noise ratio of the order of 40, both for 5.9 keV X-rays and Minimum Ionising Particles (MIP). A new version of the circuit has been submitted to the 0.35 um Alcatel-Mietec process. This novel device opens new perspectives in high precision vertex detectors as well as in other applications.

Radiation hardness studies for CMS HF quartz fiber calorimeter

G. Dajkó, A. Fenyvesi, K. Makónyi, J. Molnár
Atomki, Debrecen, Hungary

P. Raics
University of Debrecen, Debrecen, Hungary

I.Dumanoglu
Cukurowa University, Adana, Turkey

J. P. Merlo
University of Iowa, Iowa City, USA

A Kerek, D. Novák
Kungl Tekniska Högskolan, Stockholm, Sweden

Abstract:

A project has been in progress to provide information on radiation hardness properties of Hamamatsu photomultiplier tubes and quartz-fibers to be used in the construction of CMS Very Forward Calorimeter. Neutron activation studies as well as neutron, gamma and electron radiation tolerance tests have been carried out, using 3.7 MeV average energy neutrons, 500 MeV energy electrons and Co-60 gamma radiation. The test setups, the irradiation conditions as well as the experimental results are described.

Compact Bidirectional 2.5 Gbit/s Optical Transceiver for the H1-Experiment

S. Lueders, R. Baldinger, R. Eichler, C. Grab, B. Meier, S. Streuli, K. Szeker
Institute for Particle Physics, ETH Zuerich, 5232 Villigen PSI, Switzerland

Abstract:

For triggering purposes, 9600 channels have to be read out within 96 ns, i.e. with a rate of 100 Gbit/s, using 40 identical very compact optical transceiver units --- each measuring 130 mm x 45 mm x 9 mm. Taking advance of VCSEL diodes and 90 degree fiber bending, 4x 850 Mbit/s of digitized trigger information as well as two channels with analog monitoring information are transferred to the receiver electronics 40 m away. From there two channels of 10 MHz clock information are received for timing adjustments.

The "MAD", a Full Custom ASIC for the CMS Barrel Muon Chambers Front End Boards

Franco Gonella and Matteo Pegoraro from INFN - Sez. Padova (Italy)

Abstract:

Front end electronics of CMS barrel muon chambers is built around a full custom ASIC, named MAD, designed and developed by INFN Padova, that provides amplification, discrimination and cable driving circuitry for a quadruplet of drift tubes.
The system is organized in compact boards located in the gas volume and includes I2C slow control features for channels enable/disable and temperature monitoring, and a flexible test pulse system for calibration purposes.
Attained results confirm the good performances of the system; particularly, big effort was put in radiation tests (neutron, gamma rays and ions) to check behavior and reliability in LHC environment.

The new ATLAS TRT read-out system

Peter Lichard CERN-EP

Abstract:

The ATLAS TRT detector is very demanding in terms of electronics performance because of the high occupancy of the detector. A new version of the full read-out system, including two new ASICs and the new back-end modules, has been designed and tested successfully at 40 MHz clock rate and high trigger rate on a detector prototype. A description of this system will be given, as well as test results and plan for future scaling.

Progress in development of the readout chip for the ATLAS Semiconductor Tracker

W. Dabrowski, Faculty of Physics and Nuclear Techniques, UMM, Krakow, Poland
F. Anghinolfi, CERN, Geneva, Switzerland
A. Clark, University of Geneva, Switzerland
T. Dubbs, SCIPP, UCSC Santa Cruz, CA, USA
L. Eklund, CERN, Geneva, Switzerland
M. French, Rutherford Appleton Laboratory, Didcot, UK
W. Gannon, Rutherford Appleton Laboratory, Didcot, UK
A. Grillo, SCIPP, UCSC Santa Cruz, CA, USA
P. Jarron, CERN, Geneva, Switzerland
J. Kaplon, CERN, Geneva, Switzerland,
J. Kudlaty, MPI, Munich, Germany
C. Lacasta, IFIC, Valencia, Spain
D. LaMarra, University of Geneva, Switzerland
D. Macina, University of Geneva, Switzerland
I. Mandic, Jezef Stefan Institute, Ljubljana, Slovenia
G. Meddeler, Lawrence Berkeley National Laboratory, Berkeley, CA, USA
H. Niggli, Lawrence Berkeley National Laboratory, Berkeley, CA, USA
P.W. Phillips, Rutherford Appleton Laboratory, Didcot, UK
P. Weilhammer, CERN, Geneva, Switzerland
E. Spencer, SCIPP, UCSC Santa Cruz, CA, USA
R. Szczygiel, CERN, Geneva, Switzerland
A. Zsenei, University of Geneva, Switzerland

Abstract :

The development of the ABCD chip for the binary readout of silicon strip detectors in the ATLAS Semiconductor Tracker has turned into a pre-production phase, following comprehensive evaluation of the ABCD2T prototype chip. The ABCD2T design is one of the two options of the binary readout architecture which have been developed for the ATLAS SCT. It is manufactured in the DMILL process and comprises in a single chip all blocks of the binary readout architecture. In the paper we will present a summary of the ABCD2T performance as well as design issues and performance of the ABCD3T chip which is expected to be the final version for the ATLAS SCT detector.

Single Event Upset Studies on the APV25 Readout Chip

J Fulcher, G Hall, E Noah , M Raymond
Imperial College, London, UK

D Bisello, G. Marseguerra, J Wyss
Padova University, Padova, Italy

M French, L Jones, Q Morrissey, A Neviani
Rutherford Appleton Laboratory, Didcot, UK

Abstract

The microstrip tracker for the CMS experiment at the LHC will be read out using APV25 chips.  During high luminosity running of the LHC the tracker will be exposed to particle fluxes up to 107 cm2 s-1.  This high rate of particles introduces a concern that the APV25 could occasionally suffer from Single Event Upset (SEU).  In order to evaluate the expected upset rate under these circumstances the APV25 was run under controlled conditions in a heavy ion beam.  This enabled the measurement of the SEU upset cross-section, and hence a prediction of the upset rate in CMS.  The upset cross-section for a range of particle LETs (Linear Energy Transfer) was measured and the referred threshold energy and saturated cross-section was evaluated.  These data are then used to predict the upset rate for the APV25 in the CMS tracker.

An electronic calibration for the readout chain of the ECAL-CMS

Youngwook Baek, Daniel Boget, Pierre Zves Davis, Jean Ditta, Nadia Fouque, Jean Pierre Mendiburu
LAPP Annecy-le-Vieux

Abstract :

A calibration system has been developped in 0.8 µ DMILL technology for ECAL-CMS. It consists of several logic and analogic chips that have been funded, and tested in lab and in irradiation beams.

Mono-phase cooling system for front-end electronics on the example of the ATLAS TRT detector

Magnus Andersson - Luleå University of Technology Sweden
Pierre Bonneau - CERN
Michel Bosteels - CERN
Jan Godlewski - INP Krakow Poland, CERN

Abstract :

The work presents the results of cooling tests performed for the ATLAS TRT electronics. The test installation and control equipment are described.
A model of a standard cooling unit designed for all ATLAS detectors is also presented together with its modifications corresponding to various limitations connected with experimental zone, magnetic field, limited access and localization of various detectors.

Performance and Radiation Tolerance of the ATLAS CSC On-Chamber Electronics

A. Gordeev, V. Gratchev, A. Kandasamy, P. O'Connor, V. Polychronakos, V. Tcherniatine, K. Vetter
Brookhaven National Laboratory

J. Dailing, N. Drego, D. Hawkins, A. Lankford, Y. Li, S. Pier, M. Schernau, D.Stoker, B. Toledano
University of California, Irvine

Abstract:

The on-detector electronics for the ATLAS Cathode Strip Chamber (CSC) performs amplification, analog buffering, and digitization of the charge signals from individual cathode strips. Working in a high-rate environment (strip hit rate up to several hundred kHz) the system requires a signal-to-noise ratio of 200:1 and a dynamic range of 10 bits. Radiation conditions are: ionizing dose of 4.4 krad/yr and neutron flux of 7x10^12 n/cm^2/yr.
The system consists of 320 chamber-mounted ASM boards serving a total of over 61,000 channels. Performance and radiation tolerance of ASM prototypes will be discussed.

Off-Detector Electronics for a High-Rate CSC Detector

A. Gordeev, V. Gratchev, A. Kandasamy, P. O'Connor, V. Polychronakos, V. Tcherniatine, K. Vetter
Brookhaven National Laboratory

J. Dailing, N. Drego, D. Hawkins, A. Lankford, Y. Li, S. Pier, M. Schernau, D. Stoker, B. Toledano
University of California, Irvine

Abstract:

The off-detector electronics system for a high-rate muon Cathode Strip Chamber (CSC) is described. The CSC's are planned for use in the forward region of the ATLAS muon spectrometer. The electronics system provides control logic for switched-capacitor array analog memories on the chambers and accepts a total of nearly 37 Gbyte/s of raw data from 64 chambers. The architecture of the system is described as are some important signal processing algorithms and hardware implementation details.

A simplified and accurate front-end electronics chain for timing RPCs

A.Blanco(1), N.Carolino(1), P.Fonte (1,2), R. Ferreira-Marques (1,3), A.Gobbi (4)
(for the ALICE collaboration)

1-LIP, Coimbra, Portugal.
2-ISEC, Quinta da Nora, Coimbra, Portugal.
3-Departamento de Física da Universidade de Coimbra, Coimbra, Portugal.
4-GSI, Darmstadt, Germany.

Abstract :

Recent advances in electronics and construction techniques have pushed the timing resolution of Resistive Plate Chambers below 50 ps sigma with detection efficiencies close to 99% for MIPs. In this paper we describe a new front-end electronics chain for accurate time and charge measurement in these devices, having in view a possible application in ALICE's T0 counter.
The circuit is built solely from commercially available and inexpensive integrated circuits, featuring a reduced number of components. It includes a fast (2 GHz bandwidth) two-stage amplifier that feeds a fixed threshold discriminator followed by an external TDC. The amplified signal is also buffered into an external ADC for charge digitization.
The chain was tested with realistic test signals from an RPC, yielding a timing resolution around 10 ps sigma for signal charges above 100 fC and a charge resolution of 5 fC.

The CMS Tracker APV25 0.25µm CMOS readout chip

M. J. French, L. L. Jones, Q. Morrissey, A. Neviani, R. Turchetta
Rutherford Appleton Laboratory, Didcot, OXON, OX11 0QX, United Kingdom

J. Fulcher, G. Hall, E. Noah, M. Raymond
Blackett Laboratory, Imperial College, London SW7 2AZ, United Kingdom

K. Kloukinas, P. Moreira
CERN, 1211 Geneva 23, Switzerland

N. Bacchetta, D. Bisello, G. Marseguerra, J. Wyss
University of Padova, Italy

Abstract:

The APV25 is the 128-channel readout chip for silicon microstrips in the CMS tracker. It is the first major chip for a high energy physics experiment to exploit a modern commercial 0.25µm CMOS technology. Experimental characterisation of the circuit shows full functionality and excellent performance both in pre- and post-irradiation conditions. The measured noise is significantly reduced compared to earlier APV versions. Automated on-wafer testing of many chips has demonstrated a very high yield. A summary of the design and detailed results from measurements will be presented. Operation of the chip in conjunction with other CMS system components will be described.

First results from the ALICE1LHCb pixel chip

K. Wyllie1), M. Burns1), M. Campbell1), E. Cantatore1), V. Cencelli2), P. Chochula1), R. Dinapoli3), S. Easo4),
F. Formenti1), T. Grassi1), E. Heijne1), P. Jarron1), K. Kloukinas1), P. Lamanna3), F. Meddi1), M. Morel1), V. O’Shea4),
V. Quiquempoix1), D. San Segundo Bello5), W. Snoeys1), L. Van Koningsveld1)

1) CERN, Geneva, Switzerland
2) INFN Rome, Italy
3) University and INFN Bari, Italy
4) University of Glasgow, Glasgow, UK
5) NIKHEF, Amsterdam, The Netherlands.

Abstract:

ALICE1LHCb is an integrated circuit to read out silicon pixel sensors used for particle tracking in the ALICE Silicon Pixel Detector or for particle identification in the LHCb RICH. It has been fabricated in a commercial 0.25 micron technology, with consideration given to radiation tolerance, testability and system integration.
Results from the first laboratory measurements are presented. These include characterisation of the front-end, with measurements of noise and threshold uniformity. The functionality of the digital circuitry is described whilst operating the chip in both ALICE and LHCb modes. The use of the serial JTAG interface is outlined, in terms of configuring the chip and testing connectivity at the system level.

HAMAC, a rad-hard high dynamic range analog memory for Atlas calorimetry

E. DELAGNES, P. BORGEAUD
CEA, DSM/DAPNIA SACLAY, 91191 Gif­sur­Yvette, France.

E. AUGE, D. BRETON, G. MARTIN­CHASSARD, V. TOCUT
LABORATOIRE DE L'ACCELERATEUR LINEAIRE, IN2P3­CNRS et Université Paris­Sud, 91405 Orsay Cedex, France.

J. PARSONS, W. SIPPACH
NEVIS LABORATORIES, COLUMBIA UNIVERSITY, IRVINGTON, NY 10533, USA

Abstract:

An 12 channel analog memory dedicated to the readout of the Atlas liquid argon calorimeter has been developed. Its main function is to sample, at a 40 Mhz rate, the data coming from a three gain shaper, to store it, waiting for the level­1 trigger decision, and then to send it more slowly (5MHz) towards a 12 bit ADC. For each trigger, the ADC will digitize 5 samples. As the system is supposed to present minimum dead time, the write operations will be unceasing even during the read phases. The chip can thus be seen as a simultaneous double random access analog memory array. The read and write addresses are generated by a separate controller chip and sent together with other control signals to the analog memory using low­voltage swings.
In the ATLAS calorimetry, the electronics will have to withstand a total ionising dose higher than 20 krad over a 10 year lifetime. For reliability, the circuit may survive to a total dose of 100krad. Thus the chip has been developed in DMILL technology.
The presentation will highlight the amazing level of performance achieved by this circuit whose dynamic range is far in excess of 13 bits even while undergoing simultaneous write and read accesses.

Implementation of a Digital Time Measurement Chip (DTMROC99)in DMILL for the ATLAS TRT

C. Alexander, F. Anghinolfi, R. Van Berg, N. Dressnandt, T. Ekenberg, Ph. Farthouat, P. T. Keener, N. Lam, D. Lamarra, J. Mann, F. M. Newcomer, V. Ryjov, M. Soderberg, R. Szczygiel, H.H. Williams

Abstract:

A 16 channel digital time measurement and readout chip, the DTMROC99, has been designed and built in DMILL, a BI-CMOS rad-hard process. This chip  is designed to accept low level ternary inputs from the ASDBLR99, a companion analog front end chip, to record the time of arrival of avalanche signals from tracks with 1ns precision as well as to record the detection of Transition Radiation photons in a 144 bit data word. Data is stored in a 3.3us pipeline and transferred to a 13 deep buffer if a Level 1 trigger is decoded.  In addition to its main readout function, the chip provides four threshold voltages and two test pulse outputs for the two ASDBLR's it reads out.  Communication utilizes specially designed LVDS compatable, low power differential inputs and outputs.

Total Dose irradiation of a 0.25µm process

M. J. French
Rutherford Appleton Laboratory, Didcot, OXON, OX11 0QX, United Kingdom

I. Dindoyal, G. Hall, E. Noah, M. Raymond
Blackett Laboratory, Imperial College, London SW7 2AZ, United Kingdom

D. Bisello
University of Padova, Italy

Abstract

A commercial 0.25µm process will be used for various electronic components of the CMS tracker, one of these being the APV25 readout chip for silicon microstrips. Irradiating and measuring individual transistors is important in assessing the radiation tolerance of the chip. Transistors from two different foundries owned by the same company were irradiated up to doses of 50Mrad(SiO2) with a 10keV X-ray source. Threshold voltage shifts of up to 140mV were observed whilst noise measurements showed very little degradation in the white noise region after irradiation and annealing. Detailed results of both static characteristics and noise will be presented.

Design of the Front-End Driver card for CMS Silicon Microstrip Tracker Readout.

S.A. Baird, K.W. Bell, J.A. Coughlan, R. Halsall, W.J. Haynes, I.R. Tomalin
CLRC Rutherford Appleton Laboratory, Oxon, UK.
E. Corrin
Imperial College, London, UK.

Abstract:

The CMS silicon microstrip tracker has the order of 10 million readout channels. The tracking readout system employs several hundred off-detector Front-End Driver (FED) cards to digitise, sparsify and buffer analogue data arriving via optical links from on-detector pipeline chips (APVs). This paper describes the baseline design of the Front-End Driver card which is implemented as a 96 ADC channel (10 bits) 9U VME board. At typical LHC operating conditions the total input data rate per FED after digitisation of over 3 GBytes/s must be substantially reduced. The required digital data processing is highly parallel and heavily pipelined and is carried out in several large FPGAs. The process of FPGA digital design using VHDL and design optimisaton with board level simulation together with the tools employed are discussed.

The Detector Control System for the HMPID in ALICE Experiment at LHC

G. De Cataldo for the ALICE collaboration, INFN Bari, Italy
(email: giacinto.de.cataldo@cern.ch)

Abstract:

The Detector Control System (DCS) of ALICE at LHC will allow a hierarchical consolidation of the participating sub-detectors to obtain a fully integrated detector operation.
The High Momentum Particle Identification Detector (HMPID), based on a Ring Imaging Cherenkov, is one of the ALICE sub-detectors. Its DCS has to ensure the detector configuration, operation in standalone mode for maintenance, monitoring, control and integration in the ALICE DCS.
In this paper a status report of the HMPID DCS is presented. Costs and merits of its implementation in function of the chosen HV and LV systems will also be reported.

Design and Characterization of a DAC for the Slow Control of the Pixel Chip

F. Corsi (*), R. Dinapoli (*)(#), P. Lamanna(*), C. Marzocca(*)
* Dipartimento di Elettrotecnica ed Elettronica - Poltecnico di Bari
# INFN - Sezione di Bari

Abstract :

A digital to analog converter for slow control of pixel front end chip has been designed in a 0.35 um standard CMOS technology to prove the effectiveness of the chosen circuit structures for this application. The DAC provides a total output current variation of about 15uA with an accuracy of 8 bits (LSB=60nA).
The DAC is based on a PMOS current bank (an NMOS of a reasonable size would operate in the weak inversion region for these current levels and would hence be unsuitable for accurate current sources). The bit value determines whether the current corresponding to these bit is switched to the output or not.
The occupied area is about 300um x 300um and total power dissipation is 85uW.  The results of the test measurements performed on the 36 fabricated prototypes show that statistical fluctuations of the output current due to mismatch are negligible compared to the desired accuracy for all the input configurations.

The ALICE Silicon Pixel Detector Readout System

Federico ANTINORI (1), Jaroslav BAN (2), Michael BURNS (1), Michael CAMPBELL (1), Peter CHOCHULA (1, 3), Fabio FORMENTI (1), Tullio GRASSI (4), Alexander KLUGE (1), Pierluigi LISCO (5), Franco MEDDI (1, 6), Michel MOREL (1), Giorgio STEFANINI (1), Kennith WYLLIE (1)
for the ALICE collaboration.

(1) CERN, 1211 Geneva 23, Switzerland
(2) Institute of Experimental Physics, 04353 Kosice, Slovakia
(3) Institute of Experimental Physics, 84215 Bratislava, Slovakia
(4) Formerly CERN, 1211 Geneva 23, Switzerland
(5) Universita degli Studi di Bari, I-70126 Bari, Italy
(6) Universita di Roma La Sapienza, I-00185 Roma, Italy

Abstract:

The ALICE SILICON PIXEL DETECTOR (SPD) is located within the Inner Tracking System (ITS) and is the detector with the highest active channel density and closest to the point of interaction.
Approximately 10 million active electronic channels, contained in a volume of 34 litres, have to be read out and controlled.
Such a high density in an inaccessible position has imposed a high degree of multiplexing to reduce the amount of cabling to a minimum.
This paper will describe the proposed architecture of the readout and control paths.

Updated Design for the ALICE Central Trigger

I.J. Bloodworth [1], G. Di Marzo [2], D. Evans [1], P. Jovanovic [1],
A. Jusko [3], J.B. Kinson [1], A. Kirk [1], V. Lenti [4], M. Luptak [3],
L. Sandor [3], P. Vande Vyvre [2] and O. Villalobos Baillie [1]

for the ALICE collaboration.

1. School of Physics and Astronomy, The University of Birmingham, Edgbaston, Birmingham, UK  B15 2TT
2. CERN, European Organization for Nuclear Research, CH-1211 Geneva 23, Switzerland.
3. Dipartimento di Fisica dell' Universita and Sez. INFN, Bari, Italy
4. Institute of Experimental Physics, Slovak Academy of Sciences, Kosice, Slovakia.

Abstract:

The trigger and data acquisition systems in the ALICE experiment have undergone significant changes in the last year.  This is (i) in response to the incorporation of new detectors, (ii) the result of the use of front-end buffering schemes in the ALICE sub-detectors, and (iii) because of new more pessimistic estimates of the data volume generated by the Time Projection Chamber (TPC). In this report, we review the specification for the updated ALICE Central Trigger and examine how it might be implemented using currently available electronics components.
The User Requirement Document and the Technical Specification for this system are being discussed by the ALICE collaboration.

Readout Unit Prototype for CMS DAQ System

G. Antchev, E. Cano, S. Cittolin, S. Erhan,
B. Faure, D.Gigi, J. Gutleber , C.Jacobs, F. Meijers,
E. Meschi, A. Ninane, L.Orsini, L. Pollet, A.Racz,
D. Samyn, N. Sinanis, W. Schleifer, P. Sphicas

CERN Div.EP/CMD, Switzerland

Abstract :

In the CMS data acquisition system, the Readout Unit (RU) is a major element of the Readout Column and it is placed between Front-end Devices (FED) and Builder Data Network (BDN). The RU is intelligent fast buffer for intermediate storage of data before transferring between the levels of the DAQ system. Readout Unit prototype is developed to achieve the CMS DAQ requirement for data input bandwidth of 400MB/sec and data output bandwidth of 400 MB/sec. The new RU prototype based on reconfigurable hardware structure and high-speed standard busses is presented in this paper.

Performance of a new MCM-D technology front­end digital readout

P. Cluzel 1 , R. Della­Negra 1 , M. Goyot 1 , M. Miguet 1 , A. Savoy­Navarro 2
1 IPNL­Universit’e Louis Bernard de Lyon/IN2P3­CNRS, France
2 LPNHE­Universit’es de Paris 6 et 7/IN2P3­CNRS, France

Abstract

A CEE ESPRIT project developed a new MCM­D packaging technology with a view to industrial, biomedical and HEP applications. The objective was to establish a cost­efficient, commercial manufacturing base in silicium­ based MCMs, with active substracts and ball­grid array interconnects. Among the main features are the integration of active and passive components in the substrate and the use of a flip­chip technique and wafer rerouting. The demonstrator built with this new technology is a prototype of a fast digital readout front­end electronics, mixing analogue and digital components. The tests show very high functioning performances.

Software developments for the Readout Unit Prototypes for CMS DAQ System

M.Bellato (INFN Sezione di Padova)
G.Antchev, E.Cano, S. Cittolin, B.Faure, D.Gigi, J.Gutleber, C.Jacobs, F. Meijers, E. Meschi, L.Orsini,
L. Pollet, A.Racz,D. Samyn, N. Sinanis,W. Schleifer, P. Sphicas (CERN)
A.Ninane (Université Catholique de Louvain)

Abstract :

In the CMS data acquisition system, the readout unit is a fast buffering device for short term storage of event fragments. It interfaces front end devices and builder data network.

The current Readout Unit prototypes are based on two homegrown hardware boards, the Readout Unit Memory (RUM) and the Readout Unit I/O (RUIO). These boards are equipped with an IOP. Several OS environments for this processor are developed. The software running on those boards will have to setup and control the input and output processes. Fast IOP to host communications are experimented. A software test environment is specifically designed for test and validation of the complex memory management of the RUM.

Impact of Reliability Specification on Electrical System Design
Stan Jaroslawski

Abstract:

Advantages of addressing Reliability issues very early in any electrical system design is emphasised. An example of an impact of the Reliability specification on the design of a power subsystem is described.  The power subsystem is part of  High Resolution Limb Sounder (HIRDLS) instrument which is to be flown in space as part of Chem1 mission. The main component of the subsystem is a power supply designated Power Converter Unit (PCU). The PCU has to meet HIRDLS instrument system a very tight Reliability requirement of 0.99. The PCU must also meet HIRDLS instrument power requirement (220Watts total), be compliant with spacecraft requirements, and NASA specifications.

Electronic Design Automation tools for high-speed electronic systems

B.J. Evans
E. Calvo Giraldo
T. Motos Lopez

CERN, IT/CE

Abstract:

The LHC detectors will produce a large amount of data that will need to be moved very quickly.  The signal-speeds and interconnect-density involved lead to difficult electrical design problems, particularly regarding signal-integrity issues.
Various commercial Electronic Design Automation programs are now available to address these problems. These include 3-D full-wave electromagnetic-field solvers, SPICE-based circuit-simulation programs and printed circuit board signal-integrity point products. We will show how these seemingly disparate tools can be used in a complementary fashion to provide detailed studies of detector-electronic design. Two case studies will be presented from LHC experiments.

Minimizing crosstalk in a high-speed cable-connector assembly

B.J. Evans
E. Calvo Giraldo
T. Motos Lopez

CERN, IT/CE

Abstract

This paper presents the detailed signal-integrity analysis results of a connector-cable assembly linking the ALICE Time Projection Chamber (TPC) to its Front-End Electronics.
The goal was to minimize the crosstalk (electromagnetic coupling) between signal lines for a given line to ground capacitance. Both mechanical (cable flexibility and strength) and electrical (fast signal rise-times) design constraints were considered.
The design was analysed using Finite Element Method software tools to extract equivalent circuit models for the connector and cable. We will show how these programs helped us to quickly investigate different cable configurations. The resulting PSpice simulations will be presented.

Digital Implementation of a Tail Cancellation Filter for the Time Projection Chamber of the ALICE Experiment

R.E.Bosch, B. Mota, L. Musa
CERN, Geneva (Switzerland)

FOR THE ALICE COLLABORATION

Abstract:

In the ALICE TPC, the readout chambers are conventional multiwire proportional chambers with cathode pad readout. The pad signal has a rather complex shape, which depends on the details of the chamber and the pad geometry, characterized by a long tail due to the motion of the positive ions. Since the zero suppression has to be done before the data transfer, the high channel occupancy calls for a very precise tail suppression. In order to be compatible with the required dE/dx resolution, a suppression to 0.1% or better of the maximum pulse height, is required. We present a digital implementation of a shortening filter based on the approximation of the tail by the sum of exponential functions.The hardware implementation of the filter is described and the results analyzed.

A front end ASIC for the Dimuon arm trigger of the ALICE experiment

Laurent Royer, Gerard Bohner, Jacques Lecoq
For the ALICE collaboration
LPC Clermont-Ferrand
 

A first prototype of the front-end ASIC dedicated to the trigger detector of the dimuon arm of ALICE has been designed and tested in the Laboratoire de Physique Corpusculaire of Clermont-Ferrand.

This setup is based on the Resistive Plate Chamber (RPC), a gaseous detector which can be operated either in streamer or avalanche mode. The streamer mode has the advantage of providing large signals that can be discriminated without amplification whereas the avalanche mode presents a better rate capability and time resolution with conventional discrimination techniques.

Since we proposed to operate the RPCs in streamer mode in ALICE, we have studied a new discrimination technique in order to obtain a time resolution better than 2ns in this mode. The method used in this dedicated circuit is described, performances and tests results are given, as well as the evaluation done in the test beam of summer 2000.

Analogue Read-Out Chip for Si Strip Detector Modules for LHC Experiments
E. Chesi1, J. A. Clark2, V. Cindro3, W. Dabrowski4, D. Ferrere2, G. Kramberger3, J. Kaplon1, C. Lacasta5, J. Lozano1, M. Mikuz3, C. Morone2 S. Roe1, A. Rudge1, R. Szczygiel6, M.Tadel3, P. Weilhammer1, A. Zsenei2
1CERN, 1211 Geneva 23, Switzerland
2University of Geneva, Switzerland
3Jozef Stefan Institute, Ljubljana, Slovenia
4Faculty of Physics and Nuclear Techniques, UMM, Krakow, Poland
5IFIC, Valencia, Spain
6Institute of Nuclear Physics, Krakow, Poland

Abstract

We present a 128-channel analogue front-end chip SCT128A for readout of silicon strip detectors employed in the inner tracking detectors of LHC experiment. The architecture of the chip and critical design issues are discussed. The performance of the chip has been evaluated in detail in the bench test and is presented in the paper. The chip is used to read out prototype analogue modules compatible in size, functionality and performance with the ATLAS SCT base line modules. Several full size detector modules equipped with SCT128A chips has been built and tested successfully in the lab with b particles as well as in the beam test.

The CMS Pixel Detector

Danek Kotlinski, Paul Scherrer Institute, Switzerland

Abstract:

In the presentation the readout architecture of the CMS pixel detector will be discussed.
The data rate and volume expected at the full LHC luminosity and it's implication on the readout chip will be presented. The overall pixel readout system  and the integration with the CMS data acquisition system will be emphasized.
The first pixel detector layer will be placed at 4cm from the beam in a very high radiation environment. Some aspects of the radiation hardness and its impact on the readout design will be discussed.

Front-End electronics for ATLAS Pixel detector

Abstract:

The electronics subgroup of the ATLAS pixel detector has pursued an iterative programme of design development over the last 3 years. The initial phase of this demonstrator programme was aimed at realizing ATLAS specification front-end chips using radiation-soft technologies, the designs of which could then easily be adapted for fabrication at rad-hard foundries. First realistic prototypes were designed in 2 parallel efforts (Europe and US) in 97/98, producing a rad-soft AMS prototype (FE-A/FE-C) and a rad-soft HP prototype (FE-B). Throughout 98/99, more than 60 single chip assemblies and 10 electrically functional modules were produced and have been studied extensively in lab and during 7 testbeam periods at SPS. All of the ATLAS requirement issues (except for the radiation hardness) were addressed in detail such as noise, threshold dispersion, timewalk, digital/analog crosstalk, power supply rejection...with very encouraging results. These measurements on both single chip assembly and module are presented. A unified design approach has been adopted for rad-hard front-end chips, i.e. all working on the same design to be implemented in 2 rad-hard processes. The rad-hard designs, namely FE-D for the DMILL process and FE-H for the Honeywell process, maintain the spirit of the demonstrator programme (i.e. pin compatibility, same pixel pitches...) and combine features of both FE-A/C and FE-B. FE-D has been received in Oct. 99 and FE-H will be submitted during summer 2000.

RADIATION TOLERANCE EVALUATION OF THE ATLAS RPC COINCIDENCE MATRIX SUBMICRON TECHNOLOGY

E.Gennari, E.Petrolo, A.Salamon, R.Vari, S.Veneziano
INFN - Sezione di Roma
P.le Aldo Moro 2 - Rome - Italy

ABSTRACT:

The Coincidence Matrix ASIC is the central part of the ATLAS Level-1 Muon Trigger in the barrel region; it performs the trigger algorithm and data read-out. The ASIC will be mounted on dedicated boards on the Resistive Plate Chamber detectors. The chosen technology has to guarantee complete functionality in the ATLAS RPC radiation environment. Radiation tests have to satisfy the radiation tolerance criteria proposed by the ATLAS Policy on Radiation Tolerant Electronics. The ATLAS standard test methods has to be followed in order to guarantee both total dose and single event effects tolerance.
A frequency multiplier ASIC was used for technology evaluation and radiation tests. The chip is a low jitter programmable clock multiplier, realised in 0.25 micron CMOS technology. This frequency multiplier is intended to be used in the Coincidence Matrix ASIC as a macro, to perform the internal clock frequency multiplication. Radiation test results will be presented.

APVMUX, An analogue multiplexing chip for the CMS Tracker
M. French, P. Murray, L. Jone (Rutherford Appleton Laboratory)
M. Raymond (Imperial College)

Abstract:

A chip for multiplexing pairs of APV25 chip outputs onto differential analogue cable has been designed. The chip includes SEU tolerant logic to detect and control the APV signal phasing and termination resistors required by the APV25 chip. The termination impedance and switching phase are programmable by I2C and bond control respectively. The design and implementation is outlined and test results presented.

The CMS Tracker  front-end and  control electronics in an LHC like beam test

W.Beaumont(b), M.Bozzo(f), C.Civinini(e), J.Coughlan(k), F.Drouhin(h), P.Figueiredo(d), L.Fiore(c), A.Giassi(j), K.Gill (d), J.Gutleber(d), G.Hall(g), L.Latronico(f), C.Ljuslin(d), M.Loreti(i), C.Maazouzi(l), S.Marchioro(d), N.Marinelli(g), C. Paillard(d), T.Parthipan(k), P.Siegrist(d), L.Silvestris(c,d), I.Tomalin(k), A.Tsirou(d), P.G.Verdini(j), P.Walsham(g),
B.Wittmer(a), A.Zghiche(l,d), F.Vasey (d)

(a) RWTH, I. Physikalisches Institut, Aachen, Germany,
(b) Universitaire Instelling Antwerpen, Antwerpen, Belgium
(c) INFN, Sezione di Bari, Bari,  Italy
(d) CERN, 1211 Geneva 23, Switzerland
(e) INFN, Sezione di Firenze, Firenze,  Italy
(f) INFN, Sezione di Genova, Genova,  Italy
(g) Blackett Laboratory, Imperial College, London SW7 2AZ, United Kingdom
(h) Universite de l’Haute Alsace, Mulhouse, France
(i) INFN, Sezione di Padova, Padova,  Italy
(j) INFN, Sezione di Pisa, Pisa,  Italy
(k) Rutherford Appleton Laboratory, Didcot, OXON, OX11 0QX, United Kingdom
(l) Institut de Recherches Subatomiques, IN2PS-CNRS Strasbourg, France

Abstract:

A complete prototype of the CMS tracker read-out and control system has been built using components that are very close to the final design. The system is based on analogue amplifier and pipeline memory chips (APV), analogue optical links transmitting at 40Mbps and a VME digitisation and data handling board (FED), supplemented by a control system which sets and monitors the components of the system. This system has been successfully operated for the first time under LHC like beam conditions,  in a 25ns structured beam provided by the SPS at CERN,  mainly aiming  to  test the synchronisation of the system and pile-up effects in a high trigger rate environment.
Preliminary results are presented in this paper