Matveev M., Padley P.
matveev@physics.rice.edu
Rice University, Houston, TX, USA

Key components of the CMS Cathode Strip Chamber (CSC) Endcap Muon trigger system are the Muon Port Cards and Muon Sorter, which perform data selection and sorting. They implement sorting "3 best objects out of 18" and "4 best objects out of 36" schemes respectively. We report on a common approach to design and construction of both boards. Board functionality and first results of logic simulation and latency estimate are presented.

Summary

The front end electronics of the Cathode Strip Chamber (CSC) Endcap Muon detector at the CMS experiment needs to calculate precise muon position and timing information and generate muon trigger primitives for the Level-1 trigger system. CSC trigger primitives (called Local Charged Tracks, LCT) are formed by anode (ALCT) and cathode (CLCT) cards. ALCT cards are mounted on chambers, while CLCT cards are combined with the Trigger Motherboards (TMB) that perform a time coincidence of ALCT and CLCT. Every CLCT/TMB card (one per chamber) transmits the two best combined anode and cathode muon tags to the Muon Port Card (MPC) which serves one CSC sector (8 or 9 chambers). The MPC selects the three best muons out of 18 possible and sends them over 100m of optical cable to the Track Finder (TF) crate residing in the underground counting room. In the current electronics layout the TF crate has 12 Sector Processors (SP), each of which receives the optical streams from several MPC. The SP measures the transverse momentum, pseudo-rapidity and azimuthal angle of each muon and sends its data (up to 3 muons each) to CSC Muon Sorter (MS) that resides in the middle of the TF crate. The MS selects the four best muons out of 36 possible and transmits them to Global Muon Trigger crate for further processing.

Two devices in the CSC trigger chain perform data sorting: the MPC ("3 best muons out of 18") and the MS ("4 best muons out of 36"). The total data reduction factor is 54. We propose a common approach to implementation of sorting logic and board construction for both the MPC and MS. They will be based on single chip programmable logic devices that receive data from the previous trigger level, sort it and transmit sorting result to the next trigger level. Programmable chips will incorporate input and output FIFO buffers that would represent all possible inputs and outputs for testing and debugging purposes. Finally we will use a common sorting scheme for both designs. The MPC and MS functionality as well as the first results of logic simulation and latency estimate are presented.

Matveev M., Nussbaum T., Padley P.
Rice University, Houston, TX, USA

An optical link intended for trigger data transmission from the CMS Cathode Strip Chamber peripheral electronics to the counting room was evaluated. It is based on a Texas Instruments TLK2501 gigabit transceiver and a Finisar FTRJ-8519-1-2.5 optical module. Functionality of the evaluation board and results of tests are presented.

The CMS Cathode Strip Chamber electronic system consists of on-chamber mounted boards, the peripheral electronics in VME 9U crates, and a Track Finder in the counting room. Due to high operating frequency of 40.08MHz and the 100m cable run from the detector to the underground counting room an optical link is the only choice for data transmission between these systems. Our goal was to prototype an optical link intended for the communication between the Muon Port Card and Sector Processor modules using existing commercial components. Our initial design based on the Agilent HDMP-1022/1024 chipset and Methode MDX-19-4-1-T optical transceivers was reported at the 6th Workshop on Electronics for LHC Experiments a year ago. Data transmission of 120 bits representing three muons at 40 MHz would require as many as twelve HDMP chipsets and twelve optical transceivers on a single receiver card (the Sector Receiver). This solution has disadvantages such as a large power consumption and a significant area required for link components on both the transmitter and receiver boards. Studies of the later triggering stages show that a reduction in the number of bits representing three muons can be made without compromising the system performance. Another improvement is to utilize a data serialization and deserialization at 80Mhz using a low power chipset and small form factor optical modules for a more compact design. Now only three links rather than six in a previous design are needed for communication between the Muon Port Card and Sector Processor. Results of the evaluation of the Texas Instruments TLK2501 gigabit transceiver and Finisar FTRJ-8519-1-2.5 optical module are reported.

Authors: G. Antchev, E. Cano, S. Cittolin, S. Erhan, W. Funk, D. Gigi, F. Glege, P. Gras, J. Gutleber, C. Jacobs, F. Meijers, E. Meschi, L. Orsini, L. Pollet, A. Racz, D. Samyn, W. Schleifer, P. Sphicas, C. Schwick

Attila Racz <racz@cmsmail.cern.ch>

In the context of the CMS data acquisition system, simple and robust data links are required to transfer data from the underground counting rooms up to the surface buildings where complex processing of the data takes place. In the case of CMS, ~500 of these links, with an individual throughput of 400MB/sec over a distance of 200m, is required. The interface specification for these links as well as recent hardware developments are presented in this paper.

After reviewing the architecture and design of the CMS data acquisition system, the requirements on the front-end data link and the different possible topologies for merging data from the front-ends are presented. The front-end data link is a standard element for all CMS sub-detectors: its physical specification as well as the data format/protocol are elaborated within the Readout Unit Working Group where all sub-detectors are represented. The current state of the link definition is covered. Finally, prototyping activities towards the final link as well as test/readout devices for Front-End designers and DAQ developers are described.

N. Bondar*, T. Ferguson**, A. Golyash*, V. Sedov*, N.Terentiev**
bondar@fnal.gov
* Petersburg Nuclear Physics Institute, Gatchina, 188350, Russia
** Carnegie Mellon University, Pittsburgh, PA, 15213, USA

The very front-end electronics system for the anode signals of the CMS Endcap Muon cathode strip chambers has been designed. Each electronics channel consists of an input protection network, amplifier, shaper, constant-fraction discriminator, and a programmable delay with an output pulse width shaper. The essential part of the electronics is an ASIC consisting of a 16-channel amplifier-shaper-discriminator (CMP16). The ASIC was optimized for the large cathode chamber size (up to 3 m x 2.5 m) and for the large input capacitance (up to 300 pf). The ASIC combines low power consumption (30 mW/channel) with excellent time resolution (~2 ns). A second ASIC provides a programmable time delay which allows the alignment of signals with an accuracy of 2.5 ns.

The very front-end electronics system for the anode signals of the CMS Endcap Muon cathode strips chambers has been designed. The main tasks of the anode side of the detector are to provide a good time resolution and a high efficiency. To meet this requirement, the following measures were implemented:

-each channel was split into two parts: an analog section (amplifier-shaper-discriminator), followed by a digital delay and pulse width shaper.
-the analog part was placed as close to the anode outputs as possible, and the digital part was located on the input of the anode local charged track board (ALCT). -the amplifier input circuits were very carefully arranged and shielded.

Two ASICs were designed. The first is a 16-channel amplifier-shaper-discriminator (CMP16). The ASIC was optimized for the large chamber size (up to 3 m x 2.5 m) and for the large input capacitance (up to 300 pf). The ASIC combines low power consumption (30 mW/channel) with excellent time resolution (~2 ns). The chip is made by AMI, using a BiCMOS 1.5 micron technology. To achieve a low input resistance and relatively low noise, a BJT was used as an amplifier first stage. A two-exponent tail cancellation system, with a semi-Gaussian shaper is also employed in the chip. A two-thresholds constant-fraction discriminator is used to obtain the required time resolution. Output signal levels are LVDS standard.

The second ASIC is a 16-channel LVDS/TTL converter, with a programmable delay and output pulse width shaper. This chip was also made by AMI, using a CMOS 0.5 micron technology. The chip is a logical extension of the CMP16 chip in that it matches the amplifier outputs to the ALCT logic inputs and aligns the signals in phase at the input of the anode logic.

To support the CMP16 chip, a 16-channel anode front-end board (AD16) was also designed. The board was made in the simplest and cheapest way possible. The threshold control network and the board test facility were delegated to the ALCT board. Each AD16 board is connected to the ALCT board with a 40-wire cable. This cable supplies the board with power, a threshold voltage setting and test pulses, as well as transmits the output signals to the ALCT. A special setup and accompanying procedures were designed to test and certify the AD16 boards and the two ASICs.

The anode front-end electronics system has met the required specifications, and the mass production has begun.

P.Aspell, D.Barney, P.Bloch, A.Go, C.Palomares
Paul.Aspell@cern.ch

DeltaStream is a 36 channel preamplifier and shaper ASIC that provides low noise, charge to voltage readout for capacitive sensors over a large dynamic range. The chip has been designed in the DMILL BiCMOS radiation hard technology for the CMS Preshower project. Two gain settings are possible. High gain (HG), has gain 30mV/MIP (7.5mV/fC) for a dynamic range of 0.1 to 50 MIPS (0.4fC – 200fC) and low gain (LG), has gain 4mV/MIP (1mV/fC) for a dynamic range of 1 to 400 MIPS (4fC – 1600fC). The peaking time is ~25ns and the noise has been measured at ~ENC = 680e + 28e/pF. Each channel contains a track & hold circuit to sample the peak voltage followed by an analog multiplexer operating up to 20MHz. The response of the signal is linear throughout the system. The design and measured results for input capacitance < 55pF are presented.

DeltaStream has an architecture that follows in the Amplex family of silicon sensor readout ASICs. It contains 36 channels, each of which contains a low noise preamplifier, shaper and a track & hold circuit to sample the peak voltage. An analog multiplexer then serializes the analog values into a single analog data stream.

DeltaStream has been developed to provide a readout ASIC suitable for the production testing of the CMS Preshower silicon sensors. It also serves as a multi-channel prototype chip for the preamplifier and shaper (Delta) and a 20MHz analog multiplexer intended for use within the Preshower front-end electronics analog memory ASIC called PACE.

DeltaStream is designed to be dc coupled to silicon sensor strips and is insensitive to dc leakage currents < 50mA per strip. Charge to voltage readout over a large dynamic range (< 400 MIPs) for total input capacitance up to 55pF with 25ns peaking times are the main design goals. Two gain settings are possible. High gain (HG), has gain ~30mV/MIP (7.5mV/fC) for a dynamic range of 0.1 to 50 MIPS (0.4fC – 200fC) and low gain (LG), has gain ~4mV/MIP (1mV/fC) for a dynamic range of 1 to 400 MIPS (4fC – 1600fC).

Measurements of gain, rise time and noise have been made in both HG and LG for two different levels of total input capacitance (13pF, 52 pF). The mean gain is as follows : HG (13 pF) = 33.1 mV/MIP, HG (52 pF) = 24.6mV/MIP, LG (13 pF) = 4.6 mV/MIP, LG (52 pF) = 3.4 mV/MIP. The rise time measured from 10-90% of the peak voltage is HG (13pF) = 18.9ns, HG (52pF) = 21.8ns, LG (13pF) = 14.5ns, LG (52pF) = 17.5ns, The standard deviation across all channels is ~3% for gain and ~1% for the rise time.

Noise has been measured for all the channels in high gain resulting in a mean value of ENC = 680e + 28e/pF.

The multiplexer operates at frequencies up to 20MHz with a linear response. It can also be used to individually select a channel allowing the full pulse shape to be readout.

Authors list with Institutions:
Franco Gonella from Dip. di Fisica dell'Universita' di Padova and Sezione INFN di Padova, Padova, Italy
franco.gonella@pd.infn.it

Matteo Pegoraro from Sezione INFN di Padova, Padova, Italy

Paper category :
LHC Experiment: CMS
LHC Experiment Subsystem: MU
LEB2001 Workshop topic: Electronics for muon detectors

To meet frontend electronics needs of CMS barrel muon chambers a full custom ASIC, named "The MAD", has been first developed by INFN of Padova and then produced in over 50.000 pieces to equip the 180.000 drift tubes. The chip provides 4 identical chains of amplification, discrimination and cable driving circuitry; also it integrates a flexible channel enabling/disabling capability and a temperature probe for monitoring purposes. The ASIC has been deeply tested resulting in good performances; particularly, big effort was put in radiation (neutron, gamma rays and ions) and ageing tests to check behavior and reliability in LHC environment.

The analog frontend electronics for the muon chambers of CMS barrel has been integrated in a full custom ASIC, named "The MAD", developed by INFN Padova using 0.8 µm BiCMOS technology from Austria Mikro Systeme. Each chip provides the signal processing for 4 drift tubes in a 2.5x2.5mm2 die housed in a TQFP44 package.The 4 identical analog chains contained in the ASIC are made of a charge preamplifier followed by a simple shaper with baseline restorer, whose output is compared against an external threshold by a latched discriminator; the output pulses are then stretched by a programmable one shot and sent to an output stage able to drive long twisted pair cables with LVDS compatible levels. The working conditions of the detector set requirements for high sensitivity and speed combined with low noise and little power consumption. Moreover, as the basic requirement for the frontend is the ability to work at very low threshold to improve efficiency and time resolution, a good uniformity between channels of different chips is needed for sensitivity and threshold. Gain value is 3.3 mV/fC in average, constant up to 500 fC input with less than 1% integral nonlinearity; saturation occurs at about 800 fC. Threshold uniformity is very good, the r.m.s. is below 0.6 mV and the propagation delay is about 4 ns for signals above 30fC. Key characteristics for low threshold operation are noise and crosstalk: bare chips exhibit ENC ??1400 e- (slope of 60 e-/pF) and a value below 0.1% for the latter. Once mounted on the PCB these two figures increase to 1900 e- and 0.2% mainly because of the input protection network necessary to prevent HV discharge events. The power dissipation of the chip is very low, about 25 mW/channel so reducing the need for heat removal. Control and monitoring features have been included in the chip: to mask noisy wires each channel can be disabled at the shaper input resulting in little crosstalk to neighbors. It's also possible to check trigger functionality using a fast disable/enable feature, controlled via LVDS levels, acting on the output driver of left and right channel pairs. An absolute temperature probe with a sensitivity of 7.5 mV/(K has been integrated in order to detect electronics failures and monitor environmental changes. Two separate power supplies (5V and 2.5V) are used in order to reduce power drain and minimize interference between input and output sections. The routing has been particularly cured for power, digital ground and analog ground and many pins have been reserved for this purpose. Reliability is a critical point in a hardly accessible environment as CMS detector: tests performed (accelerated ageing and irradiation with neutrons, heavy ions and gamma rays) show good MTBF characteristics, low SEU rate and immunity to latch-up events in spite of using a standard and not too expensive technology.

T.Ferguson ferguson@cmuhep2.phys.cmu.edu, N.Terentiev (teren@fn781a.fnal.gov)

(Carnegie Mellon University, Pittsburgh, PA, 15213, USA)

N.Bondar bondar@fnal.gov, A.Golyash, V.Sedov

(Petersburg Nuclear Physics Institute, Gatchina, 188350, Russia)

We report the results of several radiation tests on pre-production samples of the anode front-end electronics boards for the CMS endcap muon system. The crucial component tested was the 16-channel preamplifier ASIC (BiCMOS). The boards were exposed to doses up to 80 krad in a 63 MeV proton beam, and to a neutron fluence up to 2*10**12 n/cm**2 from a nuclear reactor. The static (current and voltage) and dynamic (noise,threshold, gain and timing) characteristics were measured versus the radiation dose.

The peak luminosity of LHC, 10**34 cm**-2*sec**-1, combined with the 7 TeV beam energy, will create a very hostile radiation environment in the detector experimental halls. Radiation tolerance and reliability are important issues for the CMS electronics, including the endcap muon CSC front-end electronics. The most severe conditions in the muon endcap region are in the vicinity of the ME1/1 CSC chambers. Here, the neutron fluence and the total ionizing dose (TID) accumulated during 10 years of LHC operation are expected to be about 6-7*10**11n/cm**2 (at En>100 keV) and 1.8-2 krad, respectively (Ref.1). The goal of our measurements was to test the performance of the anode front-end boards, with specially designed preamplifier chips (AMI 1.5 micron BiCMOS technology) on them, up to a level of 3 times these doses, and to observe the presence of single-event effects such as latch-up, at higher doses (Ref.2).

The boards were irradiated in a 63 MeV proton beam and received a TID up to 14 and 80 krad. No latch-ups or spikes or any changes in the static parameters (amplifier, discriminator and regulator voltages) were observed. However, the dynamic parameters such as threshold, gain and slewing time were sensitive to the radiation, showing a maximum deviation of 40% (for slewing time) at a TID of 60 krad. The noise and the resolution time were not affected at all. At the required 3 times level of TID (5-6 krad), all changes were practically negligible. The corresponding graphs will be presented. Some boards were exposed to a reactor neutron fluence up to 2*10**12 n/cm**2, at a neutron energy of 100 keV < En < 10 MeV. They also received a TID of about 50-60 krad from gammas which accompanied the reactor neutrons. About 50% of the boards survived, showing moderate changes (20-30%) in dynamic characteristics in a test taken one month after the irradiation. The rest of the boards recovered after one week of heating at 110 degrees C. Further heating returned all the parameters for all boards to the norm. From our results we can roughly estimate that, for the test doses given above, the annealing time is about a few months at room temperatures. Since the LHC rate of real radiation exposure is much slower than this, we conclude that the anode front end boards should not show any radiation damage during normal LHC operation.We are thankful to M. Tripathi and B. Holbrook of the University of California, Davis, and to T.Y. Ling and B. Bylsma of the Ohio State University for their valuable help.

G.M.Dallavalle, A.Montanari, F.Odorici, G.Torromeo, R.Travaglini, M.Zuffa
INFN and University, Bologna, Italy
Marco.Dallavalle@bo.infn.it

The Track-Sorter-Master (TSM) is an element of the on-chamber trigger electronics of a Muon Barrel Drift Tube Chamber in the CMS detector. The TSM provides the chamber trigger output and access to the trigger electronic devices for monitoring and configuration. The specific robustness requirements on the TSM are met with a partitioned architecture based on antifuse-FPGAs. These have been successfully tested with a 60 MeV proton beam: SEE and TID measurements are reported.

Drift Tubes Chambers (DTCs) are used to detect muons in the barrel of the Compact Muon Solenoid (CMS), which will collect data at the future Large Hadron Collider (LHC) of CERN. In LHC, two proton beams of 7 TeV will collide at a bunch crossing frequency of 40 MHz. Electronic devices installed on the DTCs analyse every bunch crossing, with no deadtime, and search for possible muon track segments. In particular, the Trigger Server system (TS) examines the search results from smaller sections of a DTC, rejects fakes and duplicates, and selects the best two segments overall, thus reducing the chamber output by a factor of 25.

Because of the limited accessibility of front-end electronics and the high neutron flux expected in the CMS cavern, priority in the TS design is given to partitioning and to remote control and testability. The TS architecture is a compromise between optimal partitioning, for minimising the impact of failures, and minimal trigger latency, in order to limit event data buffering. In the TS, muon track segment selection is performed in two steps: Track Sorter Slave (TSS) units (each serving 1/7 of a DTC) in the first layer feed Track Sorter Master (TSM) units (one each DTC) in the second layer. For the TSS, we designed a 0.5 micron CMOS ASIC implementing an ad-hoc fast sorting algorithm. Overall, in the CMS muon barrel about 1300 TSS ASICs will perform as a single synchronous system. The TSM does the final selection and provides access to the TSSs for monitoring and configuring.

The TSM is partitioned in several distinct blocks with partial redundant functionality, and automatic failure detection and re-configuring. For manufacturing the TSM blocks, antifuse-FPGAs, which have permanent configuration once programmed, are chosen, after their radiation tolerance has been successfully tested for use in LHC. Single Event Effect and Total Irradiation Dose measurements for the Actel A54SX antifuse-FPGAs were performed using a 60 MeV proton beam. The chips show good tolerance to high radiation doses of 10 to 70 Krads. For Single-Event-Upsets, we set an upper- limit cross-section of 2.9/10^12 cm2 (90% c.l.) per chip.

L. Baksay, P. Raics, Zs. Szabó, L. Molnár, G. Pszota
Institute of Experimental Physics, Debrecen University, Debrecen, Hungary

A. Fenyvesi, J. Molnár,
Institute of Nuclear Research (ATOMKI), Debrecen, Hungary

Gy. L. Bencze
Institute of Particle and Nuclear Physics, Budapest, Hungary
CERN, Geneva, Switzerland

L. Brunel
Institute of Experimental Physics, Debrecen University, Debrecen, Hungary
CERN, Geneva, Switzerland

D. Novak
Royal Institute of Technology, Stockholm, Sweden

Abstract

Components (LED light sources, LED driver and controller electronics, lens and video-sensor) of the barrel muon position monitoring system of the LHC CMS experiment have been irradiated with p(17.5 MeV)+Be neutrons. The tests were performed at the MGC-20E cyclotron of ATOMKI (Debrecen, Hungary). The neutron fluences delivered to the components were 2.6E+12 n/cm2 and 8.0E+13 n/cm2 (the expected values for the Barrel Muon and ME1/1 chambers, respectively). Changes of the electrical and optical characteristics were investigated.

This work was supported by the Hungarian National Research Fund (OTKA). Contract Nos.: T026184 and T026178.

Summary

Performance of the muon detecting system of the CMS detector of the Large Hadron Collider (LHC) is affected by the position and orientation of the individual chambers. In the case of the barrel muon detectors, their alignment will be controlled on the basis of the information that is provided by the position monitoring system. This system will consist of LED light sources, LED driver and controller electronics, optical lenses and video-sensors. They will have to work in a radiation environment, where the highest expected flux of the neutron component is about 1.0E+03 n/cm2/sec, and the estimated time of operation is 5.0E+10 sec. The total expected neutron flux is 2.6E+12 n/cm2 and 8.0E+13 n/cm2 for the Barrel Muon and ME1/1 chambers, respectively. Radiation damage induced by neutrons can alter electrical and optical characteristics of the components and thus the accuracy of the whole barrel muon position monitoring system.

Neutron radiation hardness tests of the components to be used in the Barrel Muon Alignment System were carried out using the broad-spectrum p(17.5 MeV)+Be neutron source ( 0 < En < 18 MeV, < En> = 3.7 MeV) of ATOMKI (Debrecen, Hungary).

Low current high intensity point-like LED light sources emitting at 660 nm (Type: FH1011, Stanley Electric Co. Ltd.) were irradiated up to 2.6E+12 n/cm2. Three modes of operation were studied: a) voltage on permanently, b) voltage off permanently and c) voltage on for 1 sec and off for 19 sec. For all of these modes of operation, the light yield decreased almost linearly as a function of the neutron fluency and approximately 50 % decrease was observed at the end of the irradiation. No other change in the electrical and spectral characteristics was measurable.

LED current driver and controller electronics with Microchip PIC16F84 processors were irradiated up to 8.0E+13 n/cm2. Some 20 % loss of the output currents of the LED controllers was observed at the end of the irradiation. The degradation of the current drivers was negligible below 1.0E+11 n/cm2 (the expected fluency at the position of operation of the device). Two processors were studied. Both damaged only after delivering ~ 2.0E+13 n/cm2 neutron fluency to them as the dramatically increased current consumption of the electronics indicated.

Plano-convex single lenses were irradiated up to 8.0E+13 n/cm2. They were made of BK7 glass without coating and their diameter was 10 mm. No measurable change of the spectral transmission and the refraction (focal length) was observed.

VM5402 video cameras with VV5402 CMOS sensor device (VLSI Vision Ltd.)were irradiated up to 2.8E+12 n/cm2. The radiation damage of the sensor resulted in the altered nearly Gaussian distribution of the light sensitivity of the individual pixels in all modes of operation. The mean values decreased while the sigma values increased in all three modes ( a) voltage on permanently, b) voltage off permanently and c) voltage on for 1 sec and off for 19 sec). Apart from the general sensitivity loss, the spectral sensitivity of the sensor did not change.

Giovanni Cervelli
Alessandro Marchioro, Alessandro.Marchioro@cern.ch
Paulo Moreira, pmoreira@sunvlsi.cern.ch
Francois Vasey
CERN, EP Division, CH 1211 Geneva 23, Switzerland

A 3-way Laser Driver ASIC has been implemented in deep-submicron CMOS technology, according to the CMS Tracker design and rad-tolerance requirements. While being optimised for analogue operation, the full-custom IC is also compatible with LVDS digital signalling. It will be deployed for analogue and digital transmission in the 50.000 fibre link of the Tracker. A combination of linearization methods allows achieving good analogue performance (8-bit equivalent dynamic range, over 100MHz), while maintaining wide input common-mode range (±250mV) and limited power dissipation (30mW). The linearly amplified signals are superposed to a DC-current, pre-settable over a wide range (0-60mA). The driver gain is pre-settable via a SEU-robust serial interface. ASIC qualification and system test results are discussed in the paper.

Data connection to the CMS Tracker Front-Ends is provided by a large number of optical fibre links: 50.000 analogue for readout and ~3.000 digital for trigger, timing, and control signals distribution. The Front-End components must withstand the harsh radiation environment of the Tracker, over the planned detector lifetime of 10 years. The baseline technology for ASIC developments in the Tracker is a 0.25µm CMOS, 3-metals, commercial technology (5nm oxide thickness). The intrinsic radiation tolerance of this technology is increased to the required levels, by using an appropriately extended design-rule set. A new Laser Driver has been implemented in this technology, matching the Tracker modularity and functionality requirements.

The IC modularity is 3-channels per chip. Each individual channel converts a differential input voltage into a single-ended output current superimposed to a pre-settable DC current (0-60mA). The latter allows to bias the laser diode above threshold and to track the amount of threshold-drift expected during LHC operation. Input signals are transmitted to the laser driver using 100? cable up to 30 cm long. The driver is optimised for analogue operation (good linearity, low noise), but the input voltage levels are also compatible with the digital LVDS standard (±400mV, on 100?). The channels can be individually addressed via a serial I2C interface, allowing individual power down, gain control, and pre-bias control. Robustness to Single Event Upsets is achieved by tripling the digital logic and by using a majority voting decision scheme. About 20.000 such devices will be packaged in a 5x5 mm LPCC case for ease of testing and installation in the Tracker readout and control hybrids.

The Linear Driver consists of a degenerated PMOS differential pair and a push-pull output stage. The differential pair, compared with alternative design solutions, is conceptually simple and offers good dynamic and noise performance at limited power dissipation. The required linearity is obtained with a combination of two source-degeneration methods: a parallel source-degeneration resistor, and a source-bulk cross-connection between the transistors of the differential pair. The combination of these two methods allows keeping the degeneration resistor to a value compatible with the required input common-mode range. Three switchable output stages can be activated in parallel, to provide four different selectable gains. To minimise the cross talk within a same chip, each individual channel contains its own independent bias circuit and power-down logic. The power dissipation of the Linear Driver is below 30 mW per channel and the current consumption is constant, to avoid cross talk among the ICs. The design has been implemented in the 0.25 µm CMOS technology, taking special care to isolate all parasitic conduction paths which could arise as a consequence of ionising radiation.

The ASIC qualification will be completed before the conference, except for SEU testing which is foreseen for Autumn 2001. A prototype version of the device (using the same analogue blocks and redundant functionality) has been included in the CMS Tracker System Test currently under preparation. The final device performance and functionality will be presented at the conference. The production test program and equipment is being optimized for fast execution (pass/fail) with highest possible fault coverage.

G. M. Bilei, M. T. Brunetti (corresponding author), F. Ceccotti, B.Checcucci,V. Postolache, A. Santocchia
mariateresa.brunetti@pg.infn.it

A new circuit for the conversion of analogue electrical signals into the corresponding optical ones has been built and tested by the CMS group of Perugia. This opto-hybrid circuit will be used in the read out electronics of the inner barrel part of the CMS tracker. The opto-hybrid is a vetronite circuit equipped with one programmable laser driver chip and up to 3 laser diodes, all being radiation tolerant. The description of the circuit and its performances are reported and discussed.

The opto-hybrid circuit is employed in the analogue optical link of the CMS inner barrel and converts the analogue electrical signal coming from silicon detectors and sampled by the APV chips into the analogue optical signal to be transmitted via optical fibres. The opto-hybrid is an FR4 (vetronite) circuit with dimensions of 30 x 22 mm2. The active devices are a programmable laser driver chip and up to 3 laser diodes (output channels). The laser driver through an I2C interface biases each laser diode in its linear response region. Analogue input signals up to +/- 300 mV from the MUX connected to the APV chips modulate the bias currents. The optical fibres escaping from each laser diode carry the analogue signal, which will be converted again, out of the beam area, into an electrical signal and is finally digitised for acquisition and analysis. For test purposes the opto-hybrid has been temporarily connected to ancillary circuits for power supply and signal injection. The test set-up includes an optical receiver, which converts the optical signal into the electrical output to be read by the scope or by the spectrum analyser. A set of routines, written in Labview 5.1, allows the remote control of the instruments and the automatic execution of the electrical tests. For a preliminary validation of the opto-hybrid circuits, the measurements to be performed are gain, integral-non-linearity, signal-to-noise ratio, crosstalk and bandwidth. The gain of the optical link is defined as the ratio between the output electrical signal and the corresponding pulse injected at the opto-hybrid input and is pre-settable through the programmable laser driver up to a value of 2.5. The gain test has shown a good agreement between the measurements and the values set via the laser driver. The integral-non-linearity (INL) test gives the deviation from a linear fit of the measured output values versus an increasing input voltage. The tested opto-hybrid chips have shown an INL estimated to be less than 3%, according to the request asked for its performances. The crosstalk is the noise measured on adjacent channels when one laser chip is pulsed. This test was affected by an impedance mismatch, which will be removed in further measurements, but the low noise values found were, nevertheless, encouraging. In order to completely characterise the opto-hybrid behaviour, thermal cycles and irradiation with particles are foreseen. All these tests will guarantee the correct operation of the opto-hybrid once in the hostile environment of the LHC tunnel.

K. Gill, R. Grabit, M. Hedberg, J. Troska, F. Vasey and A. Zanet
CERN EP Division.

Corresponding Author :
karl.gill@cern.ch

Dr Jan Troska
(: +41 (0)22 767 2063
Fax: +41 (0)22 767 2800
CERN, EP Division
CH-1211 Geneva 23
Switzerland
Email: jan.troska@cern.ch

The QA programme for the environmental tests of the COTS components for the CMS Tracker Optical link system is presented. These tests will take place in the pre-production and final production phases of the project and will measure radiation resistance, component lifetime, and sensitivity to magnetic fields. The results are summarized from the extensive series of earlier prototype sample testing and the evolution of these small-scale tests to the pre-production final manufacturing tests is outlined.

Final production of the CMS Tracker optical links will begin in 2001 and continue until 2004. Approximately 40000 uni-directional analogue optical links, and ~1000 bi-directional digital optical links will be produced during this time. Full details of the two types of optical link system, including the quantities of components and their specifications, can be found on the web[1].

Both analogue and digital optical links for the CMS Tracker share the same basic components, namely 1310nm InGaAsP/InP multi-quantum-well edge-emitting lasers and InGaAs p-i-n photodiodes coupled to single-mode optical fibre. The optical fibre is in the form of buffered single-way fibre, ruggedized 12-way ribbon fibre cable, and dense 96-way multi-way ribbon cable, with MU-type single way and MT-type multi-way optical connectors used at the various optical patch panels. All of the devices listed here are commercial off-the-shelf (COTS) components.

Quality Assurance (QA) procedures have been developed in order to guarantee that the final links meet their specified performance and are produced on schedule. A full QA manual has been written and in this paper we focus on the part of the QA programme concerning environmental testing of components.

The CMS Tracker environment is characterized by the high levels of radiation, up to ~2x10^14/cm^2 fluence and 100kGy ionizing dose for the optical link components over the first 10 years of operation[2]. The particle fluence at the innermost detector modules of the Tracker is dominated by pions and photons, with energies ~100MeV, and by ~1MeV neutrons at the outermost modules. In addition the components must operate in a 4T magnetic field and at temperatures close to -10§C.

The extensive use of COTS components in the optical links means that all prototype devices have had to be thoroughly tested. The resistance to radiation and magnetic fields are not product characteristics that are normally specified or guaranteed by telecommunications manufacturers. In extensive prototype sample tests we have measured the radiation effects in all of the optical link components, for fluences and doses typical of CMS Tracker worst-case conditions[3]. The set of results will be summarized in the full paper.

Despite having restricted the final choice of candidate components to those that have passed earlier sample tests, the use of COTS means that environmental QA testing must continue into the production phase of the project. This is simply because the factors that can affect the radiation hardness of given components are not well understood in terms of their sensitivity to any changes, however slight, in the component production method. These tests are separated into 'Advance Validation' and 'Pre-production Qualification'. In the case of the lasers, p-i-n photodiodes and the optical fibres, given the large quantities required and their observed sensitivity to radiation damage, it is desirable to do the radiation tests before the final lots have been produced and delivered to CMS. These tests are therefore carried out as Advance Validation tests which means that we will carefully screen every wafer, in the case of lasers and p-i-n photodiodes, and every glass preform, in the case of optical fibres, using a number of representative samples. It is understood that this is an unusual method of component validation, necessitating a very good working relationship with the component manufacturers.

For the other components, namely the hybrids and the terminated optical cables where there are fewer devices required, or where the radiation damage is expected to be less significant, the environmental tests will be carried out as part of the more general Pre-production Qualification.

[1] CMS Tracker Optical Links www pages, http://cms-tk-opto.web.cern.ch
[2] CMS Tracker Technical Design Report.
[3] Papers in previous LEB Workshop, RADECS and SPIE Proceedings.
(1996-2001). All available at [1].

N. Almeida, V. Antonio, N. Cardoso, A. Correia, P. Machado, J. C. Silva, I.Teixeira, J. Varela,
LIP, Lisbon and INESC, Lisbon
joao.varela"@cern.ch

The Data Concentrator Card is a module in the CMS Electromagnetic Calorimeter Readout System responsible for data collection in a readout crate, verification of data integrity and data transfer to the central DAQ. The DCC should sustain an average data flow of 200 Mbyte/s. In the first part of the paper we summarize the physics requirements for the ECAL readout and give results on the expected data volumes obtained with the CMS detector simulation (ORCA software package). In the second part we present the module's design architecture and the adopted engineering solutions. Finally we give results on the expected performance derived from a detailed simulation of the module's hardware.

Authors
J. Troska, K. Gill, R. Grabit, M. Hedberg, F. Vasey and A. Zanet
CERN
A. Go
Department of Physics, National Central University, Taiwan
M.-L. Chu
High Energy Physics Laboratory, Institute of Physics, Academia Sinica, Taiwan

Corresponding Author
Jan Troska jan.troska@cern.ch
( : +41 (0)22 767 2063
Fax: +41 (0)22 767 2800

CERN, EP Division
CH-1211 Geneva 23, Switzerland

Prototype analogue optohybrids have been designed and built for the CMS Tracker Outer Barrel and End Cap detectors. The total requirement for both types in CMS is 12900 that will be assembled between 2002 and 2004. Using very close to final optoelectronic and electronic components several optohybrids have been assembled and tested using standardised procedures very similar to those to be implemented during production. Analogue performance has met the specifications in all cases when operated in isolation and when inserted into the full prototype optical readout system.

The CMS Tracker optical readout system will consist of approximately 40000 uni-directional analogue optical links production of which is due to commence in 2001 and continue until 2004[1]. Within the CMS Tracker the transmitting elements of the analogue optical links will be housed on analogue optohybrids that interface directly to the silicon detector modules[2]. Either two or three laser diodes (depending upon the location within the Tracker) and the associated laser driver ASIC will be mounted on an analogue optohybrid (AOH). The total requirement of optohybrids is 4000 for the Tracker Inner Barrel and Disks, 5800 for the Tracker Outer Barrel (TOB) and 7100 for the Tracker End Caps (TEC).

The availability of very close to final optoelectronic components has allowed prototyping of an AOH design suitable for the TOB and TEC detectors. The PCB design, that has been carried out by CERN and produced in Taiwanese industry, can be used in both TOB and TEC by simple differential assembly of the connector on either the top- or bottom-side of the printed circuit board. The PCB measures 23mm by 30mm, is 0.5mm in thickness and accommodates two or three laser diodes, the laser driver ASIC and associated passive components. All components mounted on the prototype optohybrids (laser diodes, laser driver, optical and electrical connectors) are final or very close to final designs. An interface to the final cooling arrangement within the TOB and TEC has also been incorporated.

Two types of candidate laser diode from different manufacturers have been assembled onto prototype optohybrids which have then been submitted to a full test of the specifications to demonstrate that they will meet the requirements of use within the CMS Tracker optical readout system. Prototype optohybrids have been evaluated using the standard CMS Tracker test methods described previously[3,4]. The testing carried out has demonstrated the required performance in response to both static and dynamic test suites that mimic operation within the full analogue optical link system. Noise is within the system specification of 48dB and integral non-linearity within the operating range of the optical links meets the target of 1%. Dynamic measurements show that the bandwidth of the components is not degraded by placement on the optohybrid adding further weight to the validation of the optohybrid design. Measurements have been carried out at room temperature, 0øC, -10øC and -20øC and although some variations in the laser characteristics were observed these did not significantly degrade their performance in the optical readout system.

In addition to the standalone lab testing using standard procedures the analogue optohybrid prototypes were re-tested in a full optical readout system with a close to final design of the 12-way analogue receiver module. Results of these tests show that the prototype optohybrids perform well in this environment. Once validated the prototype optohybrids of TOB type will be included in the electronic system test carried out at CERN where their performance will be assessed as part of the entire electronic readout system of the CMS Tracker.

[1] The Tracker System Project Technical Design Report, CERN/LHCC 98-6, CMS TDR 5, 15 April 1998 & Addendum CERN/LHCC 2000-016, CMS TDR 5 Addendum, 1, 21 February 2000
[2] Specifications of the Optical Link System are available from URL http://cern.ch/cms-tk-opto
[3] A 4-channel parallel analogue optical link for the CMS-Tracker, F.Vasey et al., Proc. of the fourth workshop on electronics for LHC experiments, Rome, 1998, pp. 344-348
[4] Evaluation and selection of analogue optical links for the CMS tracker - methodology and application, F.Jensen et al., CMS Note 1999/074

Authors :
G.Magazzu' - INFN Sezione di Pisa
A.Marchioro, P.Moreira - CERN

A key component for monitoring environmental parameters like temperature, silicon detector leakage currents, power supply voltages and currents in the LHC detector environment is a rad-hard, low-power multi-channel A/D converter. For these applications in the CMS central tracker we have designed and developed an integrated circuit, the Detector Control Unit (DCU). The core of the DCU is an 8-channel 12-bit A/D converter controlled through a standard I2C interface. The structure and the performance of this ADC are desribed in the paper.

Silicon detectors, when exposed to the high level of radiation in the LHC experiments, are subject to a number of damaging phenomena demanding careful monitoring of their environmental conditions. In the CMS central tracker the detector leakage currents in the range of 100uA to 10mA are measured using sensing resistors and the temperature in the range of -20 deg C to +20 deg C is monitored using appropriate thermistors. The supervision of other parameters like the local supply voltages and the temperature of the hybrids housing the front-end integrated circuits is also performed. All these quantities need to be read and logged with relatively low frequency, therefore a fast conversion time is not required. A highly integrated and low-power solution is required because of the strict requirements in terms of space and power dissipation. The Detector Control Unit (DCU) has been developed to perform all the requested functions in one single integrated circuit. This ASIC consists basically of a 12-bit A/D converter that uses a single slope architecture, preceded by an 8 input analog multiplexer. 8 inputs are available to measures voltages in the range 0V to 2.5V (rail-to-rail, since the power supply voltage is 2.5V). The A/D conversion time is ~0.2ms. Two operating modes are available: in the "low input range" mode (0V to 1.5 V) the input signal is referenced to GND while in the "high input range" mode (1.0V to 2.5V) the signal is referenced to VDD. In both operating modes the measured non-linearity is less than 1 LSB with no missing codes. To achieve the rail-to-rail input compatibility the analog circuitry uses a complementary solution based on a pair of NMOS and PMOS comparators and has an automatic offset cancellation scheme. A 100pF metal-to-metal capacitor is charged from GND or discharged from VDD, according to the selected mode, using stable and temperature independent currents derived from an on-chip band-gap reference. Two temperature independent and stable current reference outputs (10uA and 20uA) are also provided to bias the external temperature sensing thermistors. A custom on-chip temperature sensor measures the temperature of the substrate housing the ASIC. The DCU is interfaced to the Tracker Control System via a standard I2C port, through which the user can start an on-chip temperature sensor acquisition, fix the A/D converter operating mode, select one of the 8 inputs, start an A/D conversion and read the conversion result. The digital part of the chip uses triple redundancy and majority voting to ensure protection against SEU effects. The DCU is designed in a commercial quarter micron technology using special layout techniques to enhance its radiation tolerance. The total chip area measures 2.0x2.0 mm2, contains 28 pins and the power consumption is less than 50mW. The circuit has been submitted to fabrication and fully characterized. Its architecture and the measured performance will be presented in the paper.

P. Chumney, S. Dasu, F. di Lodovico, M. Jaworski, J. Lackey, P. Robl, W.H.Smith
University of Wisconsin – Madison
Wesley H. Smith
University of Wisconsin Physics Department
1150 University Ave. Madison, Wisconsin 53706 USA
( : (608)262-4690,
Fax: (608)263-0800,
email: wsmith@wishep.physics.wisc.edu
http://hep.wisc.edu/wsmith/

The CMS regional calorimeter trigger system detects signatures of electrons/photons, taus, jets, and missing and total transverse energy in a deadtimeless pipelined architecture. This system contains 19 crates of custom-built electronics. Recent changes to the Calorimeter Trigger have been made to improve the efficiency and purity of jet and tau triggers. The revised algorithms, their implementation in hardware, and their performance on physics signals and backgrounds are discussed.

The CMS Regional Calorimeter Trigger receives compressed data from the calorimeter readout electronics on 1.2 GBbaud copper links, each carrying data for two HCAL or ECAL trigger towers. 19 total crates (18 for the barrel/endcap and one for both forward calorimeters) each contain seven rear mounted Receiver cards, seven front mounted Electron Isolation cards, and one front mounted Jet Summary card plugged into a custom point-to-point 160 MHz differential ECL backplane. Each crate transmits to the global calorimeter trigger processor its sum Et, missing energy vector, 4 highest-ranked isolated and non-isolated electrons, and 4 highest energy jets and 4 tau-tagged jets along with their locations.

The jet trigger uses the transverse energy sums (e.m.+had) computed in calorimeter regions (4x4 trigger towers), except in the HF region where it is the trigger tower itself. The input tower Et is coded in an 8 bit linear scale with programmable resolution. The subsequent summation tree extends to a 10 bit linear scale with overflow detection. Simulation studies showed that a scale of 10 bits with LSB = 1 GeV gives adequate jet trigger performance. The jet trigger uses a 3x3 calorimeter region sliding window technique which spans the complete (eta, phi) coverage of the CMS calorimeters seamlessly. The central region Et is required to be higher than the eight neighbour region ET values.

The jets and taus are characterized by the transverse energy Et in 3x3 calorimeter regions. The summation spans 12x12 trigger towers in barrel and endcap or 3x3 larger HF towers in the HF. The jets are labelled by (eta, phi) indexes of the central calorimeter region. For each calorimeter region a tau-veto bit is set ON if there are more than two active ECAL or HCAL towers in the 4x4 region. A jet is defined as "tau-like" if none of the 9 calorimeter region tau-veto bits are ON.

The four highest energy central and forward jets, and central taus in the calorimeter are selected. Jets and taus occurring in a calorimeter region where an electron is identified are not considered. The selection of the four highest energy central and forward jets and of the four highest energy taus provides enough flexibility for the definition of combined triggers. In addition counters of the number of jets above programmable thresholds in various eta regions are provided to give the possibility of triggering on events with a large number of low energy jets. Jets in the forward and backward HF calorimeters are sorted and counted separately.

The baseline implementation of jet clustering is based on the 160 MHz ASICs and point-to-point backplane technology developed for the CMS regional calorimeter electron/photon trigger. The entire eta-phi plane is covered by a single cluster crate that receives data from 18 Regional Calorimeter Trigger crates on parallel differential ECL links at 80 MHz and processes the data at 160 MHz. Another implementation under study incorporates the algorithm into the FPGA logic of the CMS Global Calorimeter Trigger.

Alex Madorsky
University of Florida/Physics
Museum rd & NS dr
Gainesville, FL, 32606, USA

(1-352-392-9849
fax: 352-392-8863

Development and Test of a Prototype Track-Finder for the Level-1 Trigger of the CMS Endcap Muon System

We report on the development and test of a prototype track-finding processor for the Level-1 trigger of the CMS endcap muon system. The processor links track segments identified in the cathode strip chambers of the endcap muon system into complete three-dimensional tracks, and measures the transverse momentum of the best track candidates from the sagitta induced by the magnetic bending. The algorithms are implemented using SRAM and Xilinx Virtex FPGAs, and the measured latency is 15 clocks. We also report on the design of the pre-production prototype, which achieves further latency and size reduction using state-of-the-art technology.

Development and Test of a Prototype Track-Finder for the Level-1 Trigger of the CMS Endcap Muon System

The endcap muon system of CMS consists of four stations (ME1-ME4) of CSC chambers on each end of the experiment, covering the range in pseudorapidity from 0.9 to 2.4. A single station is composed of six layers of CSC chambers, where a single layer has cathode strips aligned radially and anode wires aligned in the orthogonal direction.

The barrel muon system consists of four stations of drift tube chambers in the central region of CMS.

The purpose of the CSC Track-Finder is to link track segments from individual CSC stations into complete tracks, measure the transverse momentum from the sagitta induced by the magnetic bending, and report the best tracks to the Level-1 Global Muon Trigger. This objective is complicated by the non-uniform magnetic field in the CMS endcap and by the high background rates; consequently, the present design incorporates full three-dimensional information into the track-finding and measurement procedures. A momentum resolution of better than 25% has been designed in order to sufficiently reduce the rate of low momentum muons. A prototype of the CSC Track-Finder has been constructed, with a Sector Processor implementing the Track-Finding algorithms for a 60 degree azimuthal sector and three Sector Receivers collecting the data from the CSC chambers in that sector. The Sector Processor prototype uses 15 Xilinx Virtex FPGAs ranging from XCV50 to XCV400 to implement the track-finding algorithms. The total number of logic gates on board is about 2,200,000. The Sector Processor accepts 15 track segments from three Sector Receivers of the endcap muon system, and eight segments from the barrel muon system via a transition board in the back of the crate. The Sector Processor is pipelined with a latency of 15 clocks (375 ns).

The first prototype was completely debugged using internal 256-word deep FIFOs on the input and output. The input patterns were created using a CMS simulation, and the output of the Sector Processor was verified against a software model of the board. Random numbers were also used as input data for both the model and the prototype. In all tests, the prototype output matched the model exactly. The board was also tested with the Sector Receivers sending serialized data via the custom backplane at 280 MHz, and the result again matched expectations.

A second (pre-production) prototype of the Sector Processor will use state-of-the-art FPGAs from the Xilinx Virtex-E series. Use of these devices allows us to implement all Sector Processor logic into one FPGA (XCV1600E), saving board real estate and latency. There are also significant improvements in optical link technology that make it possible to implement the three Sector Receivers and one Sector Processor onto one 9U VME board. Therefore, instead of the 6 crates planned for the CSC Track-Finder at the time of the first prototype construction, the entire system will occupy just one crate. It will contain 12 boards, each sending output data via a custom GTLP backplane to a muon sorter located in the same crate.

E. Hazen, J. Rohlf, S. Wu - Boston University
hazen@joule.bu.edu
rohlf@bu.edu
wusx@bu.edu

Eric Hazen
Boston University Physics Dept
( 617/353-6120
Fax 617/353-3331
http://ohm.bu.edu/~hazen
Schedule at http://calendar.yahoo.com/public/eshazen/

The CMS HCAL data concentrator must combine data from about 600 front-end channels, with real-time synchronization and error-checking and an average throughput of 200 Mbytes/s. A modular implementation is described which is based on industry and CERN standards: PCI bus, PCI-MIP and PMC carrier boards, S-Link and LVDS serial links. A prototype has been built and tested using modular components. PC-MIP triple LVDS receivers collect data from front-end boards. A PMC logic board performs application-specific processing. A VME motherboard provides a standard platform and transparent access to monitoring and error registers. Test results and implementation details are described.

The CMS HCAL trigger/DAQ system consists of 9U VME crates with up to 18 trigger/readout modules, one data concentrator, and one readout controller. The CMS HCAL Trigger/Readout (HTR) module is a 9U VME module equipped with optical receivers, TTCrx circuitry, outputs on serial LVDS (Channel Link) and a custom mezzanine card. The optical inputs receive data from the HCAL front-end electronics, with one charge sample per bunch crossing. The CMS HCAL is a trigger detector, thus the HTR includes two data paths: the trigger path, which assigns Front-End data to a bunch crossing and sends them to the CMS regional trigger, and the DAQ path where the FE-data are pipelined, triggered and sent to the Data Concentrator Card.

The Data Concentrator Card is composed of a VME motherboard, six LVDS link receiver boards and a PMC-type logic board. The motherboard is a VME64x 9Ux400mm single-lot module. The motherboard supports VME access up to A64/D32, and contains three bridged PCI busses. Six PC-MIP mezzanine sites are arranged in groups of three on two 33MHz 32-bit PCI busses. A third 33MHz 64-bit PCI bus is bridged to the VME bus using a Tundra Universe II VME-to-PCI bridge. A single large logic mezzanine board has access to all three PCI busses for high-speed application-specific processing, and an additional standard PMC site is available. A local control FPGA on the motherboard provides access to on-board flash configuration memory, a programmable multi-frequency clock generator, and JTAG. The LVDS link receiver boards use Channel Link technology from National Semiconductor. Each board contains three links, which operate at a speed of 33MHz x 32-bits. On-board logic performs automatic event building, protocol checking, event number checking and bit error correction. A PCI slave interface provides single- and burst-read access to the data stream, plus numerous monitoring registers. On-board buffering for 128Kx32 words is provided for each link, with a fast "overflow warning" output.

The logic mezzanine board contains the core data concentrator logic. An on-board TTCrx stores level 1 accepts into an on-board FIFO. Two PCI interfaces read event fragments from up to 18 input links. A core FPGA with a large buffer memory builds events, performs extensive error-checking and monitoring, and outputs data to several destinations. The primary output is via S-Link to the DAQ. Additional outputs target the "trigger DAQ" stream for monitoring trigger performance, and a VME-accessible spy stream for monitoring.

A prototype of the entire system has been built. The HTR prototype uses 4 G-Link receivers running at 800 Mb/s. The DCC prototype uses three separate FPGAs for the PCI interfaces and a Xilinx XC2V1000 FPGA for the core processing logic. A 2Mx32 DDRSDRAM provides a memory buffer with 800Mbytes/sec transfer rate capability. A custom FE-emulator card is used to demonstrate the correct behavior of the system. Test results of the prototype are presented. Near term applications for this hardware include a high-rate radioactive source test at Fermilab in summer 2001 and a beam test at CERN in 2002 with several hundred front-end channels.

B. Allongue, F. Arteche, F. Szoncso
CERN
CH-1211 Geneve 23 Switzerland

C. Rivetta
FERMILAB
P.O.500 MS 222 Batavia Il 60510 U.S.A.
rivetta@fnal.gov

The design of DC power distribution for LHC front-end electronics imposes new challenges. Some CMS sub-detectors have proposed to use a DC-power distribution based on DC-DC power switching converters located near to the front-end electronics.

DC-DC converters operate as a constant power load. They exhibit a dynamic negative impedance at low frequencies that can generate interactions between switching regulators and other parts of the input system resulting in system instabilities. In addition, switching converters generate interference at both input and output terminals and can compromise the operation of the front-end electronics and neighboring systems. Appropriated level of filtering is necessary to reduce this interference.

This papers address the instability problem and present methods of modeling and simulation to assess the system stability and performance. The paper, also, addresses the design of input and output filters to reduce the interference and achieve the performance required.

EMI Filter Design and Stability Assessment of DC Voltage Distribution based on Switching Converters

A distinguish feature of LHC detectors is the enormous number of channels in the front-end electronics (FE) in all the sub-parts. It requires low-voltage output power supplies in the range of multi-kilowatts to bias such electronics read-outs. To minimize the volume of the distribution cables, some CMS sub-detectors are developing a DC power distribution based on DC-DC switching converters located near to the FE in the detector caverns.

Switching power supplies, in general, generate more noise than equivalent linear power supplies. In DC power distributions for FE, it is very important to keep the noise up to a level that does not compromise the operation of the FE and neighboring systems. Output filters into these converters are included to smooth the switched output voltage waveform to levels than can be tolerated by the FE. Input filters are needed to attenuate the switching input current waveform to prevent electromagnetic interference problems and to assure electromagnetic compatibility with neighboring systems. These input filters can also significantly affect the stability and performance of DC-DC converters.

Input filters can introduce instabilities in the system. DC-DC switching converters with tight output voltage regulation operate as constant power loads. In such cases, the instantaneous value of the input impedance is positive, but the incremental input impedance is negative. Due to the negative impedance characteristic of switching regulators, interaction between those units and other parts of the system may result in system instability.

Interference that is emitted by DC-DC converters can be either conducted or radiated. In general, interference covers a broad range of frequencies. Inputs and output filters consist of two distinct filter sections. The larger, lower frequency section is included to minimize the differential-mode noise (DMN) produced by the converter. The higher frequency section has a special topology to attenuate both differential and common-mode noise (CMN). The last component is due to currents flowing to ground through parasitic elements of the converter.

Commercial converters include part of these filters. Our goal is to include additional filtering to further reduce both common-mode and differential mode noise at the input and output of the converter. The most critical is the input filter because the primary requirements are: Sufficient attenuation of both DMN and CMN components, stability and good performance of the complete system and also minimum size and reliability.

To define the additional level of attenuation, DMN and CMN measurements of the input and output currents are necessary. The separation of noise components into CM and DM components simplify the filter design. The filter topology allows designing the elements that attenuate the CM noise almost independently of those elements that affect the DM noise components. Also this filter has influence at high frequency and its effect at low frequency can be ignored.

To assess stability and performance a model of the complete system is necessary. It includes not only all the DC-DC converters connected in parallel at the input but also the cable impedance and the output impedance of the primary AC/DC converter. Large-signal and small signal analysis is used to define the necessary damping to include into the input filter to satisfy the required performance.

CMS-ECAL collaboration

Corresponding author : Alessandro Bartoloni – INFN ROMA
I.N.F.N. Sezione di Roma
Ple Aldo Moro 2 - 00185 - Roma
( +39-0649913535/4423
cell. +39-347-3730183
Fax +39-06-4957697

This paper describes the power supply system that will be used to bias the Avalanche Photo Diodes (APD) used in the barrel part of the CMS Electromagnetic Calorimeter detector (ECAL).

Such part is composed by 61200 PbWO crystals each equipped with 2 APD that need a bias voltage in the order of 300 Volts with high stability and ultra low noise figures (40 mV peak-peak).

Such system, that will be located in the CMS control room 150 meters far from the APDs, is currently under development under the responsibility of the INFN-ROMA department.

Prototypes tests showing the system feasibility and reliability are also discussed in the following.

The barrel part of the CMS–ECAL detector is composed by 61200 PbWO2 crystals each equipped with 2 APDs developed for the CMS collaboration by the Hamamatsu corporation.

The APDs have to be reversed biased in the breakdown region at an operating gain (M) of 50 that will allow producing the necessary current value to be processed by the front-end electronics.

For this a bias voltage of about 300 Volts is required.

The stability of the voltage bias seen by the APD directly affects the ECAL resolution through the gain sensitivity, as a constant contribution to s(E)/E. The design goal for the constant term is 0.5%. Other expected contributions to the constant term (intercalibration, light collection uniformity, energy leakage) are estimated of the order of 0.2% or less each. To preserve the resolution, the contribution from the gain stability must be of the same order. As a consequence, considering a safety factor of 2, gain fluctuations due to the APD (and its bias supply) should be limited to the ± 0.1% (RMS) level.

A 3%/V (the typical dM/dV value for the selected APD at M=50) gain sensitivity means that ± 0.1% corresponds to ± 33 mV (66 mV p-p).

For the system specification all the system characteristics (Noise, Ripple, Stability, Regulation ) have then been fixed to 40 mV as maximum value.

Another issue of the system is its locations, because of the high radiation dose expected close to the detector (up to 1 MRad along with a neutron fluence of 2´ 10¹³ n/cm² over the entire life of the experiment) , the power supply system will sit in the control room connected to the detector by cables approximately 150 m long.

This approach leads to the choice of a modular power supply system organized in 144 High Voltage Boards (HVB) each containing 9 High Voltage Channels (HVC) used to supply 900 APDs (100 per channel).

The system will take care also of the variations of the APD leakage current (I_dark) due to the radiation. Measurements made on this subject allows to evaluate that the I_dark from a starting value of 10 nA will increase up to 20 µA during an LHC running time of 10 years.

A leakage current monitor integrated into the system will allows to measure continuously the surged current from 100 APD on each channel.

In order to understand the feasibility and the critical points of the final system, a series of test was performed using laboratory power supplies and some prototypes of the HVB and HVC produced by two different firms (CAEN and ISEG).

For such measurements some test-bed using APDs arrays, programmable electronic load and resistors boxes was built to create load condition similar to the detector.

At the moment laboratory qualification of the final system is going on, qualification on a real system using 400 crystals, 800 APDs and the relative front-end electronics (M0’ module) is scheduled for September 2001 in the H4 beam facility at CERN.

Design and Test of the Track-Sorter-Slave ASIC for the CMS Drift Tube Chambers

Authors
G.M.Dallavalle, A.Montanari, F.Odorici, R.Travaglini
INFN and University, Bologna, Italy

Oral presentation: F. Odorici (INFN Bologna)
Conference Topic: High Energy Physics Instrumentation
Fabrizio.Odorici@bo.infn.it

Abstract

Drift Tubes Chambers (DTCs) are used to detect muons in the CMS barrel. Several electronic devices installed on the DTCs will analyse data every bunch crossing, in order to produce a trigger decision. In particular, the Trigger Server system has to examine data from smaller sections of a DTC, in order to reduce the chamber trigger output by a factor of 25. The basic elements of the Trigger Server system are the Track-Sorter-Slave (TSS) units, implemented in a 0.5 micron CMOS ASIC. This paper describes the TSS ASIC, with emphasis on the methodology used for design verification with prototypes and IC simulation and test.

Summary

In the CMS muon barrel the Drift Tubes Chambers (DTCs) represent an important detector to produce a trigger decision. Several electronic devices installed on the DTCs will analyse data every bunch crossing, in particular the Trigger Server system has to examine data from smaller sections of a DTC.

The Trigger Server is implemented as a two-stage sorting system and has the task to complete the muon segments selection initiated by the previous DTC trigger stages. The basic elements of the Trigger Server system are the Track-Sorter-Slave (TSS) units, implemented in a 0.5 micron CMOS ASIC.

In the IC design particular effort has been devoted to speed optimization (event processing has to be completed within 25 ns), programmability and monitoring. Programmability allows to choose among different processing options, depending on the local trigger demands of each DTC section, and permits to partially cover for malfunctioning trigger channels. Since TSS units will be hosted onto the DT chambers and their access will not be easy nor frequent, much effort has been dedicated to redundancy of remote programming and monitoring logic. In particular, two independent access protocols, via serial JTAG and/or via an ad-hoc 8-bit parallel interface, allow programming and exhaustive monitoring of each device.

In order to master and verify the considerable design complexity, the TSS unit has been realized by following a joined approach between IC simulation and prototype testing phases. In both phases we adopted a common base of software tools, developed in order to provide an event generator, a device emulator and an output comparator. The hardware test tool was based on a programmable I/O Pattern Unit module, able to operate at the LHC bunch crossing frequency, that we designed as a general testing tool for digital electronic devices.