Evolution:
Bigger, faster, cheaper chips, better software.

Revolution:
Versatile I/O for 5 V, 3.3 V, 2.5 V and 1.8 V interfaces
Controlled-impedance I/O drives transmission lines, simplifies pc-boards
Versatile clock management eliminates delay, adjusts phase
Dedicated fast multipliers (>100 per chip)
PowerPC cores, up to 4 per chip
3.125 Bbps ( 2.5 Gbps data ) serial interface, clock recovery, 8B/10B,
20-bit FIFOs ( 10 Mbps in the future )

Convolution:
Using BlockRAM as state machines
Using multipliers as logic or arithmetic shifters
Using input flip-flops to count at 1 GHz
Using FPGAs with asynchronous clocks
Using triple redundancy to correct single-event upsets

Author:
Kerry Bernstein
STSM, IBM Server Technology
863K, 1000 River Rd, Essex Jct, VT 05452
(: (802)769-6897 HOME: (802) 899-2216
Fax: (802)769-6744 PAGE: (802) 769-1844 x 3946

kbernste@us.ibm.com

Entropy is a worthy adversary! High performance logic design in next-generation CMOS lithography must address an increasing array of challenges in order to deliver superior performance, power consumption, reliability and cost. Technology scaling is reaching fundamental quantum- mechanical boundaries! This talk will review example mechanisms which threaten deep submicron VLSI circuit design, such as tunneling, radiation- induced logic corruption, and on-chip delay variability. We will also examine architectures, circuit topologies, and device technologies under development which extend "evolutionary" concepts and introduce "revolutionary" paradigms. It will be these revolutionary technologies which will bring us to the threshold of human compute capability.

Joel Bovier
Director R&D
CES Creative Electronic Systems SA
70 route du Pont Butin
CH 1213 Petit Lancy, Switzerland
joel@ces.ch
((+41 22) 879 51 00

This paper describes the different aspects of modern board level electronic design with the consequences on the fabrication process. New technology packages such as BGA and FBGA implies the use of secure design techniques because the rework is very difficult. CES’s experience of the different steps will be covered : design for testability, EMI/RFI concern, signal integrity, in situ programming, new PCB layout techniques, JTAG testing strategy, and yield in production.