Abstract

Modular approach to development of Distributed Modular System Architecture for Detector Control, Data Acquisition and Trigger Data processing is proposed. Multilevel parallel-pipeline Model of Data Acquisition, Processing and Control is proposed and discussed. Multiprocessor Architecture with SCI-based Interconnections is proposed as good high-performance System for parallel-pipeline Data Processing. Tradition Network (Ethernet –100) can be used for Loading, Monitoring and Diagnostic purposes independent of basic Interconnections. The Modular cPCI –based Structures with High-speed Modular Interconnections are proposed for DAQ and Control Applications. Distributed Control RT-Systems. To construct the Effective (cost-performance) systems the same platform of Intel compatible processor board should be used.

Basic Computer Multiprocessor Nodes consist of high-power PC MB (Industrial Computer Systems), which interconnected by SCI modules and link to embedded microprocessor-based Sub-systems for Control Applications. Required number of Multiprocessor Nodes should be interconnected by SCI for Parallel-pipeline Data Processing in Real Time (according to the Multilevel Model) and link to RT-Systems for embedded Control/

Institute of Physics of Azerbaijan Republic Science Academy,

370143, Baku, Husseyn Javid Avenue, 33.

State Oil Academy of Azerbaijan Republic,

370010, Baku, Azadlig avenue, 20.

E. M. Kerimova, S.N. Mustafaeva, S.I. Mekhtieva, S.M. Bidzinova, N. Z. Gasanov, A. I. Gasanov

Institute of Physics,
Academy of Sciences of Azerbaijan,
G. Javid Prospect,
33,370143 Baku, Azerbaijan
E-mail:_Physics @_lan.ab.az

This paper deals with the investigation of optical properties of TlGaS₂, TlInS₂, TlGaSe₂ single crystals and influence of Fe and Cu doping and also intercalation by Li ions on these properties. The following main results have been obtained.

Intercalation of TlGaSe₂ single crystals by Li ions brings about the shift of energy position of exciton absorption peak, related with direct transition to long-wave side of spectrum. In particular at 5K this energy shift is D E=15 meV. As a result of intercalation the coefficient of temperature shift of this exciton peak decreased half as many in absolute value and is ¶ E^ex/¶ T within the range 20£ T£ 105 K and -0.25^.10^-4 eV/K at 5£ T£ 20 K.

Study of absorption spectra of TlM_1-xFe_xS₂ (M-In,Ga) single crystals in wide temperature range 5¸ 200K showed, that, in particular the width of bandgap of TlGa_1-xFe_xS₂ (x=0.001; 0.005; 0.01) crystals as of TlGaS₂ crystals increases with temperature rise. For TlGa_0.999Fe_0.001S₂ there have been observed exciton absorption band (hn =2.58eV at T=5K) which with temperature rise is broadened and shifted to side of higher energy. There have been also determined values of direct optical transition in TlIn_1-xFe_xS₂ (x=0.005; 0.01) single crystals at 5 and 300K.

Study of exciton absorption spectra of TlInS₂ single crystals doped by Cu showed that doping leads to the shift of energy position of exciton peak to long-wave region and it also increases exciton bond energy at the absorption edge: if for TlInS₂ =20meV, for Tl_0.995Cu_0.005InS₂ =31meV, for Tl_0.985Cu_0.015InS₂ =54meV. Bohr radius of exciton and its effective mass are calculated.

Thus, doping and intercalation of TlMC₂^VI leads to modification of their absorption spectra, change of exciton characteristics, i.e. allow optical properties to be controlled.

P. Moreira (1), T. Toifl (2), A. Kluge (1), G. Cervelli (1), F. Faccio (1), A. Marchioro (1) and J. Christiansen (1)

1. CERN-EP/MIC, Geneva, Switzerland
2. IBM Research, Zurich, Switzerland

Correspondin author:
Paulo Moreira, EP Division, CERN
Email: Paulo.Moreira@cern.ch

Gbit/s data transmission links will be used in several LHC detectors in trigger and data acquisition systems. In these experiments, the transmitters will be subject to high radiation doses over the experiment's lifetime. In this work, a radiation tolerant transmitter ASIC is presented. It supports two standard data transmission protocols, the G-Link and the Gbit-Ethernet, and sustains transmission of data at both 800 Mbit/s and 1.6 Gbit/s. The ASIC was implemented in a mainstream 0.25um CMOS technology employing radiation tolerant layout practices. A prototype was tested and its behavior under total dose irradiation as well as its susceptibility to single event upsets was studied. The experimental results are reported in the paper.

Several LHC detectors require high-speed (~ Gbit/s) digital optical links for transmission of data between the sub-detectors and the data acquisition systems. Typically, high-speed data transmission is required for both the trigger systems data path and the data readout systems. In general, those links will be unidirectional with the transmitters located inside the detectors and the receivers situated in the counting rooms. Due to the proximity to the collision point, the transmitters will be subject to high levels of radiation doses over the lifetime of the experiments. Additionally, the large numbers of high-speed optical links planned (of the order of 100K total for the four LHC experiments) impose strict constraints on device cost. Moreover, in trigger links, data has to be transmitted with constant latency and synchronously with the LHC 40.08 MHz reference clock - this to facilitate data alignment at the receiving end before the data is fed to the trigger processors. Although commercial optical links and components can be found that meet the bandwidth requirements of all of the LHC planned systems, those components generally have not been designed to withstand high levels of total dose irradiation. The few radiation-hardened devices, which exist on the market, have prohibitively high prices when the large number (~ 100K) of links required is taken into account. It was thus considered necessary to develop a dedicated solution that would meet the very special requirements of the High-Energy Physics (HEP) environment. Since only the transmitters will be subject to irradiation, only they need to be developed and qualified for radiation tolerance.

In this paper, a radiation tolerant ASIC developed for data transmission at both 800 Mbit/s and 1.6 Gbit/s is reported. The data format and encoding were chosen so that the transmitter can be operated with either a Gigabit Ethernet or a G-Link "commercial of the shelf" receiver. The IC was fabricated in a mainstream 0.25um CMOS technology using radiation tolerant layout practices. The paper will describe in detail the circuit architecture and its functionality. Emphasis will be given to the presentation of experimental results reporting on the robustness of the design against total dose irradiation effects and on the behavior of the device under ionizing radiation that gives origin to single event upsets (SEU). To assess the techniques used to improve the robustness against SEU phenomena, a performance comparison will be established with a previously developed 1.2Gbit/s serializer prototype.

S. Zimmermann, J. Andresen, J.A. Appel, G. Cardoso, D.C. Christian, B.K. Hall, J. Hoff, S.W. Kwan, A. Mekkaoui, R. Yarema.

Sergio Zimmermann
Fermi National Accelerator Laboratory
Computing Divison/Electronic Systems Engineering Dept.
P.O. Box 500
Batavia, IL 60510
USA
e-mail: zimmer@fnal.gov
( : (630) 840-4276
fax: (630) 840-8208

At Fermilab, a pixel detector multichip module is being developed for the BTeV experiment. The module is composed of three layers. The lowest layer is formed by the readout ICs. The back of the ICs are in thermal contact with the supporting structure while the other side is bump-bonded to the pixel sensor. A low mass flex-circuit interconnect is glued on the top of this assembly, and the readout IC pads wire-bounded to the flex circuit. This paper will present recent results on the development of a module prototype and summarize its performance characteristics.

At Fermilab, the BTeV experiment has been approved for the CZero interaction region of the Tevatron. The innermost detector for this experiment will be a pixel detector composed of 64 pixel planes of approximately 100 mm by 100 mm each, assembled perpendicular to the colliding beams and installed a few millimeters from the beams. Each plane is formed by sets of hybridized modules, each composed of a single active-area sensor and of one row of readout integrated circuits (ICs).

The pixel detector will be employed for on-line track finding for the lowest level trigger system and, therefore, the pixel readout ICs will have to transfer data for all detected hits. This requirement imposes a severe constraint on the design of the readout IC, hybridized module, and data transmission. Several factors affect the amount of data that each IC needs to transfer: readout array size, distance from the beam, number of bits of pulse height information, the data format, etc. Presently, the most likely dimension of the pixel chip array will be 128 rows by 22 columns.

The BTeV pixel detector module is based on a design relying on a hybrid approach. With this approach, the readout chip and the sensor array are developed separately and the detector is constructed by flip-chip mating the two together. This method offers maximum flexibility in the development process, choice of fabrication technologies, and the choice of sensor material. The module is composed of three layers. The lowest layer is formed by the readout ICs. The back of the ICs are in thermal contact with the supporting structure while the other side is bump-bonded to the pixel sensor. The low mass flex-circuit interconnect is glued on the top of this assembly and the readout IC pads wired-bounded to the flex-circuit. The module is remotely controlled by the pixel Data Combiner Board, located approximately 10 meters away from the detector. All the controls, clocks and data are transmitted between the pixel module and the data acquisition system by differential signals employing the LVDS standard. Common clocks and control signals are sent to each module and then bussed to each readout IC. All data signals are point to point connected to the Data Combiner Boards.

A prototype module using the FPIX1 IC has been characterized. However, differently from the proposed "sandwich" module, the flex-circuit of this prototype is located on the side of the ICs. Typical results include threshold of 1500 electrons, threshold dispersion of 280 electrons and noise of 60 electrons. The comparison of these results with the characterization results of a single FPIX1 IC board shows no observed degradation in performance. Furthermore, tests with dead-time-less mode, where the charge inject in the front end is time swept in relation to the readout clock also does not reveal any degradation in performance, suggesting no crosstalk problems between the digital and analog sections of the FPIX1 IC and the flex-circuit.

M. IMORI
( : +81 3 3815 8384
Fax: +81 3 3814 8806
E-mail: imori@icepp.s.u-tokyo.ac.jp

ICEPP
University of Tokyo
7-3-1 Hongo,
Bunkyo-ku,
Tokyo 113-0033, Japan

The article describes a network of high voltage power supplies which can work efficiently under a magnetic field of 1.5 tesla. The high voltage power supply incorporates a piezoelectric ceramic transformer. The power supply includes feedback to stabilize the high voltage output, supplying from 2000V to 4000V with a load of more than 20 megohm at efficiency higher than 50 percent. The high voltage power supply includes a Neuron chip, a programming device processing a variety of input and output capabilities. The chip can also communicate with other Neuron chips over a twisted-pair cable, which allows establishing a high voltage control network consisting of a number of power supplies each of which incorporates the chip individually. The chip sets the output high voltage. The chip detects the short circuit of the output high voltage and controls its recovery. The chip also monitors the output current. The functions of the power supply under the control of the chip are managed through the network. The high voltage power supplies are networked, being monitored and controlled through the network.

Network-Controlled High Voltage Power Supplies Operating in Magnetic Field High Voltage Power Supply The article describes a network of high voltage power supplies. The high voltage power supply includes feedback to stabilize the high voltage output, supplying from 2000V to 4000V with a load of more than 20 megohm at efficiency higher than 50 percent. The power supply incorporates a ceramic transformer. So the power supply can be operated efficiently under a magnetic field of 1.5 tesla. The power supply could be utilized in LHC experiments. The power supply includes an error amplifier and a voltage-controlled oscillator (VCO). The output voltage is fed to the error amplifier to be compared with a reference voltage. The output of the error amplifier is supplied to the VCO which generates the frequency of a carrier where the carrier drives the ceramic transformer. Voltage amplification of the transformer depends on the frequency of the carrier. So the feedback adjusts magnitude of the amplification by controlling the frequency.

Breakdown of Feedback

While the load of the power supply falls within an allowable range, the driving frequency is maintained higher than the resonance frequency of the transformer such that the feedback is negative as designed. The allowable range of load cannot cover, for example, short-circuiting the output high voltage to ground. When the load deviates beyond the allowable range, the driving frequency may decrease below the resonance frequency; a condition that will not provide the required negative feedback, i.e., positive feedback locks the circuit such that it is independent of load.

Network

The high voltage power supply includes a "Neuron" chip possessing a variety of input and output processing capabilities. The Neuron chip can communicates with other Neuron chips over a twisted-pair cable; a feature that allows establishing a network consisting of a number of power supplies that respectively incorporate the chip. Since most functions of the power supply is brought under the control of the chip, the power supplies are managed via the network.

Output High Voltage

The reference voltage is generated by a digital-to-analog converter controlled by the chip so that the output high voltage can be controlled by the network.

Recovery from Feedback Breakdown

The VCO voltage, being the output of the error amplifier, controls the driving frequency of the carrier. The feedback breakdown is produced by deviation of the VCO voltage from its normal range. The deviation is detected by voltage comparators, interrupting the Neuron chip. Once awakened, the chip reports the feedback breakdown and manages the power supply so as to recover from the breakdown.

Current Monitor

If both the output high voltage and the supply voltage are known beforehand, the frequency at which the transformer is driven depends on the magnitude of the load. The output current can be estimated from the driving frequency. The chip gets the driving frequency by counting pulses, which allows calculating the output current.

Agapito J. A.³, Cardeira F. M. ² , Casas J. ¹ , Fernandes A. P. ² , Franco F. J. ³ , Gomes P. ¹, Goncalves I. C. ² , Cachero A. H. ³ , Lozano J. ³, Marques J. G. ² , Paz A. ³, Ramalho A. J. G. ², Rodriguez Ruiz M. A. ¹ and Santos J. P. ³.

A study of several comercial instrumentation amplifiers (INA110, INA111, INA114, INA116, INA118 & INA121) under neutron and very low gamma radiation was done. Some parameters (Gain, CMRR, input offset voltage, input bias currents) were measured on-line and bandwith, slew rate and supply current were determined before and after radiation. Different digital-to-analog and analog-to-digital converters were tested under radiation . Finally, the results of the testing of some voltage reference and analog switchs will be shown.

Commercial instrumentation amplifiers have been tested: INA110 (fast settling time FET-Input amplifier), INA111 (High speed FET-input amplifier), INA114 & INA118 (bipolar instrumentation amplifier), INA116 (DiFET instrumentation amplifier) and INA121 (low power FET-Input instrumentation amplifier). Input offset voltage, input bias currents, differential gain and CMRR were measured under the irradiation once every 20 minutes during 5 days. After the irradiation, other parameters as slew rate, supply currents and bandwidth were measured.

It was observed that JFET-input, designed to have an excellent frecuency response, exhibit the best behaviour. On the other hand, the worst is a DiFET amplifier because its destruction happened quickly. This is a great surprise because, in early papers, it was found that the best operational amplifiers under neutron radiation were built in this technology. Most of other amplifiers were destroyed during the irradiation.

It was observed a growth of the input offset voltage and the bias currents. Differential gain remains constant upto a value of radiation wich depends on the different amplifiers. CMRR behaves in a similar way. In all the amplifiers that survived, the supply currents decrease and the frecuency response is degradated. The value of slew rate and bandwidth is lower and output signal is very distorted in the more irradiated amplifiers.

In MX7541 digital-to-analog converter a great increase of output current offset and integral non-linearity error were observed but gain error keeps constant until a total dose (3-5·10¹² cm^-2, 150 Gy) which destroy the converter. In this moment, a reduction of the number of output voltage levels was observed. Before the destruction, this number was reduced to 16, 8, 4 and none. The converter did not come back to work after the annealing. It is possible that the converter destruction was due to the vestigial gamma dose because an alike converter, AD7541 from Analog Devices, is reported to be destroyed at similar levels of gamma dose.

The study of the parameters of ADS1210 analog-to-digital converter has been carried out.

The resistance and the leakage current of DG412 analog switches were also measured. It was observed a high increase of the switch resistances. The initial value was 20-30 ohms but the last values obtained before the destruction was 80-100 ohms. It was observed an increase of the leakage current (absent in the beginning, it can reach 1 mA). The aparition of this current is due to the action of gamma rays that form charges inside the oxide of the MOSFET transistors and the oxide that covers the semiconductor. However, the growth of resistance value is due to the neutron radiation.

With respect to REF102 voltage reference, it was observed an increase of line regulation and, also, the lowest voltage needed to obtain the nominal output voltage moved from 12 volts to 16-20 volts.

Because of increasing clock frequencies, faster rise times and wider busses, printed circuit board (PCB) design layout becomes an issue. The Cadence® SPECCTRAQuest™ SI (signal integrity) package allows the pre- and post-layout signal integrity analysis of a PCB designed in the Cadence flow under Allegro. Case studies of work done for some LHC detectors will be presented. These will show how the tools can help Engineers in design choice, optimizing electrical performance of board layout, to reduce prototype iterations and to improve production robustness. Examples will include work done on PCI 66MHz and GTL busses.

P.K.Skorobogatov, A.Y.Nikiforov

Specialized Electronic Systems,
Kashirskoe shosse, 31,
115409, Moscow,
Russia pkskor@spels.ru

Temperature dependence of p-n junction radiation-induced charge collection under 1.06 and 0.53 micrometer focused laser beams was investigated in the temperature range from 22 to 110 C using experiments and numerical simulation. It was shown that in the case of 0.53 micrometer laser irradiation the temperature practically does not affect the collected charge. In the case of 1.06 micrometer laser irradiation the theory and experiments have shown the essential growth (from 2 to 3 times) of collected charge with temperature. The result obtained must be taken into account in device SEE selection for LHC electronic.

The high radiation environment of the LHC experiments requires the electronics to withstand single event effects (SEE). The procedure for estimating of integrated circuits SEE vulnerability based on particle accelerators testing is very expensive.

The focused laser sources may be used for SEE investigation and estimation [1,2]. Laser simulation of SEE is based on the focused laser beam capability to induce local ionization of IC structures. A wide range of particle linear energy transfer (LET) and penetration depths may be simulated varying the laser beam spot diameter and wavelength. The temperature dependence of the laser absorption coefficient in semiconductor affects the equivalent LET and must be accounted for when devices are tested at temperature range [3].

In order to estimate the influence of temperature on SEE laser testing parameters we have analyzed the temperature dependence of charge collected by test structure p-n junction. The experiments were performed using the original "PICO-2E" pulsed solid-state laser simulator in basic (1.06 micrometer) and frequency-double (0.53 micrometer) modes with laser spot diameter of 5 micrometers. The numerical simulations were performed using the original "DIODE-2D" 2D software simulator.

The investigated test structure was manufactured in a conventional 2 micrometer bulk CMOS process and includes well-substrate p-n junction. The measurements of p-n junction collected charge were performed in the temperature range from 22 to 110 ?C for two laser beam spot positions: within the n-well and out of junction area. It was shown that in the case of 0.53 micrometer laser irradiation the temperature practically does not affect the collected charge because of slight laser absorption coefficient temperature dependence in this range. The theoretically predicted variations of collected charge do not exceed 10% and may be explained by carrier lifetime and mobility temperature dependences. In the case of 1.06 micrometer laser irradiation the theory and experiment have shown the essential growth of collected charge with temperature. It is corresponds with strong laser absorption coefficient temperature dependence for photon energy near the bandgap. The theoretical prediction gives the approximately doubling of collected charge in the range from 22 to 110 C. The experimental results show that SEE sensitivity increases at least three times in this temperature range. The difference between measured and simulated results may be explained by uncertainties of laser absorption coefficient temperature dependence near the edge of silicon fundamental band-to-band absorption zone. The results obtained prove that the temperature dependence of the laser absorption coefficient in semiconductor affects the equivalent LET and must be taken into account in device SEE selection for LHC electronic.

P.K.Skorobogatov, A.S.Artamonov, B.A.Ahabaev

Specialized Electronic Systems, Kashirskoe shosse, 31, 115409, Moscow,
Russia pkskor@spels.ru

The dependence of p-i-n diode ionizing current amplitude vs 1.06 micrometer pulsed laser irradiation intensity is investigated. It is shown that analyzed dependence becomes nonlinear beginning with relatively low laser intensities near 10 W/cm2. This effect is connected with the modulation of pi-n diode intrinsic region by laser irradiation. As a result the distribution of electric field becomes non-uniform that leads to decrease of excess carriers collection. The ionizing current pulse form becomes more prolonged and does not repeat the laser pulse waveform. It is necessary to take into account when p-i-n diode is used as a laser intensity dosimeter.

Pulsed laser sources are widely used for dose rate effects simulation in IC's. The Nd:YAG laser with 1.06 micrometer wavelength is near ideal for silicon devices, with a penetration depth near 700 micrometers. The measurements of pulsed laser irradiation intensity and waveform monitoring may be provided with p-i-n diode. High electric field in its intrinsic region provides the full and fast excess carriers collection. As a result the ionizing current pulse waveform repeats the laser pulse within the accuracy of several nanoseconds.

Possible nonlinear ionization effects may disturb the behavior of p-i-n diode at high laser intensities. To investigate the p-i-n diode possibilities at high laser intensities the original software simulator "DIODE-2D" and the pulsed laser simulator with 1.06 micrometer wavelength were used. The typical p-i-n diode with 380 micrometers intrinsic region width under 300 V reverse bias was investigated. The simulation of p-i-n diode structure have shown that linear dependence between laser intensity and ionizing current is valid only at relatively low intensities up to 10 W/cm2 under 11 ns laser pulse irradiation. The ionization distribution nonuniformity connected with laser radiation attenuation does not affect the dependence because of relatively low excess carrier density to sufficiently change the absorption coefficient. In the field of high laser intensities this dependence becomes non-linear and ionizing current increases more slowly than laser intensity. The numerical results were confirmed by experimental measurement of pi-n diode ionizing reaction in a wide range of laser intensities. The pulsed laser simulator "RADON-5E" with 1.06 micrometer wavelength and 11 ns pulse width was used in the experiments as a radiation source [1]. The laser pulse maximum intensity was varied from 0.3 up to 2ú103 W/cm2 with laser spot size covering the entire chip. It provides in silicon the equivalent dose rates up to 109rad(Si)/s

As in the case of gamma irradiation [2], the reason of non-linearity is connected with the modulation of p-i-n diode intrinsic region by excess carriers. Because of low level of initial carriers concentration the modulation takes place at relatively low laser intensities.

As a result of modulation the distribution of electric field in the intrinsic region becomes non-uniform that leads to decrease of excess carriers collection. The behavior of p-i-n diode becomes similar to that of ordinary p-n junction with prompt and delayed components of ionizing current. The prompt component repeats the dose rate waveform. The delayed component is connected with the excess carriers collection from regions with low electric fields. As a result the ionizing current pulse form becomes more prolonged and dose not repeat the laser pulse waveform. The non-linear character of behavior and prolonged reaction must be taken into account when p-i-n diode is used as a laser intensity dosimeter in LHC experiment.

Radiation tolerance studies of BTeV pixel readout chip prototypes

Gabriele_Chiodini
chiodini@fnal.gov
Particle Physics Division,
Fermi National Accelerator Laboratory
P.O. Box 500Z
Batavia, IL 60510
(: (630) 840-5151
Fax: (630) 840-3867
chiodini@fnal.gov

We report on several irradiation studies performed on BTeV pixel readout chip prototypes exposed to a 200 MeV proton beam at Indiana University Cyclotron Facility. The pixel readout chip preFPIX2 has been developed at Fermilab for collider experiments and implemented in standard 0.25 um CMOS technology following radiation tolerant design rules. The tests confirmed the radiation tolerance of the chip design to proton total dose up to 14 MRad. In addition, non destructive radiation-induced single event upsets have been observed in on-chip static registers and the single bit upset cross section has been measured. We also show irradiation test results that we are planning to do on June-July 2001, where preFPIX2 readout chips bump-bonded to pixel sensors will be exposed to high dose.

The BTeV experiment is planned to run at the Tevatron collider in ~2006. It is design to cover the ``forward'' region of the p-antip interaction point at the expected luminosity of 2E32/s/cm**2$. The experiment will employ a silicon pixel vertex detector to provide high precision space points for on-line lowest level trigger impact parameter finding. The ``hottest'' chip, located at 6 mm from the beam, will experience a fluence of ~ 1E14/cm**2/y.

This correspond to the highest radiation enviroments at ATLAS and CMS at LHC. A pixel detector readout chip (FPIX) has been developed at Fermilab to meet the requirement of Tevatron collider experiments. The preFPIX2 reppresents the most advanced iteration of very succesfull chip prototypes and has been realized in standard deep-submicron CMOS technology from two vendors. As demostrated by the RD49 collaboration at CERN, the above process can be made very radiation tolerant following specific design rules.

We show results of radiation tests performed this year with preFPIX2 chip prototypes including both total dose and single event effects. The tests have been performed by exposing the chip to 200 MeV protons (at the Indiana University Cyclotron Facility). The comparison of the chip performace before and after exposure shows the high radiation tolerance of the design to hadrons up to ~ 14 Mrad total dose. Last year exposures to radiation from a Colbalt-60 source at Argonne National Lab already verified the high radiation tolerance to gamma radiation up to ~ 30 Mrad total dose. Total dose effects are not the only concern for reliable operation of the detector. Ionizing radiation can induce single event upset (SEU) effects, as unwanted logic state transition in a digital device, corrupting stored data. The single event upsets just described do not permanently alter the chip behavior, but they could result in data losses, shifts of the nominal operating conditions, and loss of the chip control. If the single event upset rate is particularly high it could be significantly mitigated by circuit hardering techniques. Instead, if it is not, it could be tollerated simply by a slow periodic downloading of potentially corrupted data or full system resetting in the worse case. During the irradiation tests, we observed single event upsets in the preFPIX2 registers and measured the rate. The measurements consisted of detecting bit error rates in the static registers controlling the readout chip front-end operating conditions and the pixel cell respons. The single bit upset cross section measured for the digital-analog-converter registers located on the chip periphery was sigma = 3.8(+/-1.2 +/- 0.2)E-16cm**2, while for the mask and charge-injection registers located inside each pixel cell was sigma = 2.0(+/-0.3+/-0.1)E-16cm**2 (where the first error is statistical and the second systematic due to uncertainty in the beam fluence). The implications of the estimated SEU rate in the BTeV pixel vertex detector are discussed. We would like also to report results from irradiation tests planned for June-July 2001 with single chip sensor bump-bonded to a readout chip. In these future test, the primary goals are to increase the statistics of single event upsets and compare the front-end performance before and after irradiation of the assembly sensor-readout chip.

Selcuk Cihangir
Fermilab
Particle Physics Division
selcuk@fnal.gov

W.L. Simon Kwan

swalk@fnal.gov

Pixel detectors proposed for the new generation of hadron collider experiments will use either indium or Pb/Sn solder bump-bonding technology. We have carried out a study of long term effects of both types of bump bonds using daisy-chained silicon on silicon parts. We also studied the effect of thermal cycles. Some of the parts were then exposed to intense radiation using a gamma source and the integrity of the bumps were studied afterwards.

Pixel detectors propsoed for the new generation of hadron collider experiments will use flip-chip mating technology based on either indium or solder bumps to connect the sensors to the readout chips. Last year, we reported a large scale tests of the yield using both technologies. The conclusion is that both seem to be viable for pixel detectors. We have recently carried out a study of long term effects of both types of bump bonds using daisy-chained parts. We also studied the effect of thermal cycles by heating the parts to 100 C for 2 days and cooling them down to -15 C for up to a week. Some of the parts were then exposed to intense radiation using a gamma source and the integrity of the bumps was studied afterwards.

In indium bump bonds, we observed in some channels a substantial increase in resistance along with occurance of capacitance of 50 - 300 pf. All three processes, namely long term storage, heating and cooling, caused this effect. We will quote rates for this effect.

In solder bump bonds, the effect was the breakage of the bonds at some channels. Some of these breakages may have had occured at the UBM (Under Bump Metalization) level. All three processes caused breakage of the bonds. We will quote rates for their occurances at the UBM level and otherwise. Among the three processes, cooling was the least problematic. For some channels, the heating process helped to improve the connectivity.

Z. Dolezal(corresp. author)(1), J. Broz(1), T. Cechak(2), D. Chren(2), T. Horazdovsky(2), J.Kluson(2), C. Leroy(3), S. Pospisil(2), B. Sopko(2) and I. Wilhelm(1)

(1) Charles University, Prague
(2) Czech Technical University, Prague
(3) Montreal University

dolezal@ipnp.troja.mff.cuni.cz

A direct study of neutron induced Single Event Effects (SEE) has been performed in Prague using collimated and monoenergetic neutron beams available on the Charles University Van de Graaff accelerator. For that, silicon diodes and LHC Voltage Regulator were irradiated by neutrons of different energies (60 keV, 3.8 MeV, 15 MeV). Furthermore, the associated particle method was used, in which 15 MeV neutrons produced in the 3H(d,n)4He reaction were tagged. The measurements allowed to estimate a probability of neutron interactions per sensitive volume of the junction and an upper level of SEE occurrence in the LHC Voltage regulator chip.

CMOS integrated circuits (CMOSICs) are largely used in space, aviation and particle accelerator environments, i.e. at high radiation environments. The use of submicron CMOS processes in these adverse radiation environments requires the application of special architectural and layout techniques. Failures could come not only from total dose effects but also from so-called Single Event Effects (SEE) believed to be responsible for latchup that can destroy ICs completely or render them unusable indefinitely or for various periods of time. Therefore, there is a need to understand the importance of SEE in specific operational environments and to find ways of quatifying the tolerance of the different technologies to these effects. We tried to find out whether neutrons could cause latchup phenomena in CMOSICs.

The occurrence of SEE can be provoked by specific interactions of the neutrons with the silicon chip ((n, alpha), (n,p), (n,n') etc... reactions). In this work, neutron induced SEE were studied directly on silicon diodes as well as on silicon chips.

Several steps have been fulfilled to achieve that goal. At first, the experimental set-up of a collimated, monochromatic and tagged neutron beam has been realised at the van de Graaff accelerator of Charles University, in the collaboration with Montreal University and Czech Technical University, Prague. Neutron beam energies of 60 keV (with an energy spread 10 keV), 3.8 MeV (100 keV) and 15 MeV (100 keV) are available through the reactions 3H(p,n)3He, 2H(d,n)3He and 3H(d,n)4He, respectively. Secondly, tests of the neutron beams quality have been performed including collimation, measurement of energy spread, and monitoring of the flux of neutrons. Finally, the associated particle method for the direct study of SEE, using the 3H(d,n)4He reaction, was developed and tested. The achievement of these steps provide a neutron beam energy range allowing one to recognise the expected energy threshold behaviour of SEE and at the same time to observe the history of each tagged neutron (known with an accuracy of 10 ns) in a collimated beam.

Two types of devices under test (DUT) have been tested. First silicon diodes of different sizes were put to the neutron beam and their response was studied. Levels of hits and pulse height distributions have been recorded for different neutron energies and fluences. The second step consists in the observation of the history of each neutron in a collimated neutron beam generated in 3H(d,n)4He reaction and the registration of a diode hits (pulses) correlated with a neutron of known history by the coincidence unit as simple and as fast as possible. These measurements allowed to estimate a probability of the reaction per sensitive volume of the junction and an amount of energy of reaction products deposited in this volume.

The same measurements were carried out with LHC Voltage Regulator (RD49 project). Here, only the upper limits of SEE for various neutron energies were established, as the measurements continue with the goal of achieving sufficient statistics to determine SEE probabilities.

H. Chen, F. Lanni, M.A.L. Leite, S. Rescia and H. Takai
Brookhaven National Laboratory - Physics Department
Upton, NY - 11973 - USA

An optically coupled charge injection system for ionization based radiation detectors which allows a test charge to be injected without the creation of ground loops has been developed. An ionization like signal from an external source is brought into the detector through an optical fiber and injected into the detector electrodes by means of a photodiode.

For the performance tests of ionization based radiation detectors it is desirable to have a system which is capable of injecting a charge of known value in a condition that is as close as possible to the operating environment, where charge is locally generated by the ionization of the sensitive media in the detector. One of the main problems with the conventional approach of the direct injection through an electrical cable connected to the detector electrodes is the change of the detector electrical characteristics. In particular, the grounding configuration of the system can be completely modified by the introduction of the injection circuit new ground path. The use of an optically coupled injection, in which a light to current converter is placed on the electrodes of the detector to generate the ionization signal, allows for a full galvanic isolation between the detector and the test pulser. A photodiode installed on the electrodes and biased by means of the high voltage system achieves the light to current conversion. It has a capacitance of only a few pf, small if compared with detector capacitances of the order of nF. The photodiode should also have a fast time response and low dark current. Size is also an issue, as this device may needs to fit in spaces of only a few millimeters. The light, generated by a laser diode stimulated to produce a suitable signal for the detector, is brought to the photodiode using a multimode optical fiber.

As an example of this method, the ATLAS Electromagnetic Liquid Argon Calorimeter test stand at BNL has been modified by adding photodiodes on several electrodes. The optical signal is created using a light pulse generator whose output is modulated to produce the same triangular shaped pulse generated by an ionization signal. Crosstalk studies can also be performed by injecting one electrode and recording the crosstalk pattern on neighbor channels. Results of measurements showing how the detector-readout system can be characterized based on the analysis of the signal shape and how the crosstalk at several system levels can be evaluated in this particular case will be presented.

Commissioning results of the First Level Trigger in HERA-B during 2000

Imma RIU
Riu@mail.desy.de

Abstract

During year 2000, the First Level Trigger was installed, operated and commissioned in HERA-B. This paper describes the pattern recognition algorithm, its implementation in electronics and the commissioning results.

The basic task is to accept events with lepton pairs that originate from the decay of the J/psi meson. With a latency smaller than 10 microseconds, the First Level Trigger has to process about 100,000 channels of detector data that are readout every 96 ns. Using a kalman filter technique, the First Level Trigger searches for tracks produced in the detector through up to seven layers.

Summary

The basic task of the HERA-B First Level Trigger is to accept events

with lepton pairs that originate from the decay of a J/psi meson. In order to filter these events out of the immense data stream produced out of the 920 GeV proton nucleon interactions at 10 MHz in HERA-B, a very fast trigger had to be developed. A rate reduction to 50 kHz is required due to the bandwidth of the Second Level Trigger. It explores the full detector granularity and is able to reconstruct tracks from 5 to 200 GeV momentum.

The First Level Trigger receives pretriggers from the electromagnetic calorimeter and the muon detector systems that point to the location of possible electron or muon candidates in the event. Being Kalman filter inspired, the First Level Trigger starts from these points and tries to find a track through a sequence of tracking chambers (up to seven) towards the target. The filter process is implemented in hardware processors (so-called TFUs), each assigned to a certain section of a given tracking chamber. They sit on memory boards containing all relevant hit data of their chamber section and communicate the results of the filter step by short messages containing the current track information. In order to simplify the filter logic, it is assumed that the tracking chambers used in the First Level Trigger are 100% efficient. For that reason, all layers participating in the First Level Trigger are double layers. The last processor in the filter communicates the position and direction of a found lepton track to a specialized processor (so-called TPU), which determines the primary momentum vector of the lepton and applies some cuts on the momentum and transverse momentum of the track. A final processor (so-called TDU) issues the trigger after applying some cut on the invariant mass between the accepted leptons, or on number of tracks.

These processors are based on massive use of EPLDs and Look Up Tables and are the core of the system. Approximately 100 of them operate fully pipelined and in parallel. The processors are interconnected with 2 Gbit/s links to communicate the results. The detector data arrive to the processors through about thousand 500 Mbit/s optical fibers. All these processors are housed in nine VME crates which are controlled by Power PC computers.

The complete First Level Trigger system has been set up during year 2000 and an intense commissioning and debugging phase has taken place. It can be shown that it finds tracks and its performance is mainly driven by the performance of the different detectors. This is the first time a dead timeless trigger system has been successfully

used to reconstruct tracks in events at a very high rate of 10^7 events per second. Since the trigger technologies planned for the LHC experiments are similar to our system, these results can provide a proof of principle for the LHC trigger designs