R. Kluit, P. Timmer, J.D. Schipper, V. Gromov; NIKHEF Amsterdam

r.kluit@nikhef.nl
A.P. de Haas; NIKHEF Utrecht

The design of the control electronics of the front-end of the ALICE SSD is described. This front-end is build with the HAL25 (LEPSI) chip. The controls are placed in the ladder EndCap. The main EndCap functions are power regulation and latch-up protection for the front-end, control functions for the local JTAG bus, distribution of incoming control signals for the front-end and buffering of the outgoing analog detector data. The system uses AC-coupled signal transfer for double-sided detector readout electronics.
Due to radiation-, power-, and space requirements, two ASIC’s are under development, one for analog buffering and one with all other functions combined.

The ALICE ITS is build out of three layers, Pixel-, Silicon Drift- and Silicon Strip Detectors. For the SSD the development of the control-electronics inside the detector volume will be described.

The SSD is based on Double Sided Silicon Strip Detectors with 768 strips at each side. The detectors will be readout by the HAL25 (Hardened Alice128 in .25u CMOS) front-end chip developed by LEPSI Strasbourg.

The SSD consists of 2 layers of ladders, the inner with 34 and the outer with 38 ladders. The inner ladders contain 23 modules and the outer 26. The detector modules will be connected to the DAQ- & Control system via EndCap units mounted at the end of each side of the ladder. The available space is ~ 70x70x45 mm.

Since ALICE is a heavy-ion experiment the electronics must be susceptible for Single Event Effects (SEE). Total dose is not a big issue although levels up to ~50krad may not cause any degradation. Therefore the front-end chip and the electronics in the EndCap must be protected for latch-up and are now build in radiation tolerant technologies. The limited available space and the temperature constraints of the detectors (and environment) require a low power design.

Due to the use of double-sided detectors, the readout electronics on both sides operate at different potentials. To avoid ADC and control modules to operate at these bias potentials, all signals will be AC coupled to the corresponding voltage level. Also the analogue readout data will be AC coupled to a multiplexer/buffer, which is able to drive the differential signal to ADC modules (over 10m @ 10MHz). The front-end chips of the detector modules are readout in series, both the P- and N side of each detector module to one ADC channel.

The Low Voltage power for the front-end (2.5V) for the two bias levels is regulated inside the EndCap. This circuit not only provides the latch-up protection for the front-end but also for the control electronics and buffers in the EndCap itself.

The Front-end electronics is controlled via the JTAG bus and it is also used to monitor and control the EndCap functions. Errors like latch-up can be monitored and appropriate action can now be taken. Disabled front-end chips can be put in "by-pass" mode and this information is available for the DAQ system.

All previously mentioned functions of the EndCap will be integrated in two ASIC’s, one analog multiplexer/buffer (ALABUF) and one multipurpose control chip (ALCAPONE). This development is done using a commercial technology (0.25u CMOS) with radiation tolerant design techniques.

The multipurpose control chip houses a Bandgap reference (CERN), Regulator circuit with DAC (ALICE PIXEL or LEPSI), JTAG control, LVDS and CMOS buffers for AC coupling, ADC for monitoring and digital control functions for the front-end. Simulations of the analogue functions show good feasibility for use in the EndCap, tests after irradiation should clarify if this approach gives a satisfactory result for the EndCap design.

The regulator and the analog multiplexer/buffer circuits have been submitted to a MPW test run and test results will be compared with simulated data and discussed.

Antinori, F.(1,2), Ban, J.(3), BURNS, M.(1), Campbell, M.(1), CHOCHULA, P.(1, 4), Formenti, F.(1), Kluge, A.(1), Meddi, F.(1, 7), Morel, M.(1), Petra, Rober to, Snoeys, W.(1), Stefanini, G.(1), Wyllie K.(1).

(For the ALICE Collaboration)

Described is a system that has been developed for testing the ALICE Silicon Pixel Detector Readout Chip. It is capable of covering all aspects of testing, from the selection of know good dies on a wafer, characterisation, and as a DAQ when performing beam tests Considerable effort has been invested in the software to provide a comprehensive suit of facilities and test routines to enable the complete testing and characterisation of the device. In this paper we would like to present the objectives and requirements of the test system, a description of the hardware, software and database and present some of the results obtained.

The previous test system for the pre prototype ALICE1LHC Pixel detector Readout Chip was built using both CAMAC and VME components employing a standard processor that was sited in the VME crate. The system evolved continuously to increase the system functionality and automate the measurement process. This resulted in a bulky test system which was difficult to transport and almost impossible to reproduce. The results of the measurements were stored on the VME system local disk for treatment at a later date by another computer system. The new system has taken the analogue functionality of the CAMAC modules and integrated them into the circuitry contained on the Adapter Board. The VME crate had been kept and houses the modules required in the DAQ chain. A PC running LabView software has been selected as the system controller. The PC is interfaced to the VME system using the MXI bus connection from National Instruments The Adapter Board is controlled using a 4-wire JTAG connection from an interface which may be installed in either the PC or the VME crate. All test parameters may be varied interactively to enable detailed verification of the various subsections of the Pixel Chip or routines can be executed to automatically perform detailed measurements of the devices. Acquired data is treated and displayed via a graphical user interface exploiting the capabilities of LabView to rapidly present the results. The results may then archived for further reference when either assembling the Pixel Detector or by the ALICE online database.

The system requires approximately xx minutes to characterise a device and yy m inutes to test a whole wafer automatically.

The HAL25 is a mixed low noise, low power consumption and radtol ASIC intended for read-out of Silicon Strip Detectors (SSD) in the ALICE tracker. It is designed in a 0.25 micron CMOS process and is similar in concept to the previous chip ALICE128C. The chip contains 128 channels of preamplifier, shaper and a capacitor to store the charge collected on a detector strip. The analogue data is held by an external logic signal and can be serially read out through an analogue multiplexer. A slow control mechanism based on JTAG protocol was implemented for a programmable bias generator, an internal calibration system and selection of functional modes.

The HAL25 chip is a mixed analogue-digital ASIC designed for read-out of Silicon Strip Detectors (SSD) in the ALICE tracker. It is based on the ALICE first generation chip ALICE128C which was tested with good performance for an irradiation up to 50 krad. ALICE128C is now used in the SSD frontend electronic of the STAR tracker.

For the ALICE experiment, a new radiation hardened circuit design was required to meet the total dose radiation and latchup background. It has been demonstrated that commercial deep submicron CMOS technologies exhibit intrinsic radiation tolerance. HAL25 has been designed with special design technics in a 0.25 micron CMOS process which is expected to meet the demands of low noise, low power consumption and radiation hardness required by the ALICE experiment.

HAL25 contains 128 channels of preamplifier, shaper and a capacitor to store the charge collected on a detector strip. The data is held by an external logic signal and can be serially read out through an analogue multiplexer at 10 MHz.The chip is programmable by the JTAG protocol which allows:

- to set up an adjustable bias generator which tunes the performances of analogue chains;
- to choose the internal calibration system which sends a calibrated pulse to the inputs of selected chains;
- to perform boundary scan.

For the SSD layers, the ALICE experiment needs a readout circuit having very large dynamic range (+/-15 Mips) with good linearity and an adjustable shaping time from 1.4 us to 2.0 us. This is a challenge for such a circuit designed in a deep submicron process operated at only 2.5 V which is the edge of the use of standard analog design techniques.

This paper will explain how the required specifications have been met:

- single power supply;
- low noise;
- low power consumption (mean power consumption of designed circuit for a readout cycle of 1 ms is around 300 uW/ch);
- large dynamic input range (+/-15 Mips) with good linearity;
- differential current output to improve EMC;
- geometry adapted to Tape Automated Bonding.

The authors also expect to present evaluations of the circuit which was submitted to foundry at the end of March.

Authors :
G.Mazza [INFNTo], M.Idzik[INFNTo], A.Rivetti[UniTo], F.Rotondo[INFNTo]

Institutes :
INFN sezione di Torino, Italy
Universita` di Torino, Italy

G.Mazza
Lab. di Elettronica, Sez. Torino
Via P. Giuria 1
10125 Torino - Italy
( +39 011-6707380
Fax +39 011-6699579
E-mail mazza@to.infn.it

New building blocks have been developed for the electronic readout of the ALICE Silicon Drift Detector. Those blocks include a 10 bit A/D converter with a reduced input capacitance, an 8 bit D/A converter based on the current mirror scheme, a voltage regulator and biasing schemes.
The blocks will be used in the PASCAL chip to improve the performances of the existing prototype and will be the building blocks for the SDD Detector Control System ASIC.
The circuits have been developed in a commercial CMOS 0.25 um technology using radiation tolerant layout techniques.

The front-end prototypes for the electronic readout of the ALICE experiment Silicon Drift Detector have been designed and succesfully tested. Nevertheless, a number of system requirements as minimize dead time, avoid external biasing and develop the Detector Control System have to be addressed. At this purpose, new building blocks have been developed. These blocks include a 10 bit A/D converter, an 8 bit D/A converter based on the current mirror scheme, a voltage regulator and biasing schemes. The A/D converter is based on the successive approximation principle. In order to reduce the input capacitance, the internal DAC has been splitted into a 5 bit main DAC and a 5 bit sub DAC. This arrangement makes possible to reduce the input capacitance of a factor of 8 compared to the previous version. The D/A converter is based on a matrix of 256 current mirrors. This technique relaxes the matching requirements and therefore improves DNL and INL. A transimpedance amplifier has been designed in order to convert the output current into a voltage. The voltage regulator and bias circuits will be integrated in the final front-end ASIC ( named PASCAL ) in order to have no external analog signals in the front-end board. Those components will be also the building blocks for the Detector Control System ASIC which will be located on both ends of the SDD ladder. The circuits have been developed in a commercial CMOS 0.25 um technology using radiation tolerant layout techniques.

Leonid Efimov Efimov@sunhe.jinr.ru [1],
Vito Lenti Vito.Lenti@cern.ch [2]
Orlando Villalobos-Baillie orlandov@mail.cern.ch [3]

for the ALICE Collaboration

Abstract

The design details and test results of a prototype Mutiplicity Discriminator (MD) for the ALICE L0 Trigger electronics are presented. The MD design is aimed at the earliest trigger decision founded on a fast multiplicity signal cut, in both options for the ALICE centrality detector: Micro Channel Plates or Cherenkov counters. The MD accepts detector signals with an amplitude range of plus-minus 2.5 V, base duration of 1.8 ns and rise time of 300-400 ps. The digitally controlled threshold settings give an accuracy better than 0.4% at the maximum amplitude of the accepted pulses. The MD internal latency of 15 ns allows for a decision every LHC bunch crossing period, even for the 40 MHz of p-p collisions.

A functional scheme and other considerations for the Prototype Multiplicity Discriminator (MD), as an element of ALICE L0 Trigger Front-End Electronics (FEE), are given for the proposed MCP-based detector option. The MD has to produce a Pre-Trigger on Multiplicity by cut of a fast linear sum of 8 signals from pads belonging to an MCP disc sector. This is foreseen within every FEE card according to programmable threshold codes delivered by a Source Interface Unit through the ALICE Detector Data Link. The prototype MD schematics and implementation are described in details around a functional scheme and a schematic view of the input analog section. The approach used in the design was to implement a leading edge discriminator by a proper combination of an ultra-fast voltage comparators and a digital-to-analog converter (DAC) from Analog Devices. The shaper, built on components of Motorola MECL 10KH logic series, provides the output signal with a correct form, duration and 16 mA for 50 Ohm load. The prototype MD board is mounted in a double-width NIM module to support conventional test facilities.   The correlation between MD preset and real (effective) thresholds has been studied in order to evaluate the MD sensitivity to very fast and low-amplitude detector signals. Some results of such measurements, using a fast programmable  pulse generator, are shown as the effective voltage threshold versus the DAC threshold values. Next calculation of the equivalent electric charge, carried by these pulses, gave the rough estimates of the MD sensitivity as a minimum of over DAC threshold pulse charge needed to trigger the scheme. An estimate of a Prototype MD input capacity was obtained also. The first experimental test of the prototype MD was performed at CERN PS/T10 area with muon beams of 7.5 GeV/c.
The aim of this experiment was two fold:
a) to test the timing properties of the prototype MD;
b) to simulate a study of multiplicity/centrality versus the MD threshold.
Results from the MD, used instead of a specialized fast timing discriminator for time-of-flight measurements, are presented with a distribution of events versus the time-to-digital converter channels. A resolution of about 120 ps should be taken as a good one because the MD is not optimized for timing applications. In conclusions the main achievement is defined as a prototype amplitude discriminator, for the ALICE L0 multiplicity Trigger, has been designed, elaborated and tested to stand short nanosecond signals coming from the ALICE T0/Centrality detector on Micro Channel Plates base. Commercially available, inexpensive and fast components have been used to implement the prototype MD. It features an input signal range from 0 to plus-minus 2.5 V, a programmable threshold control with 8 bit resolution, and an output signal latency of 15 ns. The minimum input signal charge, needed to trigger the scheme over the DAC threshold, has been found in about 0.26 pC. While applying the MD for timing in MIPs time-of-flight measurements, a resolution of about 120 ps has been obtained. The MD was also tested by studying the response to real MCP signals as a function of the MD threshold.

J.J. van Hunen (For the ALICE collaboration)
CERN, European Organization for Nuclear Research
CH - 1211 Geneva 23
Switzerland
Jeroen.van.Hunen@cern.ch
Office : 160-1-012
( : 41-(0)22-7679961
GSM : 41-(0)79-2014785
Fax : 41-(0)22-7679480

The Alice1LHCb front-end chip has been designed in a 0.25um CMOS commercial technology, with special design rules to obtain radiation tolerance, for the ALICE pixel and the LHCb RICH detectors. The chip has been irradiated with low energy protons and heavy ions, to determine the cross-section for Single Event Upsets, and with X-rays to evaluate the sensitivity to the Total Ionizing Dose. We report the results of those measurements. We also report preliminary results of measurements done with minimum ionising particles in a test beam at the CERN SPS.

The on-detector electronics of the ALICE silicon pixel detector (nearly 10 million pixels) consists of 1,200 readout chips, bump-bonded to silicon sensors and mounted on the front-end bus, and of 120 control (PILOT) chips, mounted on a MCM together with opto- electronic transceivers. The radiation environment in the pixel detector requires radiation tolerant components. The front-end chips are all ASICs designed in a commercial 0.25 micron CMOS technology using radiation hardening layout techniques. An 800 Mbit/s Glink- compatible serializer and laser diode driver, also designed in the same 0.25 micron process, is used to transmit data over an optical fibre to the control room where the actual data processing und event building are performed. We describe the system and report on the status of the PILOT system.

Summary

The on-detector electronics of the ALICE silicon pixel detector (nearly 10 million pixels) includes 1,200 front-end ASICs, bump-bonded to silicon sensor ladders. Two ladders (5 pixel chips each), mounted on a front-end bus, constitute a half-stave. The complete detector consists of 120 half-staves on two layers. The timing,  control and readout of each half-stave are done by a PILOT ASIC, mounted on a MCM together with opto- electronic transceivers. The MCM is wire-bonded to the bus and is connected to patch-panels, at about 1m distance, with a copper flex (power supplies) and three optical fibres. The fibres carry, respectively: (a) the incoming 40MHz clock, (b) the incoming trigger and configuration data, (c) the outgoing status and readout data.

The on-detector chips have been designed in a commercial 0.25 micron CMOS technology using radiation hardening layout techniques. This allows to achieve, and in fact considerbly exceed, the radiation tolerance requirement for the ALICE pixel detector, where the expected total ionisation dose is around 2kGy over 10 years.

The pixel detector must comply with severe space and material budget constraints. The front-end bus is an aluminium/polyimide multilayer. The MCM dimensions should not exceed 1.2mm thickness and 50mm length, with less than 10mm width available for the components.

The PILOT ASIC initiates the readout of the pixel chips, converts data levels from GTL to CMOS, reformats the data stream and forwards the data to a serialiser ASIC (named GOL) that includes a driver for the laser diode transmitter. Data are sent out on a fibre at 800Mb/s rate using the G-link protocol. The PILOT converts the incoming clock, serial trigger and serial JTAG signals into control signals for the pixel chips. The PILOT forwards the configuration data to the pixel chips, to the GOL, and to an auxiliary analog chip containing DACs that generate reference voltage and current levels.

The back-end electronics in the control room consists of 20 VME based router cards, each equipped with 6 pixel data converter daughter cards. Each data converter daughter card receives data from a half stave, performs zero suppression, reformats the data and stores it into an event memory. The router cards multiplex data from its 6 data converter daughter cards into one sub event block, reformat the data stream and send the data via the detector data link to the ALICE data acquisition. The trigger and configuration data are sent via the router card to the data converter card where they are serialized and sent to the PILOT via the optical fibre link.

This paper describes the pixel detector system and reports on the status of development and test of the PILOT.

The unit is designed to control and monitor the front end electronics, and to collect and ship data onto the Detector Data Link (optical fibre). Handling and distribution of the central trigger is also done, with the use of the onboard mounted TTCrx chip. For the prototype of the RCU the Altera EP20K400 FPGA has been used for application specific system integration.

The TPC Readout Controller Unit (RCU) is responsible for controlling the readout of the TPC, and initialising and monitoring the Front-End Cards (FECs). In total 180 RCUs will have 4500 FECs connected, with a maximum of 32 cards connected to each RCU.

On the FECs the amplifying, shaping, digitizing, processing and buffering of the TPC signals is done. A custom integrated circuit, the ALTRO (ALICE TPC Read Out), is dedicated to the processing of the digitized data. This chip is initialised and controlled directly from the RCU.

The communication between the Readout Controller Unit (RCU) and the ALTROs on the Front-End Cards (FECs) is implemented via a custom bus based on a shielded ribbon cable and a custom protocol.

The RCU collects the data from the FECs, assembles a subevent, compresses the data and sends the compressed, packed subevent to the Read Out Receiver Card (RORC). Shipping of data to the RORC (through optical fibre), is done via a custom interface named the Detector Data Link (DDL).

In addition, the RCU monitors and initialises the FECs. This supervision includes read-out of events for monitoring purposes, statistics (read out of number of datastrobes and number of triggers received), temperature variation monitoring, current measurement and power consumption monitoring for hardware fault detection. This is done via a separate slow-control bus. The initialisation of the ALTROs (including uploading of pedestal values for the digital filter responsible for tail-cancellation) is done via the main front end bus.

For the prototype of the RCU the Altera EP20K400 FPGA has been used for application specific system integration. The custom front-end bus protocol and the front-end slow control are both implemented in this FPGA.

On the RCU there will be a memory bank able to store a few full events (SRAM). The memory controller (FIFO structure) for this, is implemented in the FPGA.

A readout sequence of the TPC is initiated by a common ALICE trigger signal. This trigger is distributed to the RCU from the central trigger control. A custom Trigger Receiver Chip (TTCrx) is placed on the RCU. The interface to the TTCrx is implemented in the FPGA.

For monitoring purposes during operation a Slow Control Unit will be used. The Slow Control bus from the RCU will be connected to the central Detector Control System (DCS) of the ALICE experiment.

Several testbenches have been designed in order to test the controller unit. A first prototype of the RCU has been developed.

Authors :
E.Carrone , M. Davenport , G. De Cataldo†, A. Franco†, P.Martinengo , E. Nappi†
Presenter :
Enzo Carrone for the ALICE collaboration - CERN CH1211, Geneva 23, Switzerland
Contact :
Enzo Carrone
Enzo.Carrone@cern.ch
CERN 1-R-035 CH1211, Geneva 23 - Switzerland
( +41-22-76 71935

The HMPID (High Momentum Particle Identification Detector) detector is one of the ALICE (A Large Ion Collider Experiment) subdetectors planned to take data at LHC at the beginning of 2005. Since ALICE will be located underground, the HMPID will be remotely controlled by a Detector Control System (DCS), which consists of three layers: physical, control and supervisory.

The first one includes sensors, actuators and the detector, the second one deals with the device where the control programs run, and finally the supervisory layer contains the Machine-Man Interface (MMI), which lets the user run the DCS.

In this paper we will present the DCS design, accomplished via GRAFCET (GRAphe Fonctionel de Commande Etape/Transition), a tool which represents the DCS as a finite state machine, and then translated into code readable by the PLC (Instruction List) via an ad hoc algorithm. The SCADA DCS is based on PVSS, a commercial software. The results achieved so far show that this way of proceeding is effective and time saving, since every step of the work is autonomous, making simpler the debugging and updating phases.

Politecnico di Bari, Italy and CERN, Switzerland
CERN, Switzerland
INFN Bari, Italy

A.van den Brink(a), F.Daudo(b), S.Coli(b), G.Feofilov(c), G.Giraudo(b), O.Godisov(d), S.Igolkin(d), P.Kuijer(a), G.-J.Nooren(e), A.Swichev(d), F.Tosello(b)

a/    Utrecht University, Netherlands
b    /INFN, Torino,Italy
c/    St.Petersburg State University, Russia
d/    CKBM,St.Petersburg, Russia
e/    NIKHEF, Amsterdam, Netherlands

Reporter: G.Feofilov
(For the ALICE collaboration)

P.G.Kuijer@fys.ruu.nl
giraudo@to.infn.it
A.vandenBrink@fys.ruu.nl
DAUDO@to.infn.it
tosello@to.infn.it
igolkin@hiex.phys.spbu.ru>
godisov@nataly.spb.su
nooren@nikhef.nl
coli@to.infn.it

We present analysis, technology developments and test resultsof the heat drain system of the SDD and SSD front-end electronicsfor the ALICE Inner Tracker System (ITS). The application of the superthermoconductive carbon fibre thin plates provides a practicalsolution for the development of miniature motherboardsfor the FEE chips situated inside the sensitive ITS volume.Unidirectional carbon fibre motherboards of 160 -300 micron thicknessensure the mounting of the FEE chips and the efficient heat sink tothe cooling arteries. Thermal conductivity up to 1.3 times better thencopper is achieved while preserving a negligible multiple scatteringcontribution by the material (less then 0.07-0.15 percent of X/Xo).

1) State-of-the art Front-end electronics of coordinate-sensitive Si detectors of ALICE at the LHC is situated inside the Inner Tracking System region. Therefore the heat drain of about 7kW of power is to be done under the stringent requirement of minimisation of any materials placed in this area. Analysis of various possible cooling schemes was performed earlier as a starting point of the general ITS services design.

The application of super thermoconductive carbon fibre plastics was proposed in order to get the most efficient integration of the extremely lightweight FEE motherboards and the local heat sink units. ANSYS simulations show the value of temperature gradients along the boards which are in line with the requirements of the systematic aspects of detector performance (gradients of less then 1 degree C).

2) The implementation of these ideas in a single unit called "the heat bridge"

required the development of a new technology of thin unidirectional carbon fibre plates manufacturing. This technology was successfully developed and is being progressing further at present. The application of super thermoconductive fibre Thornell KX1100 for this purpose is the key point.

The conductivity along the fibre is about 1100W/M/K, while the mechanical strength is ensured at the level of steel. The thermal expansion coefficient of the carbon fibre based compounds is very low (close to zero), meaning the mechanically stabilised devices. The flat carbon unidirectional fibre plates were manufactured ranging in thickness from 150 to 330 microns.

The dimensions of the plates used could be from 1*7 - to 10*10 cm2. Summary of the different configurations of heat bridges produced is presented. Various types of surface coatings were also tested: pure carbon fibre surfaces and insulating Al ceramics coatings.

The carbon fibre heat bridge surface quality tests were done for a batch of CF plates. The roughness of the surface was measured and found to better than 10 microns. The choice of technology for ALICE SDD and SSD FEE chips was performed. The prototype heat bridges were tested for mounting and microcable bonding technology.

3) Thermal conductivity tests were performed for a variety of heat bridges. Results show the performance of the best samples at the level of 1.3 of copper of the same geometry.

A. Rivetti (1,2), G. Anelli (3), G. Mazza(2), I. Martinez (2,4), F. Rotondo (2), F. Tosello (2), R. Wheadon (2)

for the ALICE collaboration

1. Università di Torino, Dipartimento di Fisica Sperimentale, Via P. Giuria 1, 10125, Torino - ITALY
2. INFN, Sezione di Torino, Via P. Giuria 1, 10125, Torino - ITALY
3. CERN, EP Division, CH1211, Geneve 23, Switzerland.
4. Cinvestav, Mexico-City, Mexico.

Abstract

The front-end system of the Silicon Drift Detectors (SDDs) of the ALICE experiment is made of two ASICs. The first chip performs the preamplification, temporary analogue storage and analogue-to-digital conversion of the detector signals. The second chip is a digital buffer that allows for a significant reduction of the connection from the front-end module to the outside world. In this paper the results achieved on the first complete prototype of the front-end system for the SDDs of ALICE are presented.

Summary

Silicon Drift Detectors will be used in the third and fourth layer of the Inner Tracking System (ITS) of the ALICE experiment. In order to exploit the capabilities of the SDDs in terms of both spatial and energy resolution, analogue read-out must be performed. Therefore, for each anode of the sensor, the signal must be amplified and converted to a digital representation with high accuracy. The very limited space that will be available on the final hybrid made it mandatory to implement the whole analogue processing chain on the same chip. A half-size prototype of this unit has been developed. It contains 32 preamplifiers, a 32-channel analogue memory and sixteen 10-bit charge redistribution converters. The chip has been designed in a 0.25um CMOS process, using radiation tolerant layout techniques. After digitisation, the data must be transferred outside the front-end hybrid to an ASIC, which performs data compression and formatting. Since the use of one digital bus per each front-end chip would lead to an impractical number of connections, a multi-event buffer strategy has been adopted. The data are stored in a digital memory with a two-event capability. In this way, only a single 8-bit bus every four front-end chips can be used. A full-size prototype of the digital buffer has been produced as a custom ASIC in a 0.35um CMOS process. Since the digital buffer and the front-end chip are located very close to each other on the same hybrid, it is very important to assess the functionality of the whole system. The aim is to guarantee that the performance of the front-end are not impaired by the significant amount of digital activity. For this purpose, extensive measurements have been carried-out on a preliminary version of the system that contains one front-end chip and one digital memory. The results of these tests will be described in detail in this paper for the first time. These results are extremely positive, since no degradation in the performance of the front-end due to the digital buffer has been observed. The overall system fulfils the requirements of the experiment in terms of speed (peaking time 45 ns), dynamic range (9 mips), resolution (10 bits) and with a preliminary noise performance already compatible with the ALICE read-out requirements. On the basis of this experience, a complete hybrid hosting four front-end chips and four digital buffers is under design and will be tested by the end of the year.

Further Developments in the ALICE Trigger

Anton Jusko (Slovak Academy of Sciences, Kosice) for the ALICE Collaboration

ABSTRACT

The ALICE experiment is completing its technical specification stage, with most sub-projects about to start building. The development of the trigger system must mirror this process by specifying the interfaces and protocols for each stage in the trigger. In addition, in ALICE, sub-detector  groups will be able to test their systems using a Local Trigger Unit (LTU), which provides the sub-detector front-end systems with the correct sequence of signals driven either by the Central Trigger Processor (CTP) or by a simple pulser.

In the last year a draft User Requirement Document (URD) has been prepared for the CTP. Recently, changes have been recommended for the number of inputs and trigger classes. A study of the implementation of these new reuirements will be presented.

SUMMARY

Most of the detectors in ALICE have now completed their Technical Design Reports (TDRs) and are preparing to start production. A TDR has not yet been produced for the trigger system and the data-acquisition system, and this is not expected to happen until the second half of next year. However, the interfaces of these systems to each other, and also the interface to each sub-detector, are  being specified well before this so as to to guide the electronics designers for the sub-detector systems. This process was started in 1999 for the trigger system, leading to the release of a draft User Requirement Document (URD) for the Central Trigger Processor in May 2000. The main points in this were reviewed las year at the LEB workshop in Cracow.

The principal challenges for the ALICE trigger come from the fact that the front-end systems chosen for many of the detectors can tolerate a short latency (about 1.2 microseconds in the worst case), and that others have very long sensitive periods (up to about 100 microseconds) leading to potential problems with pile-up. In order to cope with the first problem, the trigger must be split into two "fast" levels, with latencies of 1.2 microseconds and  5.5 microseconds (L1), as not all trigger levels are ready in time for the earliest level (L0). The second requires a third trigger level (L2) and monitoring of "past-future protection", in this case to ensure taht no more than a certain number of interactions take place in a designated past-future protection interval, related to the sensitive time for the detector.

It turns out that a convenient method for combining these properties is through the notion of trigger classes. A set of parameters, such as the list of detectors to be read out, the required conditions on the inputs, the past-future protection conditions to be imposed and the scaling factors to be applied are associated with each trigger class, and these govern the operation of the trigger. In order to do this straighforwardly, it is envisaged that each trigger class brings with it a block of electronics repeated according to the number of allowed concurrent trigger classes.

In ALICE, it is envisaged that a Local Trigger Unit (LTU) will act as the interface between the CTP and each sub-detector's front-end electronics. This unit will also allow sub-detectors to work in stand-alone mode, providing the correct sequence of signals from a  pulser input. This allows each sub-detector group to operate autonomously throughout the development and installation stages.

A new evaluation of the physics aims for the ALICE trigger is in progress, which will lead to a clearer idea of the trigger requirements. The originally proposed numbers for inputs and classes are close to the practical limits for a completely general system. A   re-appraisal of the CTP is in progress, The final numbers in the system parameters, and the restrictions, if any, to be applied, are being determined.