*Corresponding author, E-mail: brettel@mppmu.mpg.de

The slow control of sub-detectors and components of ATLAS is realized by a SCADA software installed in a computer net. At present it is PVSS2 from the Austrian company ETM.

Links between net nodes and hardware are realized in different ways. Between the last node and the detector electronics a CanBus is foreseen in some cases for the transfer of control signals and the survey of temperatures, supply voltages and currents.

An example are the Hadronic End Caps of the Liquid Argon Calorimeter. The application software in a PC, called PVSS2-project, has a connection to the CanBus via a driver software OPC and an interface board NICAN2 and acts as bus master. CanBus slaves are offered by the industry for several purposes. We use the ELMB from the CERN DCS group, which is tailored to our needs. It has 2 microprocessors inside and digital and analog I/O ports.

Each of the two HEC-wheels consists of 4 quadrants served by a feed-through with a front-end crate on top of it. The low voltages for 40 PSBs , the preamplifier and summing boards which contain the cold GaAs front-end chips, are delivered by a power box, installed between the fingers of the Tile Calorimeter, about half a meter away from the crates.

The input for a power box – a DC voltage in the range of 200 to 300V – is transformed into +8, +4 and -2V at the 3 output lines by DC/DC converters. At 2 control boards the lines are split into 40 channels, one for the supply of each PSB. Integrated low voltage regulators for each power line offer the possibility for individual adjustment and ON/OFF control. We use L4913 and L7913 from STm. The ELMBs and logic chips are mounted also on the control boards and establish the connection between the regulators and the CanBus.

An ELMB has 8-bit digital I/O ports. In order to make the system architecture as simple as possible and increase reliability, only 5 of the 8 bits are used. One ELMB controls 5 PSBs which belong to the same longitudinal end-cap segment. The consequence is: if an ELMB would fail, only one longitudinal segment is affectedd..

The low voltage regulators have a current limitation. The maximal current is adjusted to such a low value, that the wires in the feed-through cannot be damaged in case of a steady short circuit inside the cryostat. In addition, in case of an over-current error signal from one regulator, the logic on the control board will switch off immediately all 3 low voltage regulators related to this channel. Then the control program is informed (via the CanBus) about details of the problem.

Meanwhile tests of hard and software prototypes have been carried out successfully. The work on control boards is progressing and we are gaining more experience with the PVSS2 software.We are considering also an emergency control system, independent of the CanBus, for the case that a computer or the bus itself would fail.

Authors: G. Antchev, E. Cano, S. Cittolin, S. Erhan, W. Funk, D. Gigi, F. Glege, P. Gras, J. Gutleber, C. Jacobs, F. Meijers, E. Meschi, L. Orsini, L. Pollet, A. Racz, D. Samyn, W. Schleifer, P. Sphicas, C. Schwick

Attila Racz <racz@cmsmail.cern.ch>

In the context of the CMS data acquisition system, simple and robust data links are required to transfer data from the underground counting rooms up to the surface buildings where complex processing of the data takes place. In the case of CMS, ~500 of these links, with an individual throughput of 400MB/sec over a distance of 200m, is required. The interface specification for these links as well as recent hardware developments are presented in this paper.

After reviewing the architecture and design of the CMS data acquisition system, the requirements on the front-end data link and the different possible topologies for merging data from the front-ends are presented. The front-end data link is a standard element for all CMS sub-detectors: its physical specification as well as the data format/protocol are elaborated within the Readout Unit Working Group where all sub-detectors are represented. The current state of the link definition is covered. Finally, prototyping activities towards the final link as well as test/readout devices for Front-End designers and DAQ developers are described.

Dr.Sci. Vyacheslav Viniogradov
Institute for Nuclear Research RAS
prosop.60-let october 7-a , Moscow,
117312 Russia
vin@inr.troitsk.ru
( 3340190
Fax 3340184

Abstract

Modular approach to development of Distributed Modular System Architecture for Detector Control, Data Acquisition and Trigger Data processing is proposed. Multilevel parallel-pipeline Model of Data Acquisition, Processing and Control is proposed and discussed. Multiprocessor Architecture with SCI-based Interconnections is proposed as good high-performance System for parallel-pipeline Data Processing. Tradition Network (Ethernet –100) can be used for Loading, Monitoring and Diagnostic purposes independent of basic Interconnections. The Modular cPCI –based Structures with High-speed Modular Interconnections are proposed for DAQ and Control Applications. Distributed Control RT-Systems. To construct the Effective (cost-performance) systems the same platform of Intel compatible processor board should be used.

Basic Computer Multiprocessor Nodes consist of high-power PC MB (Industrial Computer Systems), which interconnected by SCI modules and link to embedded microprocessor-based Sub-systems for Control Applications. Required number of Multiprocessor Nodes should be interconnected by SCI for Parallel-pipeline Data Processing in Real Time (according to the Multilevel Model) and link to RT-Systems for embedded Control/

Institute of Physics of Azerbaijan Republic Science Academy,

370143, Baku, Husseyn Javid Avenue, 33.

State Oil Academy of Azerbaijan Republic,

370010, Baku, Azadlig avenue, 20.

E. M. Kerimova, S.N. Mustafaeva, S.I. Mekhtieva, S.M. Bidzinova, N. Z. Gasanov, A. I. Gasanov

Institute of Physics,
Academy of Sciences of Azerbaijan,
G. Javid Prospect,
33,370143 Baku, Azerbaijan
E-mail:_Physics @_lan.ab.az

This paper deals with the investigation of optical properties of TlGaS₂, TlInS₂, TlGaSe₂ single crystals and influence of Fe and Cu doping and also intercalation by Li ions on these properties. The following main results have been obtained.

Intercalation of TlGaSe₂ single crystals by Li ions brings about the shift of energy position of exciton absorption peak, related with direct transition to long-wave side of spectrum. In particular at 5K this energy shift is D E=15 meV. As a result of intercalation the coefficient of temperature shift of this exciton peak decreased half as many in absolute value and is ¶ E^ex/¶ T within the range 20£ T£ 105 K and -0.25^.10^-4 eV/K at 5£ T£ 20 K.

Study of absorption spectra of TlM_1-xFe_xS₂ (M-In,Ga) single crystals in wide temperature range 5¸ 200K showed, that, in particular the width of bandgap of TlGa_1-xFe_xS₂ (x=0.001; 0.005; 0.01) crystals as of TlGaS₂ crystals increases with temperature rise. For TlGa_0.999Fe_0.001S₂ there have been observed exciton absorption band (hn =2.58eV at T=5K) which with temperature rise is broadened and shifted to side of higher energy. There have been also determined values of direct optical transition in TlIn_1-xFe_xS₂ (x=0.005; 0.01) single crystals at 5 and 300K.

Study of exciton absorption spectra of TlInS₂ single crystals doped by Cu showed that doping leads to the shift of energy position of exciton peak to long-wave region and it also increases exciton bond energy at the absorption edge: if for TlInS₂ =20meV, for Tl_0.995Cu_0.005InS₂ =31meV, for Tl_0.985Cu_0.015InS₂ =54meV. Bohr radius of exciton and its effective mass are calculated.

Thus, doping and intercalation of TlMC₂^VI leads to modification of their absorption spectra, change of exciton characteristics, i.e. allow optical properties to be controlled.

B. Hallgren, H. Burckhart, H. Kvedalen

CERN, EP-ATI/CS
Bjorn.Inge.Hallgren@cern.ch
Hallvard.Kvedalen@cern.ch
Helfried.Burckhart@cern.ch

The ELMB is a plug-in board to be used in LHC detectors as a general-purpose system for the front-end control and monitoring. It is based on CANbus, is radiation tolerant and can be used in magnetic fields. Results of the radiation tests will be presented and examples of applications will be described.

A versatile general-purpose system for the front-end detector control, the Local Monitor Box (LMB) was designed in 1998 and tested by the ATLAS sub-detector groups in test-beam and other applications. With this experience and to match better all the needs of the ATLAS sub-detector groups a modified version, the Embedded Local Monitor Board (ELMB) was designed. The main feature of the ELMB is that the ELMB now comes in the form of a general- purpose plug-in board of the size 50x67mm. The board can either be directly plugged onto the sub-detector front-end electronics, or onto a general-purpose motherboard which adapts the analog I/O signals. In order to make the ELMB available to ATLAS and other LHC experiments, which have also expressed interest, a small scale production of 300 boards for evaluation has been made by the CERN EP-ESS group in spring 2001.

The ELMB is based on the ATMEL low-power RISC microcontroller ATmega103. A second microcontroller AT90S2313 performs in system programming and monitoring functions including radiation Single Event Effects. A separate controller the Infineon SAE81C91 is used for the CANbus. The CANopen protocol has been chosen as high-level software. The ELMB can be powered remotely with the help of three low-drop power regulators. The power needed is 5V, 20 mA for the CANbus, 3.3V, 15 mA for the microcontrollers and 5V, 10mA for the ADC. The regulators function also as low-pass filters and provide current limitation and thermal protection for the ELMB. On the backside of the PCB are two high-density connectors of SMD type and optionally a 16+7 bit delta-sigma ADC with 64 differential inputs. There are up to 34 digital I/O lines available. The ATmega103 runs at a clock speed of 4 MHz. It has 128 kbytes of on-chip flash memory, 4 kbytes of SRAM and 4 kbytes of EEPROM. Also when the ELMB is installed in the detector it is possible to program the flash memory of the processors using the In-System Programming feature of the processors via the CAN bus.

A motherboard is available in order to evaluate the ELMB and for non-embedded applications. On the backside it contains two 100-pin SMD connectors for the ELMB and sockets for adapters for the 64 channel ADC. There are adapters available for different temperature sensors like NTC resistors, 2 wire Pt1000 and 4 wire Pt100 sensors. The motherboard may be mounted in DIN rail housing of the size 80 x 190 mm. On the front side there are connectors for the ADC inputs, digital ports, a SPI interface, CAN interface and power connectors.

The environmental requirements are such that it can be used in the ATLAS cavern (USA15) outside of the calorimeter in the area of the muon detectors (MDTs) and further out. This implies tolerance to radiation up to about 5 Gy and 3E10 neutrons/cm2 for a period of 10 years and to a magnetic field up to 1.5 T. Several radiation tests of the ELMB have been made following the procedures as laid out by the ATLAS radiation policy. The results of TID tests made at Pagure, Saclay and GIF, CERN with different dose rates will be reported. Further neutron testing at Prospero and SEE tests at Cyclone/Louvain-la-Neuve are planned for spring and summer 2001. The ELMB was also tested for a week at 100 degrees for accelerated ageing corresponding to 40000h at 25 degree C.

S. Cadeddu, A. Lai*

INFN Sezione di Cagliari, Cittadella Universitaria, 09042 Monserrato
(Cagliari) - Italy

*Corresponding author,
( . Off +39 070 675 4913 * labs. +39 070 675 4973/5/8
Fax +39 070 510212
( . @ CERN +41 22 76 74968 - Bat. 14-04-005

alessandro.cadeddu@ca.infn.it
adriano.lai@ca.infn.it.
http://www.ca.infn.it/~elettro

We present a custom integrated circuit, developed in the IBM 0.25 micron technology. The chip is named DIALOG ((DIagnostics, time Adjuster and LOGics) and it is a fundamental ingredient of the LHCb muon front-end electronics. Each integrated circuit handles 16 front-end channels. The circuit generates the information used by the level 0 trigger starting from the front-end signals, by means of a suitable (programmable) logical combination. In addition, it integrates functionalities important for signal time-alignment and front-end channels diagnostics at run time.

The LHCb muon system supplies binary information, used by the fast L0 muon trigger. Nevertheless, the information used by the trigger does not coincide with the signals as output by the front-end Amplifier-Shaper-Discriminators (ASD). This is due to single channel maximum capacitance and sustainable rates. So, an important task of the electronics system is to generate trigger information, corresponding to 26,000 so called logical channels, starting from about 120,000 ASD signals, called physical channels. In order to minimize the number of links (and costs), such a function is performed on detector by DIALOG, our custom integrated circuit. The logical combinations necessary to generate the logical channels are different, according to the different detector regions. Consequently, DIALOG is configurable by writing suitable internal registers, which are accessible via an I2C interface. DIALOG is also important to time-align logical channels, in order to correctly synchronize the entire detector. This task is crucial for all the LHC experiments. DIALOG integrates 16 programmable delays, which allow shifting the signal phase by 32 steps of about 1.5 ns each. This covers two bunch-crossing periods. The programmable delays are used when setting up the detector before data taking, but can be re-programmed at any needed time by writing suitable internal registers. DIALOG contains also diagnostics features to distribute synchronous pulses to the ASD channels and to monitor the physical channels' activity. Moreover, it contains DAC’s to supply voltage thresholds to the front-end discriminators. All these functions are controlled via the I2C interface. DIALOG is being developed in the IBM 0.25 micron radiation hard technology. We plan to submit a first version in the next August run. We present the circuit internal scheme and layout and some characterizing simulations.

C. de La Taille,  LAL Orsay FRANCE

Christophe de LA TAILLE
Laboratoire de l'Accelerateur Lineaire
Centre d'Orsay - bat
F 91 898 ORSAY Cedex
taille@lal.in2p3.fr
( : (33) 1 64 46 89 39
Fax: (33) 1 64 46 89 34

In order to ensure the radiation tolerance of its front-end electronics located close to the detector, the LArG collaboration has migrated several COTS and FPGAs into DMILL ASICs. Up to seven digital chips and three analog chips have been submitted in 2000 and tested in the spring of 2001. The measurements results, including several irradiation and SEU tests will be summarized as well as the production issues.

R. Kluit, P. Timmer, J.D. Schipper, V. Gromov; NIKHEF Amsterdam

r.kluit@nikhef.nl
A.P. de Haas; NIKHEF Utrecht

The design of the control electronics of the front-end of the ALICE SSD is described. This front-end is build with the HAL25 (LEPSI) chip. The controls are placed in the ladder EndCap. The main EndCap functions are power regulation and latch-up protection for the front-end, control functions for the local JTAG bus, distribution of incoming control signals for the front-end and buffering of the outgoing analog detector data. The system uses AC-coupled signal transfer for double-sided detector readout electronics.
Due to radiation-, power-, and space requirements, two ASIC’s are under development, one for analog buffering and one with all other functions combined.

The ALICE ITS is build out of three layers, Pixel-, Silicon Drift- and Silicon Strip Detectors. For the SSD the development of the control-electronics inside the detector volume will be described.

The SSD is based on Double Sided Silicon Strip Detectors with 768 strips at each side. The detectors will be readout by the HAL25 (Hardened Alice128 in .25u CMOS) front-end chip developed by LEPSI Strasbourg.

The SSD consists of 2 layers of ladders, the inner with 34 and the outer with 38 ladders. The inner ladders contain 23 modules and the outer 26. The detector modules will be connected to the DAQ- & Control system via EndCap units mounted at the end of each side of the ladder. The available space is ~ 70x70x45 mm.

Since ALICE is a heavy-ion experiment the electronics must be susceptible for Single Event Effects (SEE). Total dose is not a big issue although levels up to ~50krad may not cause any degradation. Therefore the front-end chip and the electronics in the EndCap must be protected for latch-up and are now build in radiation tolerant technologies. The limited available space and the temperature constraints of the detectors (and environment) require a low power design.

Due to the use of double-sided detectors, the readout electronics on both sides operate at different potentials. To avoid ADC and control modules to operate at these bias potentials, all signals will be AC coupled to the corresponding voltage level. Also the analogue readout data will be AC coupled to a multiplexer/buffer, which is able to drive the differential signal to ADC modules (over 10m @ 10MHz). The front-end chips of the detector modules are readout in series, both the P- and N side of each detector module to one ADC channel.

The Low Voltage power for the front-end (2.5V) for the two bias levels is regulated inside the EndCap. This circuit not only provides the latch-up protection for the front-end but also for the control electronics and buffers in the EndCap itself.

The Front-end electronics is controlled via the JTAG bus and it is also used to monitor and control the EndCap functions. Errors like latch-up can be monitored and appropriate action can now be taken. Disabled front-end chips can be put in "by-pass" mode and this information is available for the DAQ system.

All previously mentioned functions of the EndCap will be integrated in two ASIC’s, one analog multiplexer/buffer (ALABUF) and one multipurpose control chip (ALCAPONE). This development is done using a commercial technology (0.25u CMOS) with radiation tolerant design techniques.

The multipurpose control chip houses a Bandgap reference (CERN), Regulator circuit with DAC (ALICE PIXEL or LEPSI), JTAG control, LVDS and CMOS buffers for AC coupling, ADC for monitoring and digital control functions for the front-end. Simulations of the analogue functions show good feasibility for use in the EndCap, tests after irradiation should clarify if this approach gives a satisfactory result for the EndCap design.

The regulator and the analog multiplexer/buffer circuits have been submitted to a MPW test run and test results will be compared with simulated data and discussed.

P. Moreira (1), T. Toifl (2), A. Kluge (1), G. Cervelli (1), F. Faccio (1), A. Marchioro (1) and J. Christiansen (1)

1. CERN-EP/MIC, Geneva, Switzerland
2. IBM Research, Zurich, Switzerland

Correspondin author:
Paulo Moreira, EP Division, CERN
Email: Paulo.Moreira@cern.ch

Gbit/s data transmission links will be used in several LHC detectors in trigger and data acquisition systems. In these experiments, the transmitters will be subject to high radiation doses over the experiment's lifetime. In this work, a radiation tolerant transmitter ASIC is presented. It supports two standard data transmission protocols, the G-Link and the Gbit-Ethernet, and sustains transmission of data at both 800 Mbit/s and 1.6 Gbit/s. The ASIC was implemented in a mainstream 0.25um CMOS technology employing radiation tolerant layout practices. A prototype was tested and its behavior under total dose irradiation as well as its susceptibility to single event upsets was studied. The experimental results are reported in the paper.

Several LHC detectors require high-speed (~ Gbit/s) digital optical links for transmission of data between the sub-detectors and the data acquisition systems. Typically, high-speed data transmission is required for both the trigger systems data path and the data readout systems. In general, those links will be unidirectional with the transmitters located inside the detectors and the receivers situated in the counting rooms. Due to the proximity to the collision point, the transmitters will be subject to high levels of radiation doses over the lifetime of the experiments. Additionally, the large numbers of high-speed optical links planned (of the order of 100K total for the four LHC experiments) impose strict constraints on device cost. Moreover, in trigger links, data has to be transmitted with constant latency and synchronously with the LHC 40.08 MHz reference clock - this to facilitate data alignment at the receiving end before the data is fed to the trigger processors. Although commercial optical links and components can be found that meet the bandwidth requirements of all of the LHC planned systems, those components generally have not been designed to withstand high levels of total dose irradiation. The few radiation-hardened devices, which exist on the market, have prohibitively high prices when the large number (~ 100K) of links required is taken into account. It was thus considered necessary to develop a dedicated solution that would meet the very special requirements of the High-Energy Physics (HEP) environment. Since only the transmitters will be subject to irradiation, only they need to be developed and qualified for radiation tolerance.

In this paper, a radiation tolerant ASIC developed for data transmission at both 800 Mbit/s and 1.6 Gbit/s is reported. The data format and encoding were chosen so that the transmitter can be operated with either a Gigabit Ethernet or a G-Link "commercial of the shelf" receiver. The IC was fabricated in a mainstream 0.25um CMOS technology using radiation tolerant layout practices. The paper will describe in detail the circuit architecture and its functionality. Emphasis will be given to the presentation of experimental results reporting on the robustness of the design against total dose irradiation effects and on the behavior of the device under ionizing radiation that gives origin to single event upsets (SEU). To assess the techniques used to improve the robustness against SEU phenomena, a performance comparison will be established with a previously developed 1.2Gbit/s serializer prototype.

Authors list:
Niels van Bakel, Jo van den Brand, Hans Verkooijen
(Free University of Amsterdam / NIKHEF Amsterdam)

Daniel Baumeister, Werner Hofmann, Karl-Tasso Knoepfle,
Sven Loechner, Michael Schmelling
(Max-Planck-Institute for Nuclear Physics, Heidelberg)

Martin Feuerstack-Raible
(University of Heidelberg)

Neville Harnew, Nigel Smale
(University of Oxford)

Edgar Sexauer
(now at Dialog Semiconductors, Kirchheim-Nabern, Germany)

Daniel Baumeister
baumeis@asic.uni-heidelberg.de

MPI for Nuclear Physics Heidelberg
ASIC laboratory
Schroederstr. 90
D-69120 Heidelberg
(: ++49 6221 544324
Fax : ++49 6221 544345

The Beetle front end chip for LHCb is a 128 channel pipeline chip developed in 0.25 um standard CMOS technology. After intensive testing of the first version (Beetle1.0), an improved design (Beetle1.1) has been submitted in March 2001. The key measurements on the Beetle1.0, which mainly drove the design changes for the Beetle1.1, are described together with first performance data of the new chip.

A 128 channel readout chip, the Beetle, has been developed for the LHCb experiment in 0.25 um standard CMOS technology. The latest design has been submitted in March 2001. The chip can be operated as analog or alternatively as binary pipelined readout chip and fulfills the requirements of the silicon vertex detector, the inner tracker, the pile-up veto trigger and the RICH in case of multianode photomultiplier readout.

The chip integrates 128 channels with low-noise charge-sensitive preamplifiers and shapers. The risetime of the shaped pulse is 25 ns, the spill-over left 25 ns after the peak at most 30%. A comparator per channel with configurable polarity provides a fast binary signal. Four adjacent comparator channels are being ORed and brought off chip via LVDS ports. Either the shaper- or the comparator output is sampled with the LHC-bunch-crossing frequency at 40 MHz into an analogue pipeline with a programmable latency of max. 160 sampling intervalls and an integrated derandomizing buffer of 16 stages. For analog readout the data are multiplexed with up to 40 MHz onto 1 or 4 ports. A binary readout mode operates with doubled output rate on two ports. Current drivers bring the serialized data off chip. The chip can accept trigger rates of up to 1 MHz, the readout time per event is within 900 ns. For testing and calibration purposes, a charge injector with adjustable pulse height is implemented. The bias settings and various other parameters can be controlled via a standard I2C-interface.

The first chip version (Beetle1.0) submitted in April 2000 had to be patched with a focused ion beam to be functional. The reason was a layout bug in the control circuit. Beetle1.1 fixes this bug. In addition it solves a problem with the bias network of the pipeline readout amplifier, avoids charge injection in the switch of the resetable amplifier and fixes an error inside the multiplexer. The measurements pointing out bugs and problems on Beetle1.0 are presented, the resulting design modification on the Beetle1.1 are described and first performance measurements with the new readout chip are shown

John W. Dawson, David J. Francis, William N. Haberichter,and James L. Schlereth

Argonne National Laboratory and CERN
John.Dawson@cern.ch

The TTCPR receiver is a mezzanine card intended for use in distributing TTC information to Data Acquisition and Trigger Crates in the Atlas Prototype Integration activities. An original prototype run of these cards was built for testbeam and integration studies, implemented in both the PMC and PCI form factors, using the TTCrx chips from the previous manufacture. When the new TTCrx chips became available, the TTCPR was redesigned to take advantage of the availability and enhanced features of the new TTCrx, and a run of 20 PMC cards was manufactured, and has since been used in integration studies and the testbeam. The TTCPR uses the AMCC 5933 to manage the PCI port, an Altera 10K30A to provide all the logic so that the functionality may be easily altered, and provides a 4K deep FIFO to retain TTC data for subsequent DMA through the PCI port. In addition to DMA's which are mastered by the Add On logic, communication through PCI is accomplished via mailboxes, interrupts, and the Pass-thru feature of the 5933. An interface to the I2C bus of the TTCrx is provided so that internal registers may be accessed, and the card supports reinitialization of the TTCrx from PCI. Software has been developed to suport operation of the TTCPR under both LynxOS and Linux.

S. Zimmermann, J. Andresen, J.A. Appel, G. Cardoso, D.C. Christian, B.K. Hall, J. Hoff, S.W. Kwan, A. Mekkaoui, R. Yarema.

Sergio Zimmermann
Fermi National Accelerator Laboratory
Computing Divison/Electronic Systems Engineering Dept.
P.O. Box 500
Batavia, IL 60510
USA
e-mail: zimmer@fnal.gov
( : (630) 840-4276
fax: (630) 840-8208

At Fermilab, a pixel detector multichip module is being developed for the BTeV experiment. The module is composed of three layers. The lowest layer is formed by the readout ICs. The back of the ICs are in thermal contact with the supporting structure while the other side is bump-bonded to the pixel sensor. A low mass flex-circuit interconnect is glued on the top of this assembly, and the readout IC pads wire-bounded to the flex circuit. This paper will present recent results on the development of a module prototype and summarize its performance characteristics.

At Fermilab, the BTeV experiment has been approved for the CZero interaction region of the Tevatron. The innermost detector for this experiment will be a pixel detector composed of 64 pixel planes of approximately 100 mm by 100 mm each, assembled perpendicular to the colliding beams and installed a few millimeters from the beams. Each plane is formed by sets of hybridized modules, each composed of a single active-area sensor and of one row of readout integrated circuits (ICs).

The pixel detector will be employed for on-line track finding for the lowest level trigger system and, therefore, the pixel readout ICs will have to transfer data for all detected hits. This requirement imposes a severe constraint on the design of the readout IC, hybridized module, and data transmission. Several factors affect the amount of data that each IC needs to transfer: readout array size, distance from the beam, number of bits of pulse height information, the data format, etc. Presently, the most likely dimension of the pixel chip array will be 128 rows by 22 columns.

The BTeV pixel detector module is based on a design relying on a hybrid approach. With this approach, the readout chip and the sensor array are developed separately and the detector is constructed by flip-chip mating the two together. This method offers maximum flexibility in the development process, choice of fabrication technologies, and the choice of sensor material. The module is composed of three layers. The lowest layer is formed by the readout ICs. The back of the ICs are in thermal contact with the supporting structure while the other side is bump-bonded to the pixel sensor. The low mass flex-circuit interconnect is glued on the top of this assembly and the readout IC pads wired-bounded to the flex-circuit. The module is remotely controlled by the pixel Data Combiner Board, located approximately 10 meters away from the detector. All the controls, clocks and data are transmitted between the pixel module and the data acquisition system by differential signals employing the LVDS standard. Common clocks and control signals are sent to each module and then bussed to each readout IC. All data signals are point to point connected to the Data Combiner Boards.

A prototype module using the FPIX1 IC has been characterized. However, differently from the proposed "sandwich" module, the flex-circuit of this prototype is located on the side of the ICs. Typical results include threshold of 1500 electrons, threshold dispersion of 280 electrons and noise of 60 electrons. The comparison of these results with the characterization results of a single FPIX1 IC board shows no observed degradation in performance. Furthermore, tests with dead-time-less mode, where the charge inject in the front end is time swept in relation to the readout clock also does not reveal any degradation in performance, suggesting no crosstalk problems between the digital and analog sections of the FPIX1 IC and the flex-circuit.

Author List:
K. Hasuko(1), C. Fukunaga(5), R. Ichimiya(3), M. Ikeno(2), Y. Ishida(5), H. Kano(5), Y. Katori(1), T. Kobayashi(1), H. Kurashige(3), K. Mizouchi(4), Y. Nakamura(1), H. Sakamoto(4), O. Sasaki(2) and K. Tanaka(5)

(1) International Center for Elementary Particle Physics (ICEPP), University of Tokyo
(2) High Energy Accelerator Research Organization (KEK)
(3) Department of Physics, Kobe University
(4) Department of Physics, Kyoto University
(5) Department of Physics, Tokyo Metropolitan University

University of Tokyo
7-3-1 Hongo
Bunkyo-ku, Tokyo 113-0033, JAPAN

hasuko@icepp.s.u-tokyo.ac.jp
www.icepp.s.u-tokyo.ac.jp/~hasuko

We present the development of a remote control system for on-detector VME modules of the ATLAS endcap muon trigger. The system consists of a local controller in an on-detector VME crate and a remote interface in a Readout Driver crate. The controller and interface are connected with dedicated optical links based on G-LINK. The control system can fully configure and control modules, especially FPGA-embedded ones using G-LINK words and VME bus from remote host. The system supports periodical readback and reconfiguration to assure correct configuration data against SEUs. The idea, prototype and initial performance tests of the system are discussed.

We present the development of a remote control system for on-detector VME modules of the ATLAS endcap muon trigger. Such the VME modules are Star Switch (SSW) and High-pT board (HPT); the remote control system fully controls and configures them from outside of detector.

SSW is a relay module between on-detector modules and Readout Driver (ROD). SSW receives hit information from readout buffers in the modules, performs data reduction and formatting, and transfers the results to ROD. SSW is based on FPGAs which should be configured and controlled by the remote control system. Since the configuration data are susceptible to radiation-induced upsets (SEUs), dedicated control and configuration links are necessary, and every configuration should be assured to be correct via the links.

The other module, HPT, is a part of trigger system.HPT is based on ASIC configured with some registers inside and fully controlled via the same links from outside.

The remote control system consists of HPT/SSW Controller (HSC) and Control/Configuration Interface (CCI). HSC is a local controller in a HPT/SSW VME crate. CCI is a remote interface in a ROD crate. HSC communicates with the ROD host via CCI. HSC and CCI are connected with optical links based on G-LINK. The links are dedicated for control and configuration. The host manages an instruction set; each instruction is encoded into 14-bit G-LINK control word and executed on HSC. When downloading data, additional 16-bit data words are used. Following instructions, HSC can master the VME bus to access the HPT/SSW modules through VME protocol encoders implemented in CPLDs on both HSC and HPT/SSW modules. All the control and configuration are performed via VME accesses.

FPGAs in SSWs are also configured via the VME bus using byte-based configuration scheme. To resist SEUs, configuration data are periodically read back. Once a SEU is detected, the accessed FPGA is instantly reconfigured.

The CPLDs as VME protocol encoders are configured with JTAG provided on the VME backplane. These JTAG signals are in a bus structure and mastered by an embedded JTAG controller on HSC with dedicated instructions. Most of the HSC functionalities are also built using CPLDs; they are configured with the same JTAG bus. Only the core part of instruction encoders on HSC manages the JTAG-related instructions and built using an ASIC to resist SEUs. Therefore all the related CPLDs are configurable using the JTAG provided via the ASIC encoder.

The detailed idea, prototype and initial performance tests of the HSC/CCI control system are discussed in this workshop. We will also discuss that the performance meets the requirements for controlling and configuration of HPT and SSW modules.

G. Hallewell, Centre de Physique des Particules de Marseille
S. Kersten, University Wuppertal
Susanne.Kersten@cern.ch

The pixel detector of the ATLAS experiment at the CERN LHC will contain around 1750 individual detector modules. The high power density of the electronics - requiring an extremely efficient cooling system – together with the harsh radiation environment constrains the design of the detector control system.

An evaporative fluorocarbon system has been chosen to cool the detector. Since irradiated sensors can be irreparably damaged by heating up, great emphasis has been placed on the safety of the connections between the cooling system and the power supplies. An interlock box has been developed for this purpose, and has been tested in prototype form with the evaporative cooling system.

We report on the status of the evaporative cooling system, on the plans for the detector control system and upon the performance and irradiation tests of the interlock box.

Authors :
Yasuo Arai
KEK, National High Energy Accelerator Research Organization
Institute of Particle and Nuclear Studies
1-1 Oho, Tsukuba, Ibaraki 305-0801, JAPAN
( +81-298-64-5366, fax +81-298-64-2580
yasuo.arai@kek.jp
and
T. Emura
Tokyo University of Agriculture and Technology

ATLAS Muon TDC (AMT) LSI has been successfully developed and performance of a prototype chip (AMT-1) was reported in the LEB 2000. A new AMT chip (AMT-2) was developed aiming for mass production. The AMTs were processed in a 0.3 um CMOS Gate-Array technology, To proceed to a mass production of 400 k channels (~17,000 chips) scheduled in 2002, a systematic test methods must be established. Furthermore, the chip must be qualified to have adequate radiation tolerance in ATLAS environment. The test method and results of the radiation tests for gamma rays and charged particles will be presented.

A TDC LSI for the ATLAS precision muon tracker (MDT) has been developed. The TDC chip, called AMT, was processed in a 0.3 um CMOS Gate-Array technology. It contains 24 input channels, 256 words level 1 buffer, 8 words trigger FIFO and 64 words readout FIFO. It also includes trigger-matching circuit, which selects data according to a trigger. The selected data are transferred through 40 Mbps serial line. By using a Phase Locked Loop (PLL) circuit, it achieved 300 ps timing resolution. The chip is packaged in a 144 pins plastic QFP with 0.5 mm pin pitch and about 110k gates are used.

A prototype chip, AMT-1 was successfully tested and reported in the last LEB workshop. The AMT-1 was mounted in a front-end PC board with ASD (Amp/Shaper/Discri) chips, and system tests connected to a detector have been done (submitted in this workshop).

A mass-production prototype chip, AMT-2, has been recently developed. Although the AMT-1 was successfully operated, it consumed relatively large power in inside LVDS receiver circuits. A low-power LVDS receiver was developed and included in the AMT-2. In addition, testability was enhanced and several minor bugs are also fixed.

Mass production of 400 k channels (~17,000 chips) are scheduled in an early period of 2002. Most of the chip tests are done in manufacture, but a systematic test system are still needed. Furthermore the chip must be qualified to have adequate radiation tolerance in ATLAS environment. Gamma-ray irradiation to measure Total Ionization Damage (TID) and proton irradiation to measure Single Event Effects (SEE) are planned.

Test methods and results of the radiation tests will be presented.

M. IMORI
( : +81 3 3815 8384
Fax: +81 3 3814 8806
E-mail: imori@icepp.s.u-tokyo.ac.jp

ICEPP
University of Tokyo
7-3-1 Hongo,
Bunkyo-ku,
Tokyo 113-0033, Japan

The article describes a network of high voltage power supplies which can work efficiently under a magnetic field of 1.5 tesla. The high voltage power supply incorporates a piezoelectric ceramic transformer. The power supply includes feedback to stabilize the high voltage output, supplying from 2000V to 4000V with a load of more than 20 megohm at efficiency higher than 50 percent. The high voltage power supply includes a Neuron chip, a programming device processing a variety of input and output capabilities. The chip can also communicate with other Neuron chips over a twisted-pair cable, which allows establishing a high voltage control network consisting of a number of power supplies each of which incorporates the chip individually. The chip sets the output high voltage. The chip detects the short circuit of the output high voltage and controls its recovery. The chip also monitors the output current. The functions of the power supply under the control of the chip are managed through the network. The high voltage power supplies are networked, being monitored and controlled through the network.

Network-Controlled High Voltage Power Supplies Operating in Magnetic Field High Voltage Power Supply The article describes a network of high voltage power supplies. The high voltage power supply includes feedback to stabilize the high voltage output, supplying from 2000V to 4000V with a load of more than 20 megohm at efficiency higher than 50 percent. The power supply incorporates a ceramic transformer. So the power supply can be operated efficiently under a magnetic field of 1.5 tesla. The power supply could be utilized in LHC experiments. The power supply includes an error amplifier and a voltage-controlled oscillator (VCO). The output voltage is fed to the error amplifier to be compared with a reference voltage. The output of the error amplifier is supplied to the VCO which generates the frequency of a carrier where the carrier drives the ceramic transformer. Voltage amplification of the transformer depends on the frequency of the carrier. So the feedback adjusts magnitude of the amplification by controlling the frequency.

Breakdown of Feedback

While the load of the power supply falls within an allowable range, the driving frequency is maintained higher than the resonance frequency of the transformer such that the feedback is negative as designed. The allowable range of load cannot cover, for example, short-circuiting the output high voltage to ground. When the load deviates beyond the allowable range, the driving frequency may decrease below the resonance frequency; a condition that will not provide the required negative feedback, i.e., positive feedback locks the circuit such that it is independent of load.

Network

The high voltage power supply includes a "Neuron" chip possessing a variety of input and output processing capabilities. The Neuron chip can communicates with other Neuron chips over a twisted-pair cable; a feature that allows establishing a network consisting of a number of power supplies that respectively incorporate the chip. Since most functions of the power supply is brought under the control of the chip, the power supplies are managed via the network.

Output High Voltage

The reference voltage is generated by a digital-to-analog converter controlled by the chip so that the output high voltage can be controlled by the network.

Recovery from Feedback Breakdown

The VCO voltage, being the output of the error amplifier, controls the driving frequency of the carrier. The feedback breakdown is produced by deviation of the VCO voltage from its normal range. The deviation is detected by voltage comparators, interrupting the Neuron chip. Once awakened, the chip reports the feedback breakdown and manages the power supply so as to recover from the breakdown.

Current Monitor

If both the output high voltage and the supply voltage are known beforehand, the frequency at which the transformer is driven depends on the magnitude of the load. The output current can be estimated from the driving frequency. The chip gets the driving frequency by counting pulses, which allows calculating the output current.

Authors: Jose Castelo, Vicente Gonzalez, Enrique Sanchis
IFIC and Dpt of Electronic Engineering. University of Valencia

Vicente Gonzalez
DSDC - Grupo de Diseño de Sistemas Digitales y de Comunicación
Dept. Ingenieria Electronica. Universitat de Valencia
vicente.gonzalez@uv.es

Abstract

"This works describes the present status and future evolution of the Read Out Driver for the ATLAS Tile Calorimeter. The developments currently under execution include the test of the adapted LAr ROD to Tile Cal needs and the design and implementation of the PMC board for algorithm testing at ATLAS rates. We will describe the test performed at University of Valencia with the LAr ROD motherboard and a new developped transition module with 4 SLINK inputs and one output which match the initial TileCal segmentation for RODs. We will also describe the work going on with the design of a DSP based PMC with SLINK input for real time data processing to be used as a test environment for optimal filtering."

N.Smale, M.Adinolfi, J.Bibby, G.Damerell, N.Harnew, S.Topp-Jorgensen
University of Oxford, UK

V.Gibson, S.Katvars, S.Wotton
University of Cambridge, UK

K.Wyllie
CERN, Switzerland

Development of a front-end readout system for the LHCb Ring Imaging Cherenkov (RICH) detectors is in progress. The baseline solution for the RICH detector readout electronics is the HPD Binary Pixel chip. This paper describes a system to transmit data with addresses, error codes and synchronisation from a radiation harsh environment. The total data read out in 900ns is 32x36x440 bits per L0 trigger, with a sustained L0 trigger rate of 1MHz. Multimode fibres driven by VCSEL devices are used to transmit data to the off-detector Level-1 electronics located in a non-radiation environment. This data is stored in 64Kbit deep QDRbuffers.

There are six stages in processing the pixel data and delivering them to the Level-1 buffer. The Level-0 radiation-hard region has an interface to/from the pixel chip, parallel /serial conversion, fibre optics and drivers. The Level-1 non-radiation region has a fibre optic receiver, serial/parallel conversion, data checking and Level-1 buffer storage. Each are described in turn.

The pixel interface: 'PInt'

The pixel chip requires an interface chip (PInt) that generates chip biasing and calibration test levels, handles the ECS (Experiment Control System) and TTC (Timing and Trigger Control). The interface adds error codes, addresses, parity and Beam crossing ID to the data. The data are synchronised to a Gigabit Optical Link (GOL). The PInt is being developed using a Spartan II FPGA chip, and then later ported into a 0.25uM CMOS radiation-hard ASIC.

Parallel to serial conversion

The GOL chip is a multi-protocol high-speed transmitter ASIC which is able to withstand high doses of radiation. The chip is run in the G-Link mode at 800Mbits/s and therefore transmits 20 bits of data in 25nS. There are 16 bits of data and 4 overhead bits for encoding. The CIMT (Conditional Invert Master Transition) encoding scheme is employed. The 20-bit word is then serialised and transmitted via a VCSEL (Vertical Cavity Surface Emitting Laser) and multimode fibres. The threshold of the laser driver may be adjusted during the lifetime of the experiment with the GOL chip.

Fibre Optic Drivers

VCSELs emit light perpendicular to their p-n junctions, high output luminosity and focussing allows for easy coupling to multimode fibres. Wavelengths are generally in the 760-960nm range and output power is typically 5mW for a multimode fibre. VCSEL arrays can be easily incorporated into single ICs which allow for a much better multiple-fibre package. The VCSELs have been proven to be very robust in terms of radiation and magnetic fields. The proposal is to use 2 VCSELs per pixel chip and drive the data over 80 metres of multi-mode fibre to the counting room at 800Mb/s.

The fibre optic receiver and serial to parallel converter

The data are to be received by a pin diode and processed by either a Hewlett Packard HDMP1034 or the Texas Instruments TLK2501IRCP.

Data checking and Level-1 storage.

Data arriving from the serial/parallel converter are in a 16 bit wide 36 bit deep format, received at a rate of 640Mbits/s. The data contain header and error codes that require checking and stripping so as to leave 32x32 bits of raw data. The raw data, with event ID, are proposed to be time multiplexed and stored in the Level-1 buffer. The Level-1 buffer is a commercially available QDR SRAM (Quad Data Rate SRAM). The QDR SRAM is a memory bank of 9Mbits and can be segmented into multiple 64K bit deep Level-1 buffers. Data can be read in and read out on the same clock edge at a rate of 333Mbits/sec. For the QDR control and address generation a Spartan II FPGA is proposed. The Spartan II is chosen for it's high performance and I/O count at a low cost. The other functions of the Spartan II are to process the data from the serial/parallel converter, interface to the ECS and TTC.

Conclusion

The readout scheme will be presented with results for bit error rates and synchronisation checking. Full compatibility with TTC and ECS for the whole integrated system will be demonstrated.

Agapito J. A.³, Cardeira F. M. ² , Casas J. ¹ , Fernandes A. P. ² , Franco F. J. ³ , Gomes P. ¹, Goncalves I. C. ² , Cachero A. H. ³ , Lozano J. ³, Marques J. G. ² , Paz A. ³, Ramalho A. J. G. ², Rodriguez Ruiz M. A. ¹ and Santos J. P. ³.

A study of several comercial instrumentation amplifiers (INA110, INA111, INA114, INA116, INA118 & INA121) under neutron and very low gamma radiation was done. Some parameters (Gain, CMRR, input offset voltage, input bias currents) were measured on-line and bandwith, slew rate and supply current were determined before and after radiation. Different digital-to-analog and analog-to-digital converters were tested under radiation . Finally, the results of the testing of some voltage reference and analog switchs will be shown.

Commercial instrumentation amplifiers have been tested: INA110 (fast settling time FET-Input amplifier), INA111 (High speed FET-input amplifier), INA114 & INA118 (bipolar instrumentation amplifier), INA116 (DiFET instrumentation amplifier) and INA121 (low power FET-Input instrumentation amplifier). Input offset voltage, input bias currents, differential gain and CMRR were measured under the irradiation once every 20 minutes during 5 days. After the irradiation, other parameters as slew rate, supply currents and bandwidth were measured.

It was observed that JFET-input, designed to have an excellent frecuency response, exhibit the best behaviour. On the other hand, the worst is a DiFET amplifier because its destruction happened quickly. This is a great surprise because, in early papers, it was found that the best operational amplifiers under neutron radiation were built in this technology. Most of other amplifiers were destroyed during the irradiation.

It was observed a growth of the input offset voltage and the bias currents. Differential gain remains constant upto a value of radiation wich depends on the different amplifiers. CMRR behaves in a similar way. In all the amplifiers that survived, the supply currents decrease and the frecuency response is degradated. The value of slew rate and bandwidth is lower and output signal is very distorted in the more irradiated amplifiers.

In MX7541 digital-to-analog converter a great increase of output current offset and integral non-linearity error were observed but gain error keeps constant until a total dose (3-5·10¹² cm^-2, 150 Gy) which destroy the converter. In this moment, a reduction of the number of output voltage levels was observed. Before the destruction, this number was reduced to 16, 8, 4 and none. The converter did not come back to work after the annealing. It is possible that the converter destruction was due to the vestigial gamma dose because an alike converter, AD7541 from Analog Devices, is reported to be destroyed at similar levels of gamma dose.

The study of the parameters of ADS1210 analog-to-digital converter has been carried out.

The resistance and the leakage current of DG412 analog switches were also measured. It was observed a high increase of the switch resistances. The initial value was 20-30 ohms but the last values obtained before the destruction was 80-100 ohms. It was observed an increase of the leakage current (absent in the beginning, it can reach 1 mA). The aparition of this current is due to the action of gamma rays that form charges inside the oxide of the MOSFET transistors and the oxide that covers the semiconductor. However, the growth of resistance value is due to the neutron radiation.

With respect to REF102 voltage reference, it was observed an increase of line regulation and, also, the lowest voltage needed to obtain the nominal output voltage moved from 12 volts to 16-20 volts.

Helio Takai and James Kierstead
Brookhaven National Laboratory
takai@bnl.gov

The power supplies for the ATLAS liquid argon calorimeter using 300V input DC-DC converters will be located in a high radiation environment. Over the life of the experiment (i.e. 10 years) the total ionizing dose is expected to reach 25 krad. Along with the total dose is a projected total fluence of 2x10^12 particles/cm^2 of 1 MeV equivalent neutrons of which a fraction of the total neutron fluence, 1x10^11 neutrons/cm^2, has energies above 20 MeV. These values include the standard ATLAS recommended safety factors. The anticipated effects in order of potential seriousness are: (a) single event burnout (SEB) of the input power MOSFET, (b) total dose effects on active CMOS and bipolar components and (c) neutron induced lattice displacements causing conductivity and other changes in active components. The power supply will also be subjected to a magnetic field at a strength of 50 Gauss.

Tests performed on commercially available modules manufactured by Vicor found that none satisfy the requirements. Therefore we are seeking a solution that involves a semi-custom design. This typically introduces questions of reliability and cost. The approach for the development of a prototype is to select a vendor with experience in designing power supplies for radiation environments, e.g. space environments. This provides some assurance that the power supply will be hardened to ionizing and neutron radiation. Then to reduce cost, the radiation hardened power MOSFET will be replaced with a less expensive commercial power MOSFET. It is known that by operating a commercial MOSFET at a lower (derated) voltage it is possible to use them safely in an environment with high-energy particles. For instance a 600 volt MOSFET operated at 500 volts might show a large SEB cross section but has a negligible SEB cross section at 300 volts.

We will report on the progress of the design and comment on the different practical issues of the process such as purchasing of components in lots and specifying parts. Results of power MOSFET qualification will also be presented as well as preliminary test results. Packaging and operational issues will also be discussed as time allows.

Jean-Michel Sainson
SI Engineering & Support
CERN - IT Division CE Group
CH - 1211 Genève 23
( :(41) 22 767 75 61
Fax:(41) 22 767 71 55
SUISSE / SWITZERLAND
mailto:J-M.Sainson@cern.ch
Intranethttp://cern.ch/support-specctraquest/

Because of increasing clock frequencies, faster rise times and wider busses, printed circuit board (PCB) design layout becomes an issue. The Cadence® SPECCTRAQuest™ SI (signal integrity) package allows the pre- and post-layout signal integrity analysis of a PCB designed in the Cadence flow under Allegro. Case studies of work done for some LHC detectors will be presented. These will show how the tools can help Engineers in design choice, optimizing electrical performance of board layout, to reduce prototype iterations and to improve production robustness. Examples will include work done on PCI 66MHz and GTL busses.

Antinori, F.(1,2), Ban, J.(3), BURNS, M.(1), Campbell, M.(1), CHOCHULA, P.(1, 4), Formenti, F.(1), Kluge, A.(1), Meddi, F.(1, 7), Morel, M.(1), Petra, Rober to, Snoeys, W.(1), Stefanini, G.(1), Wyllie K.(1).

(For the ALICE Collaboration)

Described is a system that has been developed for testing the ALICE Silicon Pixel Detector Readout Chip. It is capable of covering all aspects of testing, from the selection of know good dies on a wafer, characterisation, and as a DAQ when performing beam tests Considerable effort has been invested in the software to provide a comprehensive suit of facilities and test routines to enable the complete testing and characterisation of the device. In this paper we would like to present the objectives and requirements of the test system, a description of the hardware, software and database and present some of the results obtained.

The previous test system for the pre prototype ALICE1LHC Pixel detector Readout Chip was built using both CAMAC and VME components employing a standard processor that was sited in the VME crate. The system evolved continuously to increase the system functionality and automate the measurement process. This resulted in a bulky test system which was difficult to transport and almost impossible to reproduce. The results of the measurements were stored on the VME system local disk for treatment at a later date by another computer system. The new system has taken the analogue functionality of the CAMAC modules and integrated them into the circuitry contained on the Adapter Board. The VME crate had been kept and houses the modules required in the DAQ chain. A PC running LabView software has been selected as the system controller. The PC is interfaced to the VME system using the MXI bus connection from National Instruments The Adapter Board is controlled using a 4-wire JTAG connection from an interface which may be installed in either the PC or the VME crate. All test parameters may be varied interactively to enable detailed verification of the various subsections of the Pixel Chip or routines can be executed to automatically perform detailed measurements of the devices. Acquired data is treated and displayed via a graphical user interface exploiting the capabilities of LabView to rapidly present the results. The results may then archived for further reference when either assembling the Pixel Detector or by the ALICE online database.

The system requires approximately xx minutes to characterise a device and yy m inutes to test a whole wafer automatically.

N. Bondar*, T. Ferguson**, A. Golyash*, V. Sedov*, N. Terentiev**.
*) Petersburg Nuclear Physics Institute, Gatchina, 188350, Russia
**) Carnegie Mellon University, Pittsburgh, PA, 15213, USA

The very front-end electronics system for the anode signals of the CMS Endcap Muon cathode strip chambers has been designed. Each electronics channel consists of an input protection network, amplifier, shaper, constant-fraction discriminator, and a programmable delay with an output pulse width shaper. The essential part of the electronics is an ASIC consisting of a 16-channel amplifier-shaper-discriminator (CMP16). The ASIC was optimized for the large cathode chamber size (up to 3 m x 2.5 m) and for the large input capacitance (up to 300 pf). The ASIC combines low power consumption (30 mW/channel) with excellent time resolution (~2 ns). A second ASIC provides a programmable time delay which allows the alignment of signals with an accuracy of 2.5 ns. The electronics test results, including "on-chamber" test and radiation test, are presented.

Summary

The very front-end electronics system for the anode signals of the CMS Endcap Muon cathode strips chambers has been designed. The main tasks of the anode side of the detector are to provide a good time resolution and a high efficiency. To meet this requirement, the following measures were implemented:

-each channel was split into two parts: an analog section (amplifier-shaper-discriminator), followed by a digital delay and pulse width shaper.
-the analog part was placed as close to the anode outputs as possible, and the digital part was located on the input of the anode local charged track board (ALCT).
-the amplifier input circuits were very carefully arranged and shielded.

Two ASICs were designed. The first is a 16-channel amplifier-shaper-discriminator (CMP16). The ASIC was optimized for the large chamber size (up to 3 m x 2.5 m) and for the large input capacitance (up to 300 pf). The ASIC combines low power consumption (30 mW/channel) with excellent time resolution (~2 ns). The chip is made by AMI, using a BiCMOS 1.5 micron technology. To achieve a low input resistance and relatively low noise, a BJT was used as an amplifier first stage. A two-exponent tail cancellation system, with a semi-Gaussian shaper is also employed in the chip. A two-thresholds constant-fraction discriminator is used to obtain the required time resolution. Output signal levels are LVDS standard. The second ASIC is a 16-channel LVDS/TTL converter, with a programmable delay and output pulse width shaper. This chip was also made by AMI, using a CMOS 0.5 micron technology. The chip is a logical extension of the CMP16 chip in that it matches the amplifier outputs to the ALCT logic inputs and aligns the signals in phase at the input of the anode logic. To support the CMP16 chip, a 16-channel anode front-end board (AD16) was also designed. The board was made in the simplest and cheapest way possible. The threshold control network and the board test facility were delegated to the ALCT board. Each AD16 board is connected to the ALCT board with a 40-wire cable. This cable supplies the board with power, a threshold voltage setting and test pulses, as well as transmits the output signals to the ALCT. A special setup and accompanying procedures were designed to test and certify the AD16 boards and the two ASICs. The anode front-end electronics system has met the required specifications, and the mass production has begun.

C. Posch*, E. Hazen, J. Oliver:
christoph.posch@cern.ch
hazen@bu.edu
oliver@huhepl.harvard.edu

Development and performance of the final 8-channel front-end for the MDT segment of the ATLAS Muon Spectrometer is presented. This last iteration of the read-out ASIC contains all the required functionality and meets the envisaged design specifications. In addition to the basic "amplifier-shaper-discriminator"-architecture, MDT-ASD uses a Wilkinson ADC on each channel for precision charge measurements on the leading fraction of the muon signal. The data will be used for discriminator time-walk correction, thus enhancing spatial resolution of the tracker, and for chamber performance monitoring (gas gain, ageing etc.). The feasibility of the MDT system to perform particle identification through dE/dX measurement using the Wilkinson ADC is evaluated. Results of performance and functionality tests in the lab and on-chamber along with an outlook to volume-production and production testing are presented.

This article reviews the development of the final 8-channel front-end for the MDT segment of the ATLAS Muon Spectrometer and presents results of performance and functionality tests on the last pre-production prototype. The MDT-ASD is an octal CMOS Amplifier/Shaper/Discriminator which has been designed specifically for the ATLAS MDT chambers. Implementation as an ASIC using a high quality analog 0.5um CMOS process has been chosen for this device. The analog signal chain of the MDT-ASD has already been presented for a previous prototype version of the chip and has not been changed significantly since then. It will therefore be addressed only briefly in this article. New developments include the implementation of a Wilkinson type charge-to-time converter and on-chip programmability of certain functional and analog parameters along with a serial control data interface. Bipolar shaping was chosen to prevent baseline shift at the anticipated level of background hits. The shaper output is fed into a discriminator for the timing measurement and the Wilkinson ADC section for performing the leading edge charge measurement. The information contained in the Wilkinson output pulse, namely the leading edge timing and the pulse width encoded signal charge, will be read and converted to digital data by a TDC. The Wilkinson cell operates under the control of a Gate Generator which consists of all differential logic cells. It is thus highly immune to substrate coupling and can operate in real time without disturbing the analog signals. The final output is then sent to the LVDS cell and converted to external low level differential signals. The main purpose of the Wilkinson ADC is to provide data which can be used for the correction of time-slew effects due to pulse amplitude variations. Time slewing correction improves the spatial resolution of the tracking detector. In addition, this type of charge measurement provides a useful tool for chamber performance diagnostics and monitoring (gas gain, ageing etc.). Further applications such as dE/dx measurements of slow moving heavy particles like heavy muon SUSY partners etc are conceivable. Test results on the conversion characteristics as well as measurements of noise performance respectively non-systematic charge measurement errors of the Wilkinson ADC are shown. The feasibility of the MDT system to perform particle identification through dE/dX measurement using the Wilkinson ADC is evaluated and results of a simulation study on energy separation probability is presented. It was found advantageous to be able to control or tune certain analog and functional parameters of the MDT-ASD, both at power-up/reset and during run time. A serial I/O data interface using a JTAG type protocol plus a number of associated DACs were implemented in the chip. In order to facilitate prototype testing during the design phase as well as to perform system calibration and test runs with the final assembly, a calibration/test pulse injection system was integrated in the chip. It consists of a bank of 8 parallel switched capacitors per channel and an associated channel mask register. The mask register allows for each channel to be selected separately whether or not it will receive test pulses. The capacitors are charged with external standard LVDS voltage pulses, yielding an input signal charge range similar to the expected range of the tube signals. This pulse injection system allows for automated timing and charge conversion calibration of the system. Hence, in principle all systematic errors of the readout electronics can be calibrated out for each individual channel. As a final point, an outlook to volume-production and production testing of the chip is given.

The HAL25 is a mixed low noise, low power consumption and radtol ASIC intended for read-out of Silicon Strip Detectors (SSD) in the ALICE tracker. It is designed in a 0.25 micron CMOS process and is similar in concept to the previous chip ALICE128C. The chip contains 128 channels of preamplifier, shaper and a capacitor to store the charge collected on a detector strip. The analogue data is held by an external logic signal and can be serially read out through an analogue multiplexer. A slow control mechanism based on JTAG protocol was implemented for a programmable bias generator, an internal calibration system and selection of functional modes.

The HAL25 chip is a mixed analogue-digital ASIC designed for read-out of Silicon Strip Detectors (SSD) in the ALICE tracker. It is based on the ALICE first generation chip ALICE128C which was tested with good performance for an irradiation up to 50 krad. ALICE128C is now used in the SSD frontend electronic of the STAR tracker.

For the ALICE experiment, a new radiation hardened circuit design was required to meet the total dose radiation and latchup background. It has been demonstrated that commercial deep submicron CMOS technologies exhibit intrinsic radiation tolerance. HAL25 has been designed with special design technics in a 0.25 micron CMOS process which is expected to meet the demands of low noise, low power consumption and radiation hardness required by the ALICE experiment.

HAL25 contains 128 channels of preamplifier, shaper and a capacitor to store the charge collected on a detector strip. The data is held by an external logic signal and can be serially read out through an analogue multiplexer at 10 MHz.The chip is programmable by the JTAG protocol which allows:

- to set up an adjustable bias generator which tunes the performances of analogue chains;
- to choose the internal calibration system which sends a calibrated pulse to the inputs of selected chains;
- to perform boundary scan.

For the SSD layers, the ALICE experiment needs a readout circuit having very large dynamic range (+/-15 Mips) with good linearity and an adjustable shaping time from 1.4 us to 2.0 us. This is a challenge for such a circuit designed in a deep submicron process operated at only 2.5 V which is the edge of the use of standard analog design techniques.

This paper will explain how the required specifications have been met:

- single power supply;
- low noise;
- low power consumption (mean power consumption of designed circuit for a readout cycle of 1 ms is around 300 uW/ch);
- large dynamic input range (+/-15 Mips) with good linearity;
- differential current output to improve EMC;
- geometry adapted to Tape Automated Bonding.

The authors also expect to present evaluations of the circuit which was submitted to foundry at the end of March.

P.Aspell, D.Barney, P.Bloch, A.Go, C.Palomares
Paul.Aspell@cern.ch

DeltaStream is a 36 channel preamplifier and shaper ASIC that provides low noise, charge to voltage readout for capacitive sensors over a large dynamic range. The chip has been designed in the DMILL BiCMOS radiation hard technology for the CMS Preshower project. Two gain settings are possible. High gain (HG), has gain 30mV/MIP (7.5mV/fC) for a dynamic range of 0.1 to 50 MIPS (0.4fC – 200fC) and low gain (LG), has gain 4mV/MIP (1mV/fC) for a dynamic range of 1 to 400 MIPS (4fC – 1600fC). The peaking time is ~25ns and the noise has been measured at ~ENC = 680e + 28e/pF. Each channel contains a track & hold circuit to sample the peak voltage followed by an analog multiplexer operating up to 20MHz. The response of the signal is linear throughout the system. The design and measured results for input capacitance < 55pF are presented.

DeltaStream has an architecture that follows in the Amplex family of silicon sensor readout ASICs. It contains 36 channels, each of which contains a low noise preamplifier, shaper and a track & hold circuit to sample the peak voltage. An analog multiplexer then serializes the analog values into a single analog data stream.

DeltaStream has been developed to provide a readout ASIC suitable for the production testing of the CMS Preshower silicon sensors. It also serves as a multi-channel prototype chip for the preamplifier and shaper (Delta) and a 20MHz analog multiplexer intended for use within the Preshower front-end electronics analog memory ASIC called PACE.

DeltaStream is designed to be dc coupled to silicon sensor strips and is insensitive to dc leakage currents < 50mA per strip. Charge to voltage readout over a large dynamic range (< 400 MIPs) for total input capacitance up to 55pF with 25ns peaking times are the main design goals. Two gain settings are possible. High gain (HG), has gain ~30mV/MIP (7.5mV/fC) for a dynamic range of 0.1 to 50 MIPS (0.4fC – 200fC) and low gain (LG), has gain ~4mV/MIP (1mV/fC) for a dynamic range of 1 to 400 MIPS (4fC – 1600fC).

Measurements of gain, rise time and noise have been made in both HG and LG for two different levels of total input capacitance (13pF, 52 pF). The mean gain is as follows : HG (13 pF) = 33.1 mV/MIP, HG (52 pF) = 24.6mV/MIP, LG (13 pF) = 4.6 mV/MIP, LG (52 pF) = 3.4 mV/MIP. The rise time measured from 10-90% of the peak voltage is HG (13pF) = 18.9ns, HG (52pF) = 21.8ns, LG (13pF) = 14.5ns, LG (52pF) = 17.5ns, The standard deviation across all channels is ~3% for gain and ~1% for the rise time.

Noise has been measured for all the channels in high gain resulting in a mean value of ENC = 680e + 28e/pF.

The multiplexer operates at frequencies up to 20MHz with a linear response. It can also be used to individually select a channel allowing the full pulse shape to be readout.

Authors list with Institutions:
Franco Gonella from Dip. di Fisica dell'Universita' di Padova and Sezione INFN di Padova, Padova, Italy
franco.gonella@pd.infn.it

Matteo Pegoraro from Sezione INFN di Padova, Padova, Italy

Paper category :
LHC Experiment: CMS
LHC Experiment Subsystem: MU
LEB2001 Workshop topic: Electronics for muon detectors

To meet frontend electronics needs of CMS barrel muon chambers a full custom ASIC, named "The MAD", has been first developed by INFN of Padova and then produced in over 50.000 pieces to equip the 180.000 drift tubes. The chip provides 4 identical chains of amplification, discrimination and cable driving circuitry; also it integrates a flexible channel enabling/disabling capability and a temperature probe for monitoring purposes. The ASIC has been deeply tested resulting in good performances; particularly, big effort was put in radiation (neutron, gamma rays and ions) and ageing tests to check behavior and reliability in LHC environment.

The analog frontend electronics for the muon chambers of CMS barrel has been integrated in a full custom ASIC, named "The MAD", developed by INFN Padova using 0.8 µm BiCMOS technology from Austria Mikro Systeme. Each chip provides the signal processing for 4 drift tubes in a 2.5x2.5mm2 die housed in a TQFP44 package.The 4 identical analog chains contained in the ASIC are made of a charge preamplifier followed by a simple shaper with baseline restorer, whose output is compared against an external threshold by a latched discriminator; the output pulses are then stretched by a programmable one shot and sent to an output stage able to drive long twisted pair cables with LVDS compatible levels. The working conditions of the detector set requirements for high sensitivity and speed combined with low noise and little power consumption. Moreover, as the basic requirement for the frontend is the ability to work at very low threshold to improve efficiency and time resolution, a good uniformity between channels of different chips is needed for sensitivity and threshold. Gain value is 3.3 mV/fC in average, constant up to 500 fC input with less than 1% integral nonlinearity; saturation occurs at about 800 fC. Threshold uniformity is very good, the r.m.s. is below 0.6 mV and the propagation delay is about 4 ns for signals above 30fC. Key characteristics for low threshold operation are noise and crosstalk: bare chips exhibit ENC ??1400 e- (slope of 60 e-/pF) and a value below 0.1% for the latter. Once mounted on the PCB these two figures increase to 1900 e- and 0.2% mainly because of the input protection network necessary to prevent HV discharge events. The power dissipation of the chip is very low, about 25 mW/channel so reducing the need for heat removal. Control and monitoring features have been included in the chip: to mask noisy wires each channel can be disabled at the shaper input resulting in little crosstalk to neighbors. It's also possible to check trigger functionality using a fast disable/enable feature, controlled via LVDS levels, acting on the output driver of left and right channel pairs. An absolute temperature probe with a sensitivity of 7.5 mV/(K has been integrated in order to detect electronics failures and monitor environmental changes. Two separate power supplies (5V and 2.5V) are used in order to reduce power drain and minimize interference between input and output sections. The routing has been particularly cured for power, digital ground and analog ground and many pins have been reserved for this purpose. Reliability is a critical point in a hardly accessible environment as CMS detector: tests performed (accelerated ageing and irradiation with neutrons, heavy ions and gamma rays) show good MTBF characteristics, low SEU rate and immunity to latch-up events in spite of using a standard and not too expensive technology.

M. Ullan*, D. Dorfan*, T. Dubbs*, A. A. Grillo*, E. Spencer*, A. Seiden*,H. Spieler**, M. Gilchriese**, M. Lozano***

*Santa Cruz Institute for Particle Physics (SCIPP)
University of California at Santa Cruz
Santa Cruz, CA 95064, USA
(: 1 831 459 3567
Fax: 1 831 459 5777
E-mail: ullan@scipp.ucsc.edu

**Lawrence Berkeley National Laboratory (LBNL)
University of California at Berkeley
***Centro Nacional de Microelectrónica (CNM-CSIC)
Barcelona, Spain

Ionization damage has been investigated in the IC designed for the readout of the detectors in the Semiconductor Tracker (SCT) of the ATLAS experiment at the LHC, the ABCD chip. The technology used in the fabrication has been found to be free from Low Dose Rate Effects which facilitates the studies of the radiation hardness of the chips. Other experiments have been done on individual transistors in order to study the effects of temperature and annealing, and to get quantitative information and a better understanding of these mechanisms. With this information, suitable irradiation experiments have been designed for the chips to obtain a better answer about the survivability of these chips in the real conditions of the ATLAS detector.

The ABCD chip is the IC that has been designed for the readout of the silicon detectors of the ATLAS Semiconductor Tracker (SCT) at the LHC. It is fabricated on the DMILL technology, which is a BiCMOS process on an SOI substrate. This chip will have to be placed very close to the detectors and, therefore, inside the active area of the SCT. That means that it will have to endure the same level of radiation as the detectors themselves.

Different experiments have been carried out to study the radiation hardness of this technology and the ABCD chip itself to that high level of radiation. The physical mechanisms involved in the damage produced in the analog part of these chips from ionization or non-ionization radiation are different and it is better to study them separately to have a good understanding of the problem. This study is presented here where the effects of ionization radiation have been analyzed for the DMILL technology and the ABCD chip, taking into account the total dose effects.

A first study has been made to check if the bipolar transistors of the DMILL technology suffer from Low Dose Rate Effects (LDRE) which would greatly complicate the rest of radiation hardness studies. Different radiation experiments have been carried out up to a high enough total dose and at a very wide range of dose rates using individual transistors of the technology. The result has demonstrated that the DMILL technology does not suffer from total dose effects which facilitates the realization of other radiation hardness studies. This result has been confirmed by other irradiations up to the total dose of interest. Together with this study, the annealing of the damage produced on the transistors has been investigated in order to separate this effect from the LDRE.

Other experiments have been carried out at different temperatures in order to obtain the sensitivity of the radiation damage of these chips to temperature. The tests structures have been irradiated up to the total dose of interest and at a wide range of temperatures from 10 to 110 ºC. The results demonstrate the presence of two opposite effects. One is the increase in the damage at higher temperatures, and the other is the increase in the annealing of that damage also for higher temperatures. These two effects result in a worst case temperature at which the transistors suffer the largest damage, suffering less damage at lower and higher temperatures.

Finally the ABCD chip has been irradiated up to the total dose of 10Mrads and at a high dose rate in order to obtain the total ionization damage that will be produced in the chip in the real experiment. Given that it has been demonstrated that there are no LDRE with this technology, this experiment can be done at a high dose rate and in a short period of time. The results demonstrate that the ABCD chip remains within specifications after the expected ionization damage has been produced.

T.Ferguson ferguson@cmuhep2.phys.cmu.edu, N.Terentiev (teren@fn781a.fnal.gov)

(Carnegie Mellon University, Pittsburgh, PA, 15213, USA)

N.Bondar bondar@fnal.gov, A.Golyash, V.Sedov

(Petersburg Nuclear Physics Institute, Gatchina, 188350, Russia)

We report the results of several radiation tests on pre-production samples of the anode front-end electronics boards for the CMS endcap muon system. The crucial component tested was the 16-channel preamplifier ASIC (BiCMOS). The boards were exposed to doses up to 80 krad in a 63 MeV proton beam, and to a neutron fluence up to 2*10**12 n/cm**2 from a nuclear reactor. The static (current and voltage) and dynamic (noise,threshold, gain and timing) characteristics were measured versus the radiation dose.

The peak luminosity of LHC, 10**34 cm**-2*sec**-1, combined with the 7 TeV beam energy, will create a very hostile radiation environment in the detector experimental halls. Radiation tolerance and reliability are important issues for the CMS electronics, including the endcap muon CSC front-end electronics. The most severe conditions in the muon endcap region are in the vicinity of the ME1/1 CSC chambers. Here, the neutron fluence and the total ionizing dose (TID) accumulated during 10 years of LHC operation are expected to be about 6-7*10**11n/cm**2 (at En>100 keV) and 1.8-2 krad, respectively (Ref.1). The goal of our measurements was to test the performance of the anode front-end boards, with specially designed preamplifier chips (AMI 1.5 micron BiCMOS technology) on them, up to a level of 3 times these doses, and to observe the presence of single-event effects such as latch-up, at higher doses (Ref.2).

The boards were irradiated in a 63 MeV proton beam and received a TID up to 14 and 80 krad. No latch-ups or spikes or any changes in the static parameters (amplifier, discriminator and regulator voltages) were observed. However, the dynamic parameters such as threshold, gain and slewing time were sensitive to the radiation, showing a maximum deviation of 40% (for slewing time) at a TID of 60 krad. The noise and the resolution time were not affected at all. At the required 3 times level of TID (5-6 krad), all changes were practically negligible. The corresponding graphs will be presented. Some boards were exposed to a reactor neutron fluence up to 2*10**12 n/cm**2, at a neutron energy of 100 keV < En < 10 MeV. They also received a TID of about 50-60 krad from gammas which accompanied the reactor neutrons. About 50% of the boards survived, showing moderate changes (20-30%) in dynamic characteristics in a test taken one month after the irradiation. The rest of the boards recovered after one week of heating at 110 degrees C. Further heating returned all the parameters for all boards to the norm. From our results we can roughly estimate that, for the test doses given above, the annealing time is about a few months at room temperatures. Since the LHC rate of real radiation exposure is much slower than this, we conclude that the anode front end boards should not show any radiation damage during normal LHC operation.We are thankful to M. Tripathi and B. Holbrook of the University of California, Davis, and to T.Y. Ling and B. Bylsma of the Ohio State University for their valuable help.

G.M.Dallavalle, A.Montanari, F.Odorici, G.Torromeo, R.Travaglini, M.Zuffa
INFN and University, Bologna, Italy
Marco.Dallavalle@bo.infn.it

The Track-Sorter-Master (TSM) is an element of the on-chamber trigger electronics of a Muon Barrel Drift Tube Chamber in the CMS detector. The TSM provides the chamber trigger output and access to the trigger electronic devices for monitoring and configuration. The specific robustness requirements on the TSM are met with a partitioned architecture based on antifuse-FPGAs. These have been successfully tested with a 60 MeV proton beam: SEE and TID measurements are reported.

Drift Tubes Chambers (DTCs) are used to detect muons in the barrel of the Compact Muon Solenoid (CMS), which will collect data at the future Large Hadron Collider (LHC) of CERN. In LHC, two proton beams of 7 TeV will collide at a bunch crossing frequency of 40 MHz. Electronic devices installed on the DTCs analyse every bunch crossing, with no deadtime, and search for possible muon track segments. In particular, the Trigger Server system (TS) examines the search results from smaller sections of a DTC, rejects fakes and duplicates, and selects the best two segments overall, thus reducing the chamber output by a factor of 25.

Because of the limited accessibility of front-end electronics and the high neutron flux expected in the CMS cavern, priority in the TS design is given to partitioning and to remote control and testability. The TS architecture is a compromise between optimal partitioning, for minimising the impact of failures, and minimal trigger latency, in order to limit event data buffering. In the TS, muon track segment selection is performed in two steps: Track Sorter Slave (TSS) units (each serving 1/7 of a DTC) in the first layer feed Track Sorter Master (TSM) units (one each DTC) in the second layer. For the TSS, we designed a 0.5 micron CMOS ASIC implementing an ad-hoc fast sorting algorithm. Overall, in the CMS muon barrel about 1300 TSS ASICs will perform as a single synchronous system. The TSM does the final selection and provides access to the TSSs for monitoring and configuring.

The TSM is partitioned in several distinct blocks with partial redundant functionality, and automatic failure detection and re-configuring. For manufacturing the TSM blocks, antifuse-FPGAs, which have permanent configuration once programmed, are chosen, after their radiation tolerance has been successfully tested for use in LHC. Single Event Effect and Total Irradiation Dose measurements for the Actel A54SX antifuse-FPGAs were performed using a 60 MeV proton beam. The chips show good tolerance to high radiation doses of 10 to 70 Krads. For Single-Event-Upsets, we set an upper- limit cross-section of 2.9/10^12 cm2 (90% c.l.) per chip.

Recent Progress in Field-Programmable Gate Arrays.
by
Peter Alfke, Xilinx, Inc.

Abstract

Some progress is evolutionary, some is revolutionary.
Evolutionary progress is based on improved semiconductor technology, architectural enhancements and more efficient design tools. Over the past 15 years, Xilinx has introduced many FPGA families; only the latest ones are recommended for new designs.
Recent evolutionary improvements are better routing, better clock distribution, better clock management, and faster arithmetic, including fast multipliers.
Recent revolutionary improvements are distributed shift registers, fully synchronous dual-port BlockRAMs, and multi-standard board interfaces. A controlled-output impedance option improves board-level signal integrity and eliminates many external termination resistors. Source-synchronous design eliminates clock skew by routing clock and data together, while bit-serial I/O is self-clocking and can run at up to 3.125 Gigabits/sec ( 2.5 Gbps data), available early 2002. On-chip soft and hard microprocessors expand the range of FPGA capabilities.
This paper gives tips for achieving high performance, signal integrity, and radiation hardened designs, and it closes with a list of valuable URLs and an outlook at FPGA capabilities four years in the future.

Authors :
G.Mazza [INFNTo], M.Idzik[INFNTo], A.Rivetti[UniTo], F.Rotondo[INFNTo]

Institutes :
INFN sezione di Torino, Italy
Universita` di Torino, Italy

G.Mazza
Lab. di Elettronica, Sez. Torino
Via P. Giuria 1
10125 Torino - Italy
( +39 011-6707380
Fax +39 011-6699579
E-mail mazza@to.infn.it

New building blocks have been developed for the electronic readout of the ALICE Silicon Drift Detector. Those blocks include a 10 bit A/D converter with a reduced input capacitance, an 8 bit D/A converter based on the current mirror scheme, a voltage regulator and biasing schemes.
The blocks will be used in the PASCAL chip to improve the performances of the existing prototype and will be the building blocks for the SDD Detector Control System ASIC.
The circuits have been developed in a commercial CMOS 0.25 um technology using radiation tolerant layout techniques.

The front-end prototypes for the electronic readout of the ALICE experiment Silicon Drift Detector have been designed and succesfully tested. Nevertheless, a number of system requirements as minimize dead time, avoid external biasing and develop the Detector Control System have to be addressed. At this purpose, new building blocks have been developed. These blocks include a 10 bit A/D converter, an 8 bit D/A converter based on the current mirror scheme, a voltage regulator and biasing schemes. The A/D converter is based on the successive approximation principle. In order to reduce the input capacitance, the internal DAC has been splitted into a 5 bit main DAC and a 5 bit sub DAC. This arrangement makes possible to reduce the input capacitance of a factor of 8 compared to the previous version. The D/A converter is based on a matrix of 256 current mirrors. This technique relaxes the matching requirements and therefore improves DNL and INL. A transimpedance amplifier has been designed in order to convert the output current into a voltage. The voltage regulator and bias circuits will be integrated in the final front-end ASIC ( named PASCAL ) in order to have no external analog signals in the front-end board. Those components will be also the building blocks for the Detector Control System ASIC which will be located on both ends of the SDD ladder. The circuits have been developed in a commercial CMOS 0.25 um technology using radiation tolerant layout techniques.

P.K.Skorobogatov, A.Y.Nikiforov

Specialized Electronic Systems,
Kashirskoe shosse, 31,
115409, Moscow,
Russia pkskor@spels.ru

Temperature dependence of p-n junction radiation-induced charge collection under 1.06 and 0.53 micrometer focused laser beams was investigated in the temperature range from 22 to 110 C using experiments and numerical simulation. It was shown that in the case of 0.53 micrometer laser irradiation the temperature practically does not affect the collected charge. In the case of 1.06 micrometer laser irradiation the theory and experiments have shown the essential growth (from 2 to 3 times) of collected charge with temperature. The result obtained must be taken into account in device SEE selection for LHC electronic.

The high radiation environment of the LHC experiments requires the electronics to withstand single event effects (SEE). The procedure for estimating of integrated circuits SEE vulnerability based on particle accelerators testing is very expensive.

The focused laser sources may be used for SEE investigation and estimation [1,2]. Laser simulation of SEE is based on the focused laser beam capability to induce local ionization of IC structures. A wide range of particle linear energy transfer (LET) and penetration depths may be simulated varying the laser beam spot diameter and wavelength. The temperature dependence of the laser absorption coefficient in semiconductor affects the equivalent LET and must be accounted for when devices are tested at temperature range [3].

In order to estimate the influence of temperature on SEE laser testing parameters we have analyzed the temperature dependence of charge collected by test structure p-n junction. The experiments were performed using the original "PICO-2E" pulsed solid-state laser simulator in basic (1.06 micrometer) and frequency-double (0.53 micrometer) modes with laser spot diameter of 5 micrometers. The numerical simulations were performed using the original "DIODE-2D" 2D software simulator.

The investigated test structure was manufactured in a conventional 2 micrometer bulk CMOS process and includes well-substrate p-n junction. The measurements of p-n junction collected charge were performed in the temperature range from 22 to 110 ?C for two laser beam spot positions: within the n-well and out of junction area. It was shown that in the case of 0.53 micrometer laser irradiation the temperature practically does not affect the collected charge because of slight laser absorption coefficient temperature dependence in this range. The theoretically predicted variations of collected charge do not exceed 10% and may be explained by carrier lifetime and mobility temperature dependences. In the case of 1.06 micrometer laser irradiation the theory and experiment have shown the essential growth of collected charge with temperature. It is corresponds with strong laser absorption coefficient temperature dependence for photon energy near the bandgap. The theoretical prediction gives the approximately doubling of collected charge in the range from 22 to 110 C. The experimental results show that SEE sensitivity increases at least three times in this temperature range. The difference between measured and simulated results may be explained by uncertainties of laser absorption coefficient temperature dependence near the edge of silicon fundamental band-to-band absorption zone. The results obtained prove that the temperature dependence of the laser absorption coefficient in semiconductor affects the equivalent LET and must be taken into account in device SEE selection for LHC electronic.

P.K.Skorobogatov, A.S.Artamonov, B.A.Ahabaev

Specialized Electronic Systems, Kashirskoe shosse, 31, 115409, Moscow,
Russia pkskor@spels.ru

The dependence of p-i-n diode ionizing current amplitude vs 1.06 micrometer pulsed laser irradiation intensity is investigated. It is shown that analyzed dependence becomes nonlinear beginning with relatively low laser intensities near 10 W/cm2. This effect is connected with the modulation of pi-n diode intrinsic region by laser irradiation. As a result the distribution of electric field becomes non-uniform that leads to decrease of excess carriers collection. The ionizing current pulse form becomes more prolonged and does not repeat the laser pulse waveform. It is necessary to take into account when p-i-n diode is used as a laser intensity dosimeter.

Pulsed laser sources are widely used for dose rate effects simulation in IC's. The Nd:YAG laser with 1.06 micrometer wavelength is near ideal for silicon devices, with a penetration depth near 700 micrometers. The measurements of pulsed laser irradiation intensity and waveform monitoring may be provided with p-i-n diode. High electric field in its intrinsic region provides the full and fast excess carriers collection. As a result the ionizing current pulse waveform repeats the laser pulse within the accuracy of several nanoseconds.

Possible nonlinear ionization effects may disturb the behavior of p-i-n diode at high laser intensities. To investigate the p-i-n diode possibilities at high laser intensities the original software simulator "DIODE-2D" and the pulsed laser simulator with 1.06 micrometer wavelength were used. The typical p-i-n diode with 380 micrometers intrinsic region width under 300 V reverse bias was investigated. The simulation of p-i-n diode structure have shown that linear dependence between laser intensity and ionizing current is valid only at relatively low intensities up to 10 W/cm2 under 11 ns laser pulse irradiation. The ionization distribution nonuniformity connected with laser radiation attenuation does not affect the dependence because of relatively low excess carrier density to sufficiently change the absorption coefficient. In the field of high laser intensities this dependence becomes non-linear and ionizing current increases more slowly than laser intensity. The numerical results were confirmed by experimental measurement of pi-n diode ionizing reaction in a wide range of laser intensities. The pulsed laser simulator "RADON-5E" with 1.06 micrometer wavelength and 11 ns pulse width was used in the experiments as a radiation source [1]. The laser pulse maximum intensity was varied from 0.3 up to 2ú103 W/cm2 with laser spot size covering the entire chip. It provides in silicon the equivalent dose rates up to 109rad(Si)/s

As in the case of gamma irradiation [2], the reason of non-linearity is connected with the modulation of p-i-n diode intrinsic region by excess carriers. Because of low level of initial carriers concentration the modulation takes place at relatively low laser intensities.

As a result of modulation the distribution of electric field in the intrinsic region becomes non-uniform that leads to decrease of excess carriers collection. The behavior of p-i-n diode becomes similar to that of ordinary p-n junction with prompt and delayed components of ionizing current. The prompt component repeats the dose rate waveform. The delayed component is connected with the excess carriers collection from regions with low electric fields. As a result the ionizing current pulse form becomes more prolonged and dose not repeat the laser pulse waveform. The non-linear character of behavior and prolonged reaction must be taken into account when p-i-n diode is used as a laser intensity dosimeter in LHC experiment.

L. Baksay, P. Raics, Zs. Szabó, L. Molnár, G. Pszota
Institute of Experimental Physics, Debrecen University, Debrecen, Hungary

A. Fenyvesi, J. Molnár,
Institute of Nuclear Research (ATOMKI), Debrecen, Hungary

Gy. L. Bencze
Institute of Particle and Nuclear Physics, Budapest, Hungary
CERN, Geneva, Switzerland

L. Brunel
Institute of Experimental Physics, Debrecen University, Debrecen, Hungary
CERN, Geneva, Switzerland

D. Novak
Royal Institute of Technology, Stockholm, Sweden

Abstract

Components (LED light sources, LED driver and controller electronics, lens and video-sensor) of the barrel muon position monitoring system of the LHC CMS experiment have been irradiated with p(17.5 MeV)+Be neutrons. The tests were performed at the MGC-20E cyclotron of ATOMKI (Debrecen, Hungary). The neutron fluences delivered to the components were 2.6E+12 n/cm2 and 8.0E+13 n/cm2 (the expected values for the Barrel Muon and ME1/1 chambers, respectively). Changes of the electrical and optical characteristics were investigated.

This work was supported by the Hungarian National Research Fund (OTKA). Contract Nos.: T026184 and T026178.

Summary

Performance of the muon detecting system of the CMS detector of the Large Hadron Collider (LHC) is affected by the position and orientation of the individual chambers. In the case of the barrel muon detectors, their alignment will be controlled on the basis of the information that is provided by the position monitoring system. This system will consist of LED light sources, LED driver and controller electronics, optical lenses and video-sensors. They will have to work in a radiation environment, where the highest expected flux of the neutron component is about 1.0E+03 n/cm2/sec, and the estimated time of operation is 5.0E+10 sec. The total expected neutron flux is 2.6E+12 n/cm2 and 8.0E+13 n/cm2 for the Barrel Muon and ME1/1 chambers, respectively. Radiation damage induced by neutrons can alter electrical and optical characteristics of the components and thus the accuracy of the whole barrel muon position monitoring system.

Neutron radiation hardness tests of the components to be used in the Barrel Muon Alignment System were carried out using the broad-spectrum p(17.5 MeV)+Be neutron source ( 0 < En < 18 MeV, < En> = 3.7 MeV) of ATOMKI (Debrecen, Hungary).

Low current high intensity point-like LED light sources emitting at 660 nm (Type: FH1011, Stanley Electric Co. Ltd.) were irradiated up to 2.6E+12 n/cm2. Three modes of operation were studied: a) voltage on permanently, b) voltage off permanently and c) voltage on for 1 sec and off for 19 sec. For all of these modes of operation, the light yield decreased almost linearly as a function of the neutron fluency and approximately 50 % decrease was observed at the end of the irradiation. No other change in the electrical and spectral characteristics was measurable.

LED current driver and controller electronics with Microchip PIC16F84 processors were irradiated up to 8.0E+13 n/cm2. Some 20 % loss of the output currents of the LED controllers was observed at the end of the irradiation. The degradation of the current drivers was negligible below 1.0E+11 n/cm2 (the expected fluency at the position of operation of the device). Two processors were studied. Both damaged only after delivering ~ 2.0E+13 n/cm2 neutron fluency to them as the dramatically increased current consumption of the electronics indicated.

Plano-convex single lenses were irradiated up to 8.0E+13 n/cm2. They were made of BK7 glass without coating and their diameter was 10 mm. No measurable change of the spectral transmission and the refraction (focal length) was observed.

VM5402 video cameras with VV5402 CMOS sensor device (VLSI Vision Ltd.)were irradiated up to 2.8E+12 n/cm2. The radiation damage of the sensor resulted in the altered nearly Gaussian distribution of the light sensitivity of the individual pixels in all modes of operation. The mean values decreased while the sigma values increased in all three modes ( a) voltage on permanently, b) voltage off permanently and c) voltage on for 1 sec and off for 19 sec). Apart from the general sensitivity loss, the spectral sensitivity of the sensor did not change.

Leonid Efimov Efimov@sunhe.jinr.ru [1],
Vito Lenti Vito.Lenti@cern.ch [2]
Orlando Villalobos-Baillie orlandov@mail.cern.ch [3]

for the ALICE Collaboration

Abstract

The design details and test results of a prototype Mutiplicity Discriminator (MD) for the ALICE L0 Trigger electronics are presented. The MD design is aimed at the earliest trigger decision founded on a fast multiplicity signal cut, in both options for the ALICE centrality detector: Micro Channel Plates or Cherenkov counters. The MD accepts detector signals with an amplitude range of plus-minus 2.5 V, base duration of 1.8 ns and rise time of 300-400 ps. The digitally controlled threshold settings give an accuracy better than 0.4% at the maximum amplitude of the accepted pulses. The MD internal latency of 15 ns allows for a decision every LHC bunch crossing period, even for the 40 MHz of p-p collisions.

A functional scheme and other considerations for the Prototype Multiplicity Discriminator (MD), as an element of ALICE L0 Trigger Front-End Electronics (FEE), are given for the proposed MCP-based detector option. The MD has to produce a Pre-Trigger on Multiplicity by cut of a fast linear sum of 8 signals from pads belonging to an MCP disc sector. This is foreseen within every FEE card according to programmable threshold codes delivered by a Source Interface Unit through the ALICE Detector Data Link. The prototype MD schematics and implementation are described in details around a functional scheme and a schematic view of the input analog section. The approach used in the design was to implement a leading edge discriminator by a proper combination of an ultra-fast voltage comparators and a digital-to-analog converter (DAC) from Analog Devices. The shaper, built on components of Motorola MECL 10KH logic series, provides the output signal with a correct form, duration and 16 mA for 50 Ohm load. The prototype MD board is mounted in a double-width NIM module to support conventional test facilities.   The correlation between MD preset and real (effective) thresholds has been studied in order to evaluate the MD sensitivity to very fast and low-amplitude detector signals. Some results of such measurements, using a fast programmable  pulse generator, are shown as the effective voltage threshold versus the DAC threshold values. Next calculation of the equivalent electric charge, carried by these pulses, gave the rough estimates of the MD sensitivity as a minimum of over DAC threshold pulse charge needed to trigger the scheme. An estimate of a Prototype MD input capacity was obtained also. The first experimental test of the prototype MD was performed at CERN PS/T10 area with muon beams of 7.5 GeV/c.
The aim of this experiment was two fold:
a) to test the timing properties of the prototype MD;
b) to simulate a study of multiplicity/centrality versus the MD threshold.
Results from the MD, used instead of a specialized fast timing discriminator for time-of-flight measurements, are presented with a distribution of events versus the time-to-digital converter channels. A resolution of about 120 ps should be taken as a good one because the MD is not optimized for timing applications. In conclusions the main achievement is defined as a prototype amplitude discriminator, for the ALICE L0 multiplicity Trigger, has been designed, elaborated and tested to stand short nanosecond signals coming from the ALICE T0/Centrality detector on Micro Channel Plates base. Commercially available, inexpensive and fast components have been used to implement the prototype MD. It features an input signal range from 0 to plus-minus 2.5 V, a programmable threshold control with 8 bit resolution, and an output signal latency of 15 ns. The minimum input signal charge, needed to trigger the scheme over the DAC threshold, has been found in about 0.26 pC. While applying the MD for timing in MIPs time-of-flight measurements, a resolution of about 120 ps has been obtained. The MD was also tested by studying the response to real MCP signals as a function of the MD threshold.

Giovanni Cervelli
Alessandro Marchioro, Alessandro.Marchioro@cern.ch
Paulo Moreira, pmoreira@sunvlsi.cern.ch
Francois Vasey
CERN, EP Division, CH 1211 Geneva 23, Switzerland

A 3-way Laser Driver ASIC has been implemented in deep-submicron CMOS technology, according to the CMS Tracker design and rad-tolerance requirements. While being optimised for analogue operation, the full-custom IC is also compatible with LVDS digital signalling. It will be deployed for analogue and digital transmission in the 50.000 fibre link of the Tracker. A combination of linearization methods allows achieving good analogue performance (8-bit equivalent dynamic range, over 100MHz), while maintaining wide input common-mode range (±250mV) and limited power dissipation (30mW). The linearly amplified signals are superposed to a DC-current, pre-settable over a wide range (0-60mA). The driver gain is pre-settable via a SEU-robust serial interface. ASIC qualification and system test results are discussed in the paper.

Data connection to the CMS Tracker Front-Ends is provided by a large number of optical fibre links: 50.000 analogue for readout and ~3.000 digital for trigger, timing, and control signals distribution. The Front-End components must withstand the harsh radiation environment of the Tracker, over the planned detector lifetime of 10 years. The baseline technology for ASIC developments in the Tracker is a 0.25µm CMOS, 3-metals, commercial technology (5nm oxide thickness). The intrinsic radiation tolerance of this technology is increased to the required levels, by using an appropriately extended design-rule set. A new Laser Driver has been implemented in this technology, matching the Tracker modularity and functionality requirements.

The IC modularity is 3-channels per chip. Each individual channel converts a differential input voltage into a single-ended output current superimposed to a pre-settable DC current (0-60mA). The latter allows to bias the laser diode above threshold and to track the amount of threshold-drift expected during LHC operation. Input signals are transmitted to the laser driver using 100? cable up to 30 cm long. The driver is optimised for analogue operation (good linearity, low noise), but the input voltage levels are also compatible with the digital LVDS standard (±400mV, on 100?). The channels can be individually addressed via a serial I2C interface, allowing individual power down, gain control, and pre-bias control. Robustness to Single Event Upsets is achieved by tripling the digital logic and by using a majority voting decision scheme. About 20.000 such devices will be packaged in a 5x5 mm LPCC case for ease of testing and installation in the Tracker readout and control hybrids.

The Linear Driver consists of a degenerated PMOS differential pair and a push-pull output stage. The differential pair, compared with alternative design solutions, is conceptually simple and offers good dynamic and noise performance at limited power dissipation. The required linearity is obtained with a combination of two source-degeneration methods: a parallel source-degeneration resistor, and a source-bulk cross-connection between the transistors of the differential pair. The combination of these two methods allows keeping the degeneration resistor to a value compatible with the required input common-mode range. Three switchable output stages can be activated in parallel, to provide four different selectable gains. To minimise the cross talk within a same chip, each individual channel contains its own independent bias circuit and power-down logic. The power dissipation of the Linear Driver is below 30 mW per channel and the current consumption is constant, to avoid cross talk among the ICs. The design has been implemented in the 0.25 µm CMOS technology, taking special care to isolate all parasitic conduction paths which could arise as a consequence of ionising radiation.

The ASIC qualification will be completed before the conference, except for SEU testing which is foreseen for Autumn 2001. A prototype version of the device (using the same analogue blocks and redundant functionality) has been included in the CMS Tracker System Test currently under preparation. The final device performance and functionality will be presented at the conference. The production test program and equipment is being optimized for fast execution (pass/fail) with highest possible fault coverage.

J.J. van Hunen (For the ALICE collaboration)
CERN, European Organization for Nuclear Research
CH - 1211 Geneva 23
Switzerland
Jeroen.van.Hunen@cern.ch
Office : 160-1-012
( : 41-(0)22-7679961
GSM : 41-(0)79-2014785
Fax : 41-(0)22-7679480

The Alice1LHCb front-end chip has been designed in a 0.25um CMOS commercial technology, with special design rules to obtain radiation tolerance, for the ALICE pixel and the LHCb RICH detectors. The chip has been irradiated with low energy protons and heavy ions, to determine the cross-section for Single Event Upsets, and with X-rays to evaluate the sensitivity to the Total Ionizing Dose. We report the results of those measurements. We also report preliminary results of measurements done with minimum ionising particles in a test beam at the CERN SPS.

C.Buttar, I.Dawson, A.Moraes
(University of Sheffield, UK)
Ian.Dawson@cern.ch

One of the consequences of the harsh radiation environments at LHC experiments will be induced-activation of detector systems. This has implications for operation and maintenance scenarios. We have simulated the radiation environment of the ATLAS SCT system and made first estimates on the levels of induced activation of an SCT module. This has included studying both neutron-induced and spallation-induced activation. Dose rates are also obtained and compared to other parts of the ATLAS detector where estimates have also been made.

G. M. Bilei, M. T. Brunetti (corresponding author), F. Ceccotti, B.Checcucci,V. Postolache, A. Santocchia
mariateresa.brunetti@pg.infn.it

A new circuit for the conversion of analogue electrical signals into the corresponding optical ones has been built and tested by the CMS group of Perugia. This opto-hybrid circuit will be used in the read out electronics of the inner barrel part of the CMS tracker. The opto-hybrid is a vetronite circuit equipped with one programmable laser driver chip and up to 3 laser diodes, all being radiation tolerant. The description of the circuit and its performances are reported and discussed.

The opto-hybrid circuit is employed in the analogue optical link of the CMS inner barrel and converts the analogue electrical signal coming from silicon detectors and sampled by the APV chips into the analogue optical signal to be transmitted via optical fibres. The opto-hybrid is an FR4 (vetronite) circuit with dimensions of 30 x 22 mm2. The active devices are a programmable laser driver chip and up to 3 laser diodes (output channels). The laser driver through an I2C interface biases each laser diode in its linear response region. Analogue input signals up to +/- 300 mV from the MUX connected to the APV chips modulate the bias currents. The optical fibres escaping from each laser diode carry the analogue signal, which will be converted again, out of the beam area, into an electrical signal and is finally digitised for acquisition and analysis. For test purposes the opto-hybrid has been temporarily connected to ancillary circuits for power supply and signal injection. The test set-up includes an optical receiver, which converts the optical signal into the electrical output to be read by the scope or by the spectrum analyser. A set of routines, written in Labview 5.1, allows the remote control of the instruments and the automatic execution of the electrical tests. For a preliminary validation of the opto-hybrid circuits, the measurements to be performed are gain, integral-non-linearity, signal-to-noise ratio, crosstalk and bandwidth. The gain of the optical link is defined as the ratio between the output electrical signal and the corresponding pulse injected at the opto-hybrid input and is pre-settable through the programmable laser driver up to a value of 2.5. The gain test has shown a good agreement between the measurements and the values set via the laser driver. The integral-non-linearity (INL) test gives the deviation from a linear fit of the measured output values versus an increasing input voltage. The tested opto-hybrid chips have shown an INL estimated to be less than 3%, according to the request asked for its performances. The crosstalk is the noise measured on adjacent channels when one laser chip is pulsed. This test was affected by an impedance mismatch, which will be removed in further measurements, but the low noise values found were, nevertheless, encouraging. In order to completely characterise the opto-hybrid behaviour, thermal cycles and irradiation with particles are foreseen. All these tests will guarantee the correct operation of the opto-hybrid once in the hostile environment of the LHC tunnel.

E. Chesi, A. Clark, W. Dabrowski, D. Ferrere, J. Kaplon, C. Lacasta, J. Lozano, S. Roe, R. Szczygiel, P. Weilhammer, A. Zsenei.
dabrowsk@ftj.agh.edu.pl

We present a new version of 128-channel analogue front-end chip SCT128A for readout of silicon strip detectors. Following the early prototype developed in the DMILL technology we have elaborated a design with the main goal to improve its robustness and radiation hardness. The improvements implemented in the new design are based on experience gained on the DMILL technology while developing the binary readout chip for the ATLAS Semiconductor Tracker. The architecture of the chip and critical design issues will be discussed. The performance of modules built of ATLAS baseline detectors read out by 6 SCT128A chips will be presented and discussed.

In parallel to development of the binary readout chip for the ATLAS Semiconductor Tracker we have been developing a chip with analogue readout architecture - SCT128A. Both chips have been developed in the DMILL technology and employed the same concept of a fast front-end circuit based on bipolar transistors. Analogue architecture has a number of potential advantages compared to the binary one. A feature, which is particularly important for large installations like trackers for LHC experiments, is immunity of this architecture to common noise effects. First prototype of the SCT128A chip was designed and manufactured in an early stage of stabilisation of the DMILL process. In the meantime the DMILL process has been improved and stabilised. The development of the ABCD binary readout chip helped us to understand better and quantify various aspects of the process like matching, parasitic couplings through the substrate and radiation effects. The conclusions from the work on the ABCD chip have been implemented in the new design of the SCT128A chip with a main goal to improve robustness and radiation hardness of the new chip. The SCT128A is designed to meet all basic requirements of a silicon strip tracker for LHC experiments. It comprises five basic blocks: front-end amplifiers, analogue pipeline (ADB), control logic including derandomizing FIFO, command decoder and output multiplexer. The front-end circuit is a fast transimpedance amplifier followed by an integrator, providing a semi-gaussian shaping with a peaking time of 20-25ns, and an output buffer. The peak values are sampled at 40 MHz rate and stored in the 128-cell deep analogue pipeline. Upon arrival of the trigger the analogue data from the corresponding time slot in the ADB are sampled in the buffer and sent out through the analogue multiplexer. The gain of the front-end amplifier is of about 50mV/fC. The designed peaking time for the nominal values of resistors and capacitors is 20ns. The front-end circuit is designed in such a way that it can be used with either polarity of the input signal, however the full read-out chain (NMOS switches in the analogue pipeline, output multiplexer) is optimised for the p-side strips. The dynamic range of the amplifier is designed for 12fC input which together with the gain of 50mV/fC gives the full swing at the output of the front-end in the range of 600mV. The current in the input transistor is controlled by an internal DAC and can be set within the range from 0 to 320 microA. This allows one to optimise the noise according the actual detector capacitance. The design and the performance of the chip will be presented. The basic chip performance has been evaluated in the test bench. Analogue prototype module consisting of two 6.4 cm x 6.3 cm ATLAS baseline detectors read out by SCT128A chips has been built. The chips are mounted on a ceramic hybrid connected to the sensors in the end-tap configuration. The performance of the module will be presented and discussed.

K. Gill, R. Grabit, M. Hedberg, J. Troska, F. Vasey and A. Zanet
CERN EP Division.

Corresponding Author :
karl.gill@cern.ch

Dr Jan Troska
(: +41 (0)22 767 2063
Fax: +41 (0)22 767 2800
CERN, EP Division
CH-1211 Geneva 23
Switzerland
Email: jan.troska@cern.ch

The QA programme for the environmental tests of the COTS components for the CMS Tracker Optical link system is presented. These tests will take place in the pre-production and final production phases of the project and will measure radiation resistance, component lifetime, and sensitivity to magnetic fields. The results are summarized from the extensive series of earlier prototype sample testing and the evolution of these small-scale tests to the pre-production final manufacturing tests is outlined.

Final production of the CMS Tracker optical links will begin in 2001 and continue until 2004. Approximately 40000 uni-directional analogue optical links, and ~1000 bi-directional digital optical links will be produced during this time. Full details of the two types of optical link system, including the quantities of components and their specifications, can be found on the web[1].

Both analogue and digital optical links for the CMS Tracker share the same basic components, namely 1310nm InGaAsP/InP multi-quantum-well edge-emitting lasers and InGaAs p-i-n photodiodes coupled to single-mode optical fibre. The optical fibre is in the form of buffered single-way fibre, ruggedized 12-way ribbon fibre cable, and dense 96-way multi-way ribbon cable, with MU-type single way and MT-type multi-way optical connectors used at the various optical patch panels. All of the devices listed here are commercial off-the-shelf (COTS) components.

Quality Assurance (QA) procedures have been developed in order to guarantee that the final links meet their specified performance and are produced on schedule. A full QA manual has been written and in this paper we focus on the part of the QA programme concerning environmental testing of components.

The CMS Tracker environment is characterized by the high levels of radiation, up to ~2x10^14/cm^2 fluence and 100kGy ionizing dose for the optical link components over the first 10 years of operation[2]. The particle fluence at the innermost detector modules of the Tracker is dominated by pions and photons, with energies ~100MeV, and by ~1MeV neutrons at the outermost modules. In addition the components must operate in a 4T magnetic field and at temperatures close to -10§C.

The extensive use of COTS components in the optical links means that all prototype devices have had to be thoroughly tested. The resistance to radiation and magnetic fields are not product characteristics that are normally specified or guaranteed by telecommunications manufacturers. In extensive prototype sample tests we have measured the radiation effects in all of the optical link components, for fluences and doses typical of CMS Tracker worst-case conditions[3]. The set of results will be summarized in the full paper.

Despite having restricted the final choice of candidate components to those that have passed earlier sample tests, the use of COTS means that environmental QA testing must continue into the production phase of the project. This is simply because the factors that can affect the radiation hardness of given components are not well understood in terms of their sensitivity to any changes, however slight, in the component production method. These tests are separated into 'Advance Validation' and 'Pre-production Qualification'. In the case of the lasers, p-i-n photodiodes and the optical fibres, given the large quantities required and their observed sensitivity to radiation damage, it is desirable to do the radiation tests before the final lots have been produced and delivered to CMS. These tests are therefore carried out as Advance Validation tests which means that we will carefully screen every wafer, in the case of lasers and p-i-n photodiodes, and every glass preform, in the case of optical fibres, using a number of representative samples. It is understood that this is an unusual method of component validation, necessitating a very good working relationship with the component manufacturers.

For the other components, namely the hybrids and the terminated optical cables where there are fewer devices required, or where the radiation damage is expected to be less significant, the environmental tests will be carried out as part of the more general Pre-production Qualification.

[1] CMS Tracker Optical Links www pages, http://cms-tk-opto.web.cern.ch
[2] CMS Tracker Technical Design Report.
[3] Papers in previous LEB Workshop, RADECS and SPIE Proceedings.
(1996-2001). All available at [1].

Jonathan Butterworth, jmb@hep.ucl.ac.uk
Dominic Hayes(*),Dominic.Hayes@ra.gsi.gov.uk
John Lane, jbl@hep.ucl.ac.uk
Martin Postranecky, mp@hep.ucl.ac.uk
Matthew Warren, warren@hep.ucl.ac.uk

University College London, Department of Physics and Astronomy
( * now at Radiocommunications Agency, London )

Martin Postranecky |
( : [00-44]-(0)20-7679 3453
( : [00-44]-(0)20-7679 2000
Fax: [00-44]-(0)20-7679 7145

The design, functionality, description of hardware and firmware and preliminary results of the ROD ( Read Out Driver ) System Tests of the the TIM ( TTC Interface Module ) are described.
The TIM is the standard SCT and PIXEL detector interface module to the ATLAS Level-1 Trigger, using the LHC-standard TTC ( Timing, Trigger and Control ) system.
TIM has been designed and built during the year 2000 and two prototypes have been used since. More modules are being built this year to allow for more tests of the ROD system at different sites around the world.

The TIM ( TTC Interface Module ) has been designed to provide the interface between the ATLAS Level-1 Trigger and the SCT and PIXEL off-detector electronics.
There will be one TIM module in each of the 9U-sized off-detector ROD ( Read Out Driver ) crates, distributing the timing, trigger and control signals to all the ROD modules in each crate via a custom-designed J3 backplane and BOC ( Back Of Crate ) modules.
Each TIM receives the TTC ( Timing, Trigger and Control ) information in optical form from the LHC-standard TTC distribution system, using the standard TTCrx receiver and decoder chip to provide electrical outputs.
Each TIM receives in turn the ROD BUSY signals from each ROD in the crate and transmits a masked-OR Busy signal to the Level-1 Trigger via a ROD Busy Module.
Two prototype TIM modules have been manufactured last year and have been extensively tested since that time at UCL. One module has been in use in the ROD System Tests at Cambridge from May 2001. Following these tests, further TIM modules are being built to allow for further ROD System and Front End Module testing at various sites around the world.
The TIM has been designed as a 9U multilayer PCB with a standard VME slave interface, with all registers and configuration, control and monitoring accessible to the local crate processor. All the major logic elements of the TIM module are contained on ten large scale PLDs ( Programmable Logic Devices ), allowing for possible future design changes by firmware modification.
Each TIM is also capable of fully stand-alone operation, generating all the TTC-type signals under the control of the local processor. Each TIM can also act as a 'master' to synchronise a number of 'slave' TIM modules to allow for a stand-alone operation of a system consisting of more than one ROD crate.
As well as being the 'standard' TTC Interface Module for the SCT off-detector electronics, TIMs will also be provided to the PIXEL detector community, and possibly other detectors, to provide them with the TTC interface.

Z. Guzik, R. Jacobsson and B. Jost
Richard.Jacobsson@cern.ch

To be presented by R. Jacobsson

In this paper we describe the LHCb Timing and Fast Control (TFC) system. It is different from that of the other LHC experiments in that it has to support two levels of high-rate triggers. Furthermore, emphasis has been put on partitioning and on locating the TFC mastership in one type of module: the Readout Supervisor. The Readout Supervisor handles all timing, trigger, and control command distribution. It generates auto-triggers as well as control the trigger rates.
Partitioning is handled by a programmable patch panel/switch introduced in the TTC distribution network between a pool of Readout Supervisors and the Front-End electronics.

The LHCb Timing and Fast Control (TFC) system is in the prototyping phase. Although the backbone of the timing, trigger and control distribution network is based on the CERN RD12 system (TTC), several components are unique to the LHCb experiment due to the fact that the readout system is different from that of the other experiments in several respects. Firstly, the LHCb TFC system has to handle two levels of high-rate triggers: a Level 0 (L0) trigger with an accept rate of maximum 1.1 MHz and a Level 1 (L1) trigger with an accept rate of maximum 60 kHz. Secondly the TFC architecture focuses on partitioning. A partition is in LHCb defined as a configurable ensemble of parts of a sub-detector, an entire sub-detector or a combination of sub-detectors that can be run in parallel, independently and with a different timing, trigger and control configuration than any other partition. Furthermore, the aim has been to locate the entire TFC mastership of a partition in a single module: the Readout Supervisor (RS). The idea is to have a pool of such Readout Supervisors, in which one is interfaced to the two central trigger decision units and is used for physics data taking. The others are fully configurable masters for testing, debugging and calibrating any partition stand-alone.

The Readout Supervisors receive the LHC bunch clock via the LHC machine interface. The RS used for physics data taking also receives the L0 and L1 triggers from the central L0 and L1 decision units. One task of the Readout Supervisor is to distribute these, as well as internally generated triggers and various synchronous control commands, to the Front-End electronics via the TTC network. The L0 decisions are transmitted on channel A of the TTC system, and the L1 decision as well control commands share channel B and are transmitted as short broadcasts. The six user-definable bits of the short broadcasts allow qualifying the L1 triggers and encoding different types of control commands. The RS also acts as a trigger rate controller by converting positive trigger decisions to negative whenever data congestion occurs in the system. Fast buffers such as in the L0 Front-End electronics cannot feed back overflow signals and their occupancies are therefore emulated in the RS. Slower parts of the system signal congestion via hardware.

The partitioning is implemented by introducing a programmable patch panel/switch in the TTC distribution network between a pool of Readout Supervisors and the Front-End electronics. The switch can be configured to define independent distribution networks between the Readout Supervisors and sets of sub-detector components (partitions). The Readout Supervisors can thus trigger and control different partitions independently. In order to feed back the overflow signals from different sub-detector components to the appropriate RS, a second configurable "OR switch" has been devised. It performs an OR of the signals coming from components belonging to the same partition.

The on-detector electronics of the ALICE silicon pixel detector (nearly 10 million pixels) consists of 1,200 readout chips, bump-bonded to silicon sensors and mounted on the front-end bus, and of 120 control (PILOT) chips, mounted on a MCM together with opto- electronic transceivers. The radiation environment in the pixel detector requires radiation tolerant components. The front-end chips are all ASICs designed in a commercial 0.25 micron CMOS technology using radiation hardening layout techniques. An 800 Mbit/s Glink- compatible serializer and laser diode driver, also designed in the same 0.25 micron process, is used to transmit data over an optical fibre to the control room where the actual data processing und event building are performed. We describe the system and report on the status of the PILOT system.

Summary

The on-detector electronics of the ALICE silicon pixel detector (nearly 10 million pixels) includes 1,200 front-end ASICs, bump-bonded to silicon sensor ladders. Two ladders (5 pixel chips each), mounted on a front-end bus, constitute a half-stave. The complete detector consists of 120 half-staves on two layers. The timing,  control and readout of each half-stave are done by a PILOT ASIC, mounted on a MCM together with opto- electronic transceivers. The MCM is wire-bonded to the bus and is connected to patch-panels, at about 1m distance, with a copper flex (power supplies) and three optical fibres. The fibres carry, respectively: (a) the incoming 40MHz clock, (b) the incoming trigger and configuration data, (c) the outgoing status and readout data.

The on-detector chips have been designed in a commercial 0.25 micron CMOS technology using radiation hardening layout techniques. This allows to achieve, and in fact considerbly exceed, the radiation tolerance requirement for the ALICE pixel detector, where the expected total ionisation dose is around 2kGy over 10 years.

The pixel detector must comply with severe space and material budget constraints. The front-end bus is an aluminium/polyimide multilayer. The MCM dimensions should not exceed 1.2mm thickness and 50mm length, with less than 10mm width available for the components.

The PILOT ASIC initiates the readout of the pixel chips, converts data levels from GTL to CMOS, reformats the data stream and forwards the data to a serialiser ASIC (named GOL) that includes a driver for the laser diode transmitter. Data are sent out on a fibre at 800Mb/s rate using the G-link protocol. The PILOT converts the incoming clock, serial trigger and serial JTAG signals into control signals for the pixel chips. The PILOT forwards the configuration data to the pixel chips, to the GOL, and to an auxiliary analog chip containing DACs that generate reference voltage and current levels.

The back-end electronics in the control room consists of 20 VME based router cards, each equipped with 6 pixel data converter daughter cards. Each data converter daughter card receives data from a half stave, performs zero suppression, reformats the data and stores it into an event memory. The router cards multiplex data from its 6 data converter daughter cards into one sub event block, reformat the data stream and send the data via the detector data link to the ALICE data acquisition. The trigger and configuration data are sent via the router card to the data converter card where they are serialized and sent to the PILOT via the optical fibre link.

This paper describes the pixel detector system and reports on the status of development and test of the PILOT.

CERN
CH-1211 Geneva 23
Bat 14-4-006
( : +4122 767 6152
Fax: +4122 767 9425
Email: Danielle.Moraes@cern.ch

Pos-Graduacao
Instituto de Fisica - UFRJ
Cidade Universitaria - CP 68528
21945-970 Rio de Janeiro - RJ, Brasil
( : +5521 562-7463
Fax: +5521 562-7368
Email: danielle@if.ufrj.br

D. Moraes(1,2), F. Anghinolfi(1), W. Bonivento(1), P. Jarron(1),
W. Riegler(1), B. Schimdt(1), F. Vinci dos Santos(1),

(1) CERN, CH-1211 Geneva 23, Switzerland
(2) Univ. Federal do Rio de Janeiro, C.P. 68528, BR-21945-970 Rio de Janeiro, Brazil

We present recent results of an ASD frontend development in 0.25um CMOS for the LHCb muon chambers. Characteristic features of the chip are a peaking time of 10ns, input resistance of <10 Ohm, a noise of 500+39e-/pF and a fast tail cancellation shaper. We present results of a 14 channel amplifier+discriminator submission showing crosstalk and parameter variations. A negative polarity preamp version suitable for wire readout and results from a fast 2x pole/zero tail cancellation shaper are also shown.

First results of a fast detector frontend prototype designed in 0.25um CMOS were presented at the last LEB meeting [1]. Here we want to present the progress on this project which is aimed at the production of an ASD chip for the 120k channels of the LHCb muon system. In addition to the ASD chip the frontend board will house a logic chip, also designed in 0.25um CMOS, that will perform simple logic functions. The advantage of an analog+digital frontend in deep submicron technology are radiation hardness, low cost and low power dissipation.

The muon system detectors are wire chambers with cathode and anode readout, an average primary ionization of 100 electrons and a gas gain of 10^5. The optimum time resolution of the chambers requires a peaking time of 10ns. The high rates of up to 1MHz/channel require an ion tail cancellation as well as a baseline restoration circuit. The detector capacitance ranges from 20 to 250pF, the input resistance is required to be <50 Ohm.

At the last LEB we reported the results from a positive polarity preamp+discriminator chip. In this paper we present the following:

1) Results from a submission with 14 identical positive polarity amplifier+discriminator channels showing crosstalk <1%. Channel to channel variations of different parameters are discussed as well.
2) Results from a negative polarity amplifier submission.
3) Results from an amplifier+shaper submission. The shaper contains a 2x pole/zero network optimized for an ion tail of t0=1.5ns.

The unit is designed to control and monitor the front end electronics, and to collect and ship data onto the Detector Data Link (optical fibre). Handling and distribution of the central trigger is also done, with the use of the onboard mounted TTCrx chip. For the prototype of the RCU the Altera EP20K400 FPGA has been used for application specific system integration.

The TPC Readout Controller Unit (RCU) is responsible for controlling the readout of the TPC, and initialising and monitoring the Front-End Cards (FECs). In total 180 RCUs will have 4500 FECs connected, with a maximum of 32 cards connected to each RCU.

On the FECs the amplifying, shaping, digitizing, processing and buffering of the TPC signals is done. A custom integrated circuit, the ALTRO (ALICE TPC Read Out), is dedicated to the processing of the digitized data. This chip is initialised and controlled directly from the RCU.

The communication between the Readout Controller Unit (RCU) and the ALTROs on the Front-End Cards (FECs) is implemented via a custom bus based on a shielded ribbon cable and a custom protocol.

The RCU collects the data from the FECs, assembles a subevent, compresses the data and sends the compressed, packed subevent to the Read Out Receiver Card (RORC). Shipping of data to the RORC (through optical fibre), is done via a custom interface named the Detector Data Link (DDL).

In addition, the RCU monitors and initialises the FECs. This supervision includes read-out of events for monitoring purposes, statistics (read out of number of datastrobes and number of triggers received), temperature variation monitoring, current measurement and power consumption monitoring for hardware fault detection. This is done via a separate slow-control bus. The initialisation of the ALTROs (including uploading of pedestal values for the digital filter responsible for tail-cancellation) is done via the main front end bus.

For the prototype of the RCU the Altera EP20K400 FPGA has been used for application specific system integration. The custom front-end bus protocol and the front-end slow control are both implemented in this FPGA.

On the RCU there will be a memory bank able to store a few full events (SRAM). The memory controller (FIFO structure) for this, is implemented in the FPGA.

A readout sequence of the TPC is initiated by a common ALICE trigger signal. This trigger is distributed to the RCU from the central trigger control. A custom Trigger Receiver Chip (TTCrx) is placed on the RCU. The interface to the TTCrx is implemented in the FPGA.

For monitoring purposes during operation a Slow Control Unit will be used. The Slow Control bus from the RCU will be connected to the central Detector Control System (DCS) of the ALICE experiment.

Several testbenches have been designed in order to test the controller unit. A first prototype of the RCU has been developed.

N. Almeida, V. Antonio, N. Cardoso, A. Correia, P. Machado, J. C. Silva, I.Teixeira, J. Varela,
LIP, Lisbon and INESC, Lisbon
joao.varela"@cern.ch

The Data Concentrator Card is a module in the CMS Electromagnetic Calorimeter Readout System responsible for data collection in a readout crate, verification of data integrity and data transfer to the central DAQ. The DCC should sustain an average data flow of 200 Mbyte/s. In the first part of the paper we summarize the physics requirements for the ECAL readout and give results on the expected data volumes obtained with the CMS detector simulation (ORCA software package). In the second part we present the module's design architecture and the adopted engineering solutions. Finally we give results on the expected performance derived from a detailed simulation of the module's hardware.

Authors
J. Troska, K. Gill, R. Grabit, M. Hedberg, F. Vasey and A. Zanet
CERN
A. Go
Department of Physics, National Central University, Taiwan
M.-L. Chu
High Energy Physics Laboratory, Institute of Physics, Academia Sinica, Taiwan

Corresponding Author
Jan Troska jan.troska@cern.ch
( : +41 (0)22 767 2063
Fax: +41 (0)22 767 2800

CERN, EP Division
CH-1211 Geneva 23, Switzerland

Prototype analogue optohybrids have been designed and built for the CMS Tracker Outer Barrel and End Cap detectors. The total requirement for both types in CMS is 12900 that will be assembled between 2002 and 2004. Using very close to final optoelectronic and electronic components several optohybrids have been assembled and tested using standardised procedures very similar to those to be implemented during production. Analogue performance has met the specifications in all cases when operated in isolation and when inserted into the full prototype optical readout system.

The CMS Tracker optical readout system will consist of approximately 40000 uni-directional analogue optical links production of which is due to commence in 2001 and continue until 2004[1]. Within the CMS Tracker the transmitting elements of the analogue optical links will be housed on analogue optohybrids that interface directly to the silicon detector modules[2]. Either two or three laser diodes (depending upon the location within the Tracker) and the associated laser driver ASIC will be mounted on an analogue optohybrid (AOH). The total requirement of optohybrids is 4000 for the Tracker Inner Barrel and Disks, 5800 for the Tracker Outer Barrel (TOB) and 7100 for the Tracker End Caps (TEC).

The availability of very close to final optoelectronic components has allowed prototyping of an AOH design suitable for the TOB and TEC detectors. The PCB design, that has been carried out by CERN and produced in Taiwanese industry, can be used in both TOB and TEC by simple differential assembly of the connector on either the top- or bottom-side of the printed circuit board. The PCB measures 23mm by 30mm, is 0.5mm in thickness and accommodates two or three laser diodes, the laser driver ASIC and associated passive components. All components mounted on the prototype optohybrids (laser diodes, laser driver, optical and electrical connectors) are final or very close to final designs. An interface to the final cooling arrangement within the TOB and TEC has also been incorporated.

Two types of candidate laser diode from different manufacturers have been assembled onto prototype optohybrids which have then been submitted to a full test of the specifications to demonstrate that they will meet the requirements of use within the CMS Tracker optical readout system. Prototype optohybrids have been evaluated using the standard CMS Tracker test methods described previously[3,4]. The testing carried out has demonstrated the required performance in response to both static and dynamic test suites that mimic operation within the full analogue optical link system. Noise is within the system specification of 48dB and integral non-linearity within the operating range of the optical links meets the target of 1%. Dynamic measurements show that the bandwidth of the components is not degraded by placement on the optohybrid adding further weight to the validation of the optohybrid design. Measurements have been carried out at room temperature, 0øC, -10øC and -20øC and although some variations in the laser characteristics were observed these did not significantly degrade their performance in the optical readout system.

In addition to the standalone lab testing using standard procedures the analogue optohybrid prototypes were re-tested in a full optical readout system with a close to final design of the 12-way analogue receiver module. Results of these tests show that the prototype optohybrids perform well in this environment. Once validated the prototype optohybrids of TOB type will be included in the electronic system test carried out at CERN where their performance will be assessed as part of the entire electronic readout system of the CMS Tracker.

[1] The Tracker System Project Technical Design Report, CERN/LHCC 98-6, CMS TDR 5, 15 April 1998 & Addendum CERN/LHCC 2000-016, CMS TDR 5 Addendum, 1, 21 February 2000
[2] Specifications of the Optical Link System are available from URL http://cern.ch/cms-tk-opto
[3] A 4-channel parallel analogue optical link for the CMS-Tracker, F.Vasey et al., Proc. of the fourth workshop on electronics for LHC experiments, Rome, 1998, pp. 344-348
[4] Evaluation and selection of analogue optical links for the CMS tracker - methodology and application, F.Jensen et al., CMS Note 1999/074

Daniel Dzahini, for the ATLAS Liquid Argon Collaboration
Institut des Sciences Nucléaires
53 avenue des Martyrs,
38026 Grenoble Cedex France
dzahini@isn.in2p3.fr

A high speed digital optical data link has been developed for the front-end readout of the ATLAS electromagnetic calorimeter. It is based on a commercial serialiser commonly known as Glink, and a vertical cavity surface emitting laser. To be compatible with the data interface requirements, the Glink must be coupled to a radhard multiplexer that has been designed in DMILL technology to reduce the impact of neutron and gamma radiation on the link performance. This multiplexer features a very sever timing constraints related both to the Front-End Board output data and the Glink control and input signals. The full link has been successfully neutron radiation tested by means of a custom Bit ERror Tester.

The Liquid Argon Calorimeter of the ATLAS experiment at the LHC is a highly segmented particle detector with approximately 200 000 channels. The signals are digitized on the front-end board and then transmitted to data acquisition electronics situated 100m to 200m away. The front-end electronics has a high degree of multiplexing allowing the calorimeter to be read out over 1600 links each transmitting 32 bits of data at the bunch crossing frequency of 40.08 Mhz. The radiation hardness is a major consideration in the design of the link, since the emitter side will be exposed to an integrated fluence of 3*1014 n (1 MeV Si) per cm2 of the components' surface over 10 years of the LHC running.

The demonstrator link is based on an Agilent Technologies HDMP1022/1024 serialiser/deserialiser. This Glink is used in a double frame mode: the incoming 32 bit digitized data at 40.08 Mhz are multiplexed into 16 bits at 80.16 Mhz. A multiplexer ASIC has been developed in the DMILL technology. This MUX chip translates first the data from LVDS level to CMOS level then it performs the data registration and multiplexing. The 16 bit data words are loaded at the input of the HDMP1022 serialiser. The Glink chip set adds a 4 bit control field to each 16 bit data segment which results in a total link data rate of 1.6 Gb/s.

The Glink serialiser outputs drive a VCSEL that transforms the electrical signal into light pulses transmitted over a Graded Index (GRIN) 50/125 mm multimode fibre to a PIN diode located on the receiver board. For the link described in this document the VCSEL and the PIN diode are packaged together with driving and discriminating circuits as transceiver modules manufactured by Methode. The PIN diode output signals are deserialised by the GLINK HDMP1024 chip. A Programmable Logic Array (ALTERA EMP7128) is placed on the receiver board to facilitate demultiplexing. Several link sender boards were exposed to neutron flux to assess the radiation tolerance of the DMILL MUX, the Glink serialiser and the Methode transceiver. During the radiation tests, the behaviour of the link was monitored on-line. A Bit ERror Tester (BERT) coupled to a pseudo-random pattern generator was specially developed. The BERT consists in a modular tester it permits several high speed (32 bit at 40.08 Mhz) data links to be tested simultaneously. The single bit error detection is performed by comparison of sent and transmitted bit. The BERT comprises EPLD based boards plugged in a VME crate. The slow control and the error acquisition is done on-line by a Personal Computer. The radiation tolerance of the sender part of the link has been demonstrated under neutron radiation up to 1014 n cm-2. Transient data transmission errors (Single Event Upset) were observed by means of the BERT set-up but it has been shown that the contribution of the DMILL MUX to this error rate is very negligible.

H.J.Burckhart, J.Cook, B. Hallgren, F.Varela, CERN-EP

Henk Boterenbrood, NIKHEF, Amsterdam, The Netherlands

Viatcheslav Filimonov, PNPI, St.Petersburg, Russia

Dr. Helfried Burckhart
European Laboratory for Particle Physics
CERN, EP
CH-1211 Geneva 23
( : (+41) 22 767 12 54
Fax: (+41) 22 767 83 50  

Abstract:

The ATLAS Detector Control System (DCS) consists of two main components:

A distributed supervisor system, running on PCs, and the different Front-end systems. For the former the commercial SCADA package, PVSS-II, has been chosen together with the CERN Joint Controls Project, JCOP.

For the latter, a general purpose I/O concentrator called the "Embedded Local Monitor Board" (ELMB) has been developed, which is based on the CAN fieldbus. The paper describes a full vertical slice of the DCS, including the interplay between the ELMB and PVSS-II. Examples of typical control applications will be given. 

Summary:

The Detector Control System (DCS) must enable a coherent and safe operation of the ATLAS detector. It has also to provide communication with the LHC accelerator and with external services, like cooling, ventilation, electricity distribution and safety systems. Although the DCS will operate independently from the DAQ system, efficient communication between both systems must be ensured. ATLAS consists of several subdetectors that are operationally quite independent. DCS must be able to operate them in both stand-alone mode and in an integrated fashion as a homogenous experiment.

The DCS consists of two main components: the Supervisory Control And Data Acquisition (SCADA) and the Front-End (FE) systems. They will be installed in three distinct locations. The SCADA will be used in the surface control room for overall operation and in the underground electronics rooms for equipment supervision. The commercial package PVSS has been chosen as the SCADA system for the four LHC experiments in the frame of the Joint Controls Project (JCOP) at CERN. It gathers the information from the FE equipment and offers supervisory control functions such as data processing, alert handling, trending and archiving and allows for the development of applications that can be distributed over a network. This distribution facilitates the mapping of the control system onto the different subdetectors. The FE systems are the responsibility of each subdetector and they range from simple sensors and actuators up to complex computer-based devices. They will mainly reside in the experimental cavern. This imposes specific requirements such as operation in a magnetic field of 1.5 Tesla and radiation tolerance. The I/O points are distributed over the whole volume of the detector with distances of the order of 100 meters. The CAN fieldbus has been chosen for the data transmission medium due to these environmental and physical constraints. In order to standardize the FE system where possible, a general-purpose, low-cost I/O concentrator, the Embedded Local Monitor Board (ELMB), has been developed. The ELMB implements the industry standard interface CANopen, it can be embedded into the subdetector’s electronics and provides several I/O functions. More details on the ELMB and results on radiation testing are presented in another contribution to this workshop.

This paper presents the implementation of a full vertical slice of the ATLAS DCS comprising the components described above. The ELMB has been interfaced to PVSS by means of the industry standard OPC protocol. The complete readout chain will be described including the functionality of each of the building blocks. A prototype has been developed and used in different control applications for the ATLAS subdetectors, like the cooling systems of the Pixel and TileCal subdetectors. Due to the size of systems in ATLAS, such as the Muon Spectrometer using about 1200 ELMB nodes, the scalability of the fieldbus has been investigated. Recent tests accommodating many ELMB modules on a bus have been performed in order to study node and bus behavior and their management. Results on applicability and performance, presented in this paper, will lead to the design of the overall fieldbus topology in ATLAS. The operation from SCADA and the distribution of functionality over the various building blocks of the readout chain will also be discussed.  

Authors :
G.Magazzu' - INFN Sezione di Pisa
A.Marchioro, P.Moreira - CERN

A key component for monitoring environmental parameters like temperature, silicon detector leakage currents, power supply voltages and currents in the LHC detector environment is a rad-hard, low-power multi-channel A/D converter. For these applications in the CMS central tracker we have designed and developed an integrated circuit, the Detector Control Unit (DCU). The core of the DCU is an 8-channel 12-bit A/D converter controlled through a standard I2C interface. The structure and the performance of this ADC are desribed in the paper.

Silicon detectors, when exposed to the high level of radiation in the LHC experiments, are subject to a number of damaging phenomena demanding careful monitoring of their environmental conditions. In the CMS central tracker the detector leakage currents in the range of 100uA to 10mA are measured using sensing resistors and the temperature in the range of -20 deg C to +20 deg C is monitored using appropriate thermistors. The supervision of other parameters like the local supply voltages and the temperature of the hybrids housing the front-end integrated circuits is also performed. All these quantities need to be read and logged with relatively low frequency, therefore a fast conversion time is not required. A highly integrated and low-power solution is required because of the strict requirements in terms of space and power dissipation. The Detector Control Unit (DCU) has been developed to perform all the requested functions in one single integrated circuit. This ASIC consists basically of a 12-bit A/D converter that uses a single slope architecture, preceded by an 8 input analog multiplexer. 8 inputs are available to measures voltages in the range 0V to 2.5V (rail-to-rail, since the power supply voltage is 2.5V). The A/D conversion time is ~0.2ms. Two operating modes are available: in the "low input range" mode (0V to 1.5 V) the input signal is referenced to GND while in the "high input range" mode (1.0V to 2.5V) the signal is referenced to VDD. In both operating modes the measured non-linearity is less than 1 LSB with no missing codes. To achieve the rail-to-rail input compatibility the analog circuitry uses a complementary solution based on a pair of NMOS and PMOS comparators and has an automatic offset cancellation scheme. A 100pF metal-to-metal capacitor is charged from GND or discharged from VDD, according to the selected mode, using stable and temperature independent currents derived from an on-chip band-gap reference. Two temperature independent and stable current reference outputs (10uA and 20uA) are also provided to bias the external temperature sensing thermistors. A custom on-chip temperature sensor measures the temperature of the substrate housing the ASIC. The DCU is interfaced to the Tracker Control System via a standard I2C port, through which the user can start an on-chip temperature sensor acquisition, fix the A/D converter operating mode, select one of the 8 inputs, start an A/D conversion and read the conversion result. The digital part of the chip uses triple redundancy and majority voting to ensure protection against SEU effects. The DCU is designed in a commercial quarter micron technology using special layout techniques to enhance its radiation tolerance. The total chip area measures 2.0x2.0 mm2, contains 28 pins and the power consumption is less than 50mW. The circuit has been submitted to fabrication and fully characterized. Its architecture and the measured performance will be presented in the paper.

P. Chumney, S. Dasu, F. di Lodovico, M. Jaworski, J. Lackey, P. Robl, W.H.Smith
University of Wisconsin – Madison
Wesley H. Smith
University of Wisconsin Physics Department
1150 University Ave. Madison, Wisconsin 53706 USA
( : (608)262-4690,
Fax: (608)263-0800,
email: wsmith@wishep.physics.wisc.edu
http://hep.wisc.edu/wsmith/

The CMS regional calorimeter trigger system detects signatures of electrons/photons, taus, jets, and missing and total transverse energy in a deadtimeless pipelined architecture. This system contains 19 crates of custom-built electronics. Recent changes to the Calorimeter Trigger have been made to improve the efficiency and purity of jet and tau triggers. The revised algorithms, their implementation in hardware, and their performance on physics signals and backgrounds are discussed.

The CMS Regional Calorimeter Trigger receives compressed data from the calorimeter readout electronics on 1.2 GBbaud copper links, each carrying data for two HCAL or ECAL trigger towers. 19 total crates (18 for the barrel/endcap and one for both forward calorimeters) each contain seven rear mounted Receiver cards, seven front mounted Electron Isolation cards, and one front mounted Jet Summary card plugged into a custom point-to-point 160 MHz differential ECL backplane. Each crate transmits to the global calorimeter trigger processor its sum Et, missing energy vector, 4 highest-ranked isolated and non-isolated electrons, and 4 highest energy jets and 4 tau-tagged jets along with their locations.

The jet trigger uses the transverse energy sums (e.m.+had) computed in calorimeter regions (4x4 trigger towers), except in the HF region where it is the trigger tower itself. The input tower Et is coded in an 8 bit linear scale with programmable resolution. The subsequent summation tree extends to a 10 bit linear scale with overflow detection. Simulation studies showed that a scale of 10 bits with LSB = 1 GeV gives adequate jet trigger performance. The jet trigger uses a 3x3 calorimeter region sliding window technique which spans the complete (eta, phi) coverage of the CMS calorimeters seamlessly. The central region Et is required to be higher than the eight neighbour region ET values.

The jets and taus are characterized by the transverse energy Et in 3x3 calorimeter regions. The summation spans 12x12 trigger towers in barrel and endcap or 3x3 larger HF towers in the HF. The jets are labelled by (eta, phi) indexes of the central calorimeter region. For each calorimeter region a tau-veto bit is set ON if there are more than two active ECAL or HCAL towers in the 4x4 region. A jet is defined as "tau-like" if none of the 9 calorimeter region tau-veto bits are ON.

The four highest energy central and forward jets, and central taus in the calorimeter are selected. Jets and taus occurring in a calorimeter region where an electron is identified are not considered. The selection of the four highest energy central and forward jets and of the four highest energy taus provides enough flexibility for the definition of combined triggers. In addition counters of the number of jets above programmable thresholds in various eta regions are provided to give the possibility of triggering on events with a large number of low energy jets. Jets in the forward and backward HF calorimeters are sorted and counted separately.

The baseline implementation of jet clustering is based on the 160 MHz ASICs and point-to-point backplane technology developed for the CMS regional calorimeter electron/photon trigger. The entire eta-phi plane is covered by a single cluster crate that receives data from 18 Regional Calorimeter Trigger crates on parallel differential ECL links at 80 MHz and processes the data at 160 MHz. Another implementation under study incorporates the algorithm into the FPGA logic of the CMS Global Calorimeter Trigger.

Alex Madorsky
University of Florida/Physics
Museum rd & NS dr
Gainesville, FL, 32606, USA

(1-352-392-9849
fax: 352-392-8863

Development and Test of a Prototype Track-Finder for the Level-1 Trigger of the CMS Endcap Muon System

We report on the development and test of a prototype track-finding processor for the Level-1 trigger of the CMS endcap muon system. The processor links track segments identified in the cathode strip chambers of the endcap muon system into complete three-dimensional tracks, and measures the transverse momentum of the best track candidates from the sagitta induced by the magnetic bending. The algorithms are implemented using SRAM and Xilinx Virtex FPGAs, and the measured latency is 15 clocks. We also report on the design of the pre-production prototype, which achieves further latency and size reduction using state-of-the-art technology.

Development and Test of a Prototype Track-Finder for the Level-1 Trigger of the CMS Endcap Muon System

The endcap muon system of CMS consists of four stations (ME1-ME4) of CSC chambers on each end of the experiment, covering the range in pseudorapidity from 0.9 to 2.4. A single station is composed of six layers of CSC chambers, where a single layer has cathode strips aligned radially and anode wires aligned in the orthogonal direction.

The barrel muon system consists of four stations of drift tube chambers in the central region of CMS.

The purpose of the CSC Track-Finder is to link track segments from individual CSC stations into complete tracks, measure the transverse momentum from the sagitta induced by the magnetic bending, and report the best tracks to the Level-1 Global Muon Trigger. This objective is complicated by the non-uniform magnetic field in the CMS endcap and by the high background rates; consequently, the present design incorporates full three-dimensional information into the track-finding and measurement procedures. A momentum resolution of better than 25% has been designed in order to sufficiently reduce the rate of low momentum muons. A prototype of the CSC Track-Finder has been constructed, with a Sector Processor implementing the Track-Finding algorithms for a 60 degree azimuthal sector and three Sector Receivers collecting the data from the CSC chambers in that sector. The Sector Processor prototype uses 15 Xilinx Virtex FPGAs ranging from XCV50 to XCV400 to implement the track-finding algorithms. The total number of logic gates on board is about 2,200,000. The Sector Processor accepts 15 track segments from three Sector Receivers of the endcap muon system, and eight segments from the barrel muon system via a transition board in the back of the crate. The Sector Processor is pipelined with a latency of 15 clocks (375 ns).

The first prototype was completely debugged using internal 256-word deep FIFOs on the input and output. The input patterns were created using a CMS simulation, and the output of the Sector Processor was verified against a software model of the board. Random numbers were also used as input data for both the model and the prototype. In all tests, the prototype output matched the model exactly. The board was also tested with the Sector Receivers sending serialized data via the custom backplane at 280 MHz, and the result again matched expectations.

A second (pre-production) prototype of the Sector Processor will use state-of-the-art FPGAs from the Xilinx Virtex-E series. Use of these devices allows us to implement all Sector Processor logic into one FPGA (XCV1600E), saving board real estate and latency. There are also significant improvements in optical link technology that make it possible to implement the three Sector Receivers and one Sector Processor onto one 9U VME board. Therefore, instead of the 6 crates planned for the CSC Track-Finder at the time of the first prototype construction, the entire system will occupy just one crate. It will contain 12 boards, each sending output data via a custom GTLP backplane to a muon sorter located in the same crate.

Authors list :
Niels van Bakel, Jo van den Brand, Hans Verkooijen
(Free University of Amsterdam / NIKHEF Amsterdam)
Daniel Baumeister, Werner Hofmann, Karl-Tasso Knoepfle,
Sven Loechner, Michael Schmelling, Edgar Sexauer^(*),

Ulrich Trunk
(Max-Planck-Institute for Nuclear Physics, Heidelberg)
ASIC Labor Heidelberg
Schroederstrasse 90
D-69120 Heidelberg
(: +49 6221 544324
Fax: +49 6221 544345
trunk@kip.uni-heidelberg.de
http://wwwasic.kip.uni-heidelberg.de/~trunk/

Martin Feuerstack-Raible
(University of Heidelberg)
Neville Harnew, Nigel Smale
(University of Oxford)
^(*) now at Dialog Semiconductors, Kirchheim-Nabern, Germany

Beetle 1.0 and 1.1 are pipelined 128 channel front end chips for the LHCb experiment, manufactured in 0.25 mu m standard CMOS technology. The final version of this chip will be equipped with SEU resistant control circuitry and a fast front end with improved analogue performance. Three chips containing prototype components have been submitted in May 2001. Descriptions of the concepts implemented in the BeetleFE1.1, BeetleFE1.2 and BeetleSE1.0 chips are presented together with simulation- and first test results.

Beetle 1.0 and 1.1 are pipelined 128 channel front end chip for the LHCb, experiment manufactured in 0.25 mu m standard CMOS technology. The chip hast to meet the requirements of the silicon vertex detector, inner tracker, the pile-up veto trigger and the RICH in case of multi-anode photomultiplier readout. The chip can be operated in analogue as well as binary readout mode. The latest version was submitted in March 2001.

Each of the chip's 128 channels features an analogue front end consisting of a charge sensitive preamplifier, an active CR-RC pulse shaper and a buffer. Its preamplifier and shaper stages use the well known folded cascode topology, the preamplifier features an NMOS input transistor. The current front end satisfies the requirements of rise below 25 ns and a remainder of at most 30% of the maximum pulse height 25 ns after the peak for a load capacitance below 15 pF. This is sufficient for applications in the LHCb vertex detector.

Higher detector capacitances as expected for the inner tracker and robust operation also for large occupancies, however, call for a faster pulse shapes with a lower remainder after 25 ns. To study possible improvements, four additional front end prototypes were developed and implemented on the BeetleFE1.1 and Beetle FE1.2 chips.

The control circuit of the Beetle heavily relies on registers, either to store configuration data, or to implement state machines. To overcome SEU failures in these registers, a parity based error correction schema (ECC) is implemented for static registers on the BeetleSE1.0, while the registers in its state machines use triple redundancy to suppress SEU failures.

The components on these chips will be included in the pipelined readout chip Beetle1.2 which is intended for submission in 2002. The circuits on the BeetleFE1.1, BeetleFE1.2 and BeetleSE1.0 chips submitted in May 2001 are presented together with simulation- and test results and descriptions of the concepts implemented on these chips.

Authors :
E.Carrone , M. Davenport , G. De Cataldo†, A. Franco†, P.Martinengo , E. Nappi†
Presenter :
Enzo Carrone for the ALICE collaboration - CERN CH1211, Geneva 23, Switzerland
Contact :
Enzo Carrone
Enzo.Carrone@cern.ch
CERN 1-R-035 CH1211, Geneva 23 - Switzerland
( +41-22-76 71935

The HMPID (High Momentum Particle Identification Detector) detector is one of the ALICE (A Large Ion Collider Experiment) subdetectors planned to take data at LHC at the beginning of 2005. Since ALICE will be located underground, the HMPID will be remotely controlled by a Detector Control System (DCS), which consists of three layers: physical, control and supervisory.

The first one includes sensors, actuators and the detector, the second one deals with the device where the control programs run, and finally the supervisory layer contains the Machine-Man Interface (MMI), which lets the user run the DCS.

In this paper we will present the DCS design, accomplished via GRAFCET (GRAphe Fonctionel de Commande Etape/Transition), a tool which represents the DCS as a finite state machine, and then translated into code readable by the PLC (Instruction List) via an ad hoc algorithm. The SCADA DCS is based on PVSS, a commercial software. The results achieved so far show that this way of proceeding is effective and time saving, since every step of the work is autonomous, making simpler the debugging and updating phases.

Politecnico di Bari, Italy and CERN, Switzerland
CERN, Switzerland
INFN Bari, Italy

E. Hazen, J. Rohlf, S. Wu - Boston University
hazen@joule.bu.edu
rohlf@bu.edu
wusx@bu.edu

Eric Hazen
Boston University Physics Dept
( 617/353-6120
Fax 617/353-3331
http://ohm.bu.edu/~hazen
Schedule at http://calendar.yahoo.com/public/eshazen/

The CMS HCAL data concentrator must combine data from about 600 front-end channels, with real-time synchronization and error-checking and an average throughput of 200 Mbytes/s. A modular implementation is described which is based on industry and CERN standards: PCI bus, PCI-MIP and PMC carrier boards, S-Link and LVDS serial links. A prototype has been built and tested using modular components. PC-MIP triple LVDS receivers collect data from front-end boards. A PMC logic board performs application-specific processing. A VME motherboard provides a standard platform and transparent access to monitoring and error registers. Test results and implementation details are described.

The CMS HCAL trigger/DAQ system consists of 9U VME crates with up to 18 trigger/readout modules, one data concentrator, and one readout controller. The CMS HCAL Trigger/Readout (HTR) module is a 9U VME module equipped with optical receivers, TTCrx circuitry, outputs on serial LVDS (Channel Link) and a custom mezzanine card. The optical inputs receive data from the HCAL front-end electronics, with one charge sample per bunch crossing. The CMS HCAL is a trigger detector, thus the HTR includes two data paths: the trigger path, which assigns Front-End data to a bunch crossing and sends them to the CMS regional trigger, and the DAQ path where the FE-data are pipelined, triggered and sent to the Data Concentrator Card.

The Data Concentrator Card is composed of a VME motherboard, six LVDS link receiver boards and a PMC-type logic board. The motherboard is a VME64x 9Ux400mm single-lot module. The motherboard supports VME access up to A64/D32, and contains three bridged PCI busses. Six PC-MIP mezzanine sites are arranged in groups of three on two 33MHz 32-bit PCI busses. A third 33MHz 64-bit PCI bus is bridged to the VME bus using a Tundra Universe II VME-to-PCI bridge. A single large logic mezzanine board has access to all three PCI busses for high-speed application-specific processing, and an additional standard PMC site is available. A local control FPGA on the motherboard provides access to on-board flash configuration memory, a programmable multi-frequency clock generator, and JTAG. The LVDS link receiver boards use Channel Link technology from National Semiconductor. Each board contains three links, which operate at a speed of 33MHz x 32-bits. On-board logic performs automatic event building, protocol checking, event number checking and bit error correction. A PCI slave interface provides single- and burst-read access to the data stream, plus numerous monitoring registers. On-board buffering for 128Kx32 words is provided for each link, with a fast "overflow warning" output.

The logic mezzanine board contains the core data concentrator logic. An on-board TTCrx stores level 1 accepts into an on-board FIFO. Two PCI interfaces read event fragments from up to 18 input links. A core FPGA with a large buffer memory builds events, performs extensive error-checking and monitoring, and outputs data to several destinations. The primary output is via S-Link to the DAQ. Additional outputs target the "trigger DAQ" stream for monitoring trigger performance, and a VME-accessible spy stream for monitoring.

A prototype of the entire system has been built. The HTR prototype uses 4 G-Link receivers running at 800 Mb/s. The DCC prototype uses three separate FPGAs for the PCI interfaces and a Xilinx XC2V1000 FPGA for the core processing logic. A 2Mx32 DDRSDRAM provides a memory buffer with 800Mbytes/sec transfer rate capability. A custom FE-emulator card is used to demonstrate the correct behavior of the system. Test results of the prototype are presented. Near term applications for this hardware include a high-rate radioactive source test at Fermilab in summer 2001 and a beam test at CERN in 2002 with several hundred front-end channels.

Gabriele_Chiodini
chiodini@fnal.gov
Particle Physics Division,
Fermi National Accelerator Laboratory
P.O. Box 500Z
Batavia, IL 60510
(: (630) 840-5151
Fax: (630) 840-3867
chiodini@fnal.gov

We report on several irradiation studies performed on BTeV pixel readout chip prototypes exposed to a 200 MeV proton beam at Indiana University Cyclotron Facility. The pixel readout chip preFPIX2 has been developed at Fermilab for collider experiments and implemented in standard 0.25 um CMOS technology following radiation tolerant design rules. The tests confirmed the radiation tolerance of the chip design to proton total dose up to 14 MRad. In addition, non destructive radiation-induced single event upsets have been observed in on-chip static registers and the single bit upset cross section has been measured. We also show irradiation test results that we are planning to do on June-July 2001, where preFPIX2 readout chips bump-bonded to pixel sensors will be exposed to high dose.

The BTeV experiment is planned to run at the Tevatron collider in ~2006. It is design to cover the ``forward'' region of the p-antip interaction point at the expected luminosity of 2E32/s/cm**2$. The experiment will employ a silicon pixel vertex detector to provide high precision space points for on-line lowest level trigger impact parameter finding. The ``hottest'' chip, located at 6 mm from the beam, will experience a fluence of ~ 1E14/cm**2/y.

This correspond to the highest radiation enviroments at ATLAS and CMS at LHC. A pixel detector readout chip (FPIX) has been developed at Fermilab to meet the requirement of Tevatron collider experiments. The preFPIX2 reppresents the most advanced iteration of very succesfull chip prototypes and has been realized in standard deep-submicron CMOS technology from two vendors. As demostrated by the RD49 collaboration at CERN, the above process can be made very radiation tolerant following specific design rules.

We show results of radiation tests performed this year with preFPIX2 chip prototypes including both total dose and single event effects. The tests have been performed by exposing the chip to 200 MeV protons (at the Indiana University Cyclotron Facility). The comparison of the chip performace before and after exposure shows the high radiation tolerance of the design to hadrons up to ~ 14 Mrad total dose. Last year exposures to radiation from a Colbalt-60 source at Argonne National Lab already verified the high radiation tolerance to gamma radiation up to ~ 30 Mrad total dose. Total dose effects are not the only concern for reliable operation of the detector. Ionizing radiation can induce single event upset (SEU) effects, as unwanted logic state transition in a digital device, corrupting stored data. The single event upsets just described do not permanently alter the chip behavior, but they could result in data losses, shifts of the nominal operating conditions, and loss of the chip control. If the single event upset rate is particularly high it could be significantly mitigated by circuit hardering techniques. Instead, if it is not, it could be tollerated simply by a slow periodic downloading of potentially corrupted data or full system resetting in the worse case. During the irradiation tests, we observed single event upsets in the preFPIX2 registers and measured the rate. The measurements consisted of detecting bit error rates in the static registers controlling the readout chip front-end operating conditions and the pixel cell respons. The single bit upset cross section measured for the digital-analog-converter registers located on the chip periphery was sigma = 3.8(+/-1.2 +/- 0.2)E-16cm**2, while for the mask and charge-injection registers located inside each pixel cell was sigma = 2.0(+/-0.3+/-0.1)E-16cm**2 (where the first error is statistical and the second systematic due to uncertainty in the beam fluence). The implications of the estimated SEU rate in the BTeV pixel vertex detector are discussed. We would like also to report results from irradiation tests planned for June-July 2001 with single chip sensor bump-bonded to a readout chip. In these future test, the primary goals are to increase the statistics of single event upsets and compare the front-end performance before and after irradiation of the assembly sensor-readout chip.

Tony Weidberg
Physics Department
Oxford University
Oxford OX1 3RH, UK
( +44 (0) 1865 273370
Fax +44 (0) 1865 273417
t.weidberg1@physics.ox.ac.uk

The readout of the ATLAS SCT and Pixel detectors will use optical links. The results of new radiation hardness and lifetime after irradiation for Truelight VCSELs are discussed. Final prototype ATLAS style opto-packages have been integrated into the SCT opto-harnesses and tested using a dedicated test system. These opto-harnesses have been used in the system tests of the SCT forward and barrel detectors. This has enabled different grounding configurations to be assessed. The plans for the production of the opto- harnesses are described.

Optical links will be used in the ATLAS SCT and Pixel detectors to transmit data from the detector modules to the off-detector electronics and to distribute a subset of the Timing, Trigger and Control (TTC) data from the counting room to the front-end electronics. The links are based on VCSELs and epitaxial silicon PIN diodes operating at a wavelength of 850 nm.

The radiation hardness and lifetime after irradiation has been studied for a sample of 20 Truelight VCSELs. The VCSELs were exposed to a fluence of 2 10**14 p/cm**2 with 30 MeV protons. Assuming that the damage scales with the NIEL value in GaAs this is equivalent to a factor of two greater than the fluence expected during 10 years of ATLAS operation. The VCSELs survived the irradiation and showed rapid annealing. In order to assess the reliability of the devices after irradiation, accelerated aging tests were performed on the irradiated VCSELs. The results of these tests will be described. The final production wafers for the DORIC4A and VDC ASICs used in the SCT optical links have been produced and tested. The Neutron and photon irradiation tests have been performed for samples from these wafers and the results of these tests will be described.

The opto-packages and the opto ASICs for the barrel SCT are mounted on copper/kapton opto-flex circuits. The opto-flex circuits are used to connect to the SCT module and to make the connection to the low mass Al power tapes. Six of the opto-flex/power tape combinations are combined into an opto- harness. The fibres from the pig-tailed opto-packages are ribbonised and fusion spliced into 12 way and 6 way ribbon fibre. The 12 way (6 way) ribbon fibres have MT12 (MT8) connectors at the patch panel end. One opto-harness is used to read out one half row of SCT modules. Several of these opto- harnesses have been assembled and the procedure used is described. For the forward SCT the DORIC4A and VDC ASICs are mounted on the module hybrid and there is a connector for a plug-in opto-package. The fibres from several (usually six) of these opto-packages are combined into one opto- harness in a similar way to the barrel harness. The results of detailed system tests of the barrel and forward opto-harnesses will be described.

These prototype opto-harnesses have been used in the SCT system test at CERN to assess the performance of SCT modules in a realistic configuration to simulate operation in ATLAS. The results have shown that there is no significant increase in noise, compared to the operation of the SCT modules on individual electrical test stands. Different grounding schemes have been studied. In order to maintain the maximum flexibility during the SCT assembly, the harnesses are being designed so that two different grounding schemes can be implemented.

The plans for the production of the harnesses and the detailed acceptance tests that will be performed are described.

Selcuk Cihangir
Fermilab
Particle Physics Division
selcuk@fnal.gov

W.L. Simon Kwan

swalk@fnal.gov

Pixel detectors proposed for the new generation of hadron collider experiments will use either indium or Pb/Sn solder bump-bonding technology. We have carried out a study of long term effects of both types of bump bonds using daisy-chained silicon on silicon parts. We also studied the effect of thermal cycles. Some of the parts were then exposed to intense radiation using a gamma source and the integrity of the bumps were studied afterwards.

Pixel detectors propsoed for the new generation of hadron collider experiments will use flip-chip mating technology based on either indium or solder bumps to connect the sensors to the readout chips. Last year, we reported a large scale tests of the yield using both technologies. The conclusion is that both seem to be viable for pixel detectors. We have recently carried out a study of long term effects of both types of bump bonds using daisy-chained parts. We also studied the effect of thermal cycles by heating the parts to 100 C for 2 days and cooling them down to -15 C for up to a week. Some of the parts were then exposed to intense radiation using a gamma source and the integrity of the bumps was studied afterwards.

In indium bump bonds, we observed in some channels a substantial increase in resistance along with occurance of capacitance of 50 - 300 pf. All three processes, namely long term storage, heating and cooling, caused this effect. We will quote rates for this effect.

In solder bump bonds, the effect was the breakage of the bonds at some channels. Some of these breakages may have had occured at the UBM (Under Bump Metalization) level. All three processes caused breakage of the bonds. We will quote rates for their occurances at the UBM level and otherwise. Among the three processes, cooling was the least problematic. For some channels, the heating process helped to improve the connectivity.

ATLAS SCT Collaboration

Corresponding author, Zdenek Dolezal
Zdenek.Dolezal@mff.cuni.cz

ATLAS Semiconductor Tracker (SCT) prototype modules equipped with ABCD2T chips were tested with 180 GeV pion beams at CERN SPS. Binary readout method is used so many threshold scans at a variety of incidence angles, magnetic field levels and detector bias voltages were taken. Results of analysis showing module efficiencies, noise occupancies, cluster sizes and magnetic field effects will be presented. Several modules have been built using detectors irradiated to the full ATLAS dose of 3x10E14
p/cm**2 and one module was irradiated as a complete module. Effects of irradiation on the detector and ASIC performance will be shown.

Two types of silicon microstrip modules, barrel and forward, have been tested with the pion beams of 180 GeV/c at the CERN H8 SPS beamline. The barrel modules were equipped with square silicon microstrip sensors of a physical size of 64 mm long and 63.6 mm wide with strips in parallel at a pitch of 80 micrometers. A module had a pair of sensors glued on the top and the other glued on the bottom side of a baseboard of the module, being angled at 40 mrad to have a stereo view. The strip length of a module was 12 cm by connecting the pair of sensors. The forward modules had a similar strip length but were wedge-shaped with a fan geometry of strips with an average strip pitch of about 80 micrometers. Strips were connected to the readout electronics, near the middle of the strips in the barrel module and at the end of the strips in the forward modules.

A module was equipped with 12 readout chips (prototype ABCD2T), 6 on the top and 6 on the bottom side of the module. Chips were glued on specially-designed hybrids based on polyimide supported by carbon substrate.

Several modules have been built using detectors irradiated to the full ATLAS dose of 3x10E14 p/cm**2 with 24 GeV protons at the CERN proton synchrotron and one module was irradiated as a complete module.

The ABCD chip utilises on-chip discrimination of the signal pulses at each silicon detector strip, producing a binary output packet. For this reason, threshold scans (at 12 threshold values) were carried out, with different module parameters or environmental conditions. A total of over a 1000 runs

of 5000 events each were taken at 5 incidence angles, 2 magnetic field levels and 6 detector bias voltages. These data are complemented by noise runs (taken in situ, but with no beam) and local calibration runs. The readout was triggered with an external scintillator system while simultaneously measuring the particle track using 3 telescopes and time of the beam trigger relative to the 40 MHz system sampling clock.

In the course of data analysis, binary hits in the module channels were classified to ‘efficient hits’ and ‘noise hits’ according to their proximity to the extrapolated track position and timing. Bad channels known from lab and in situ calibrations were excluded from the analysis.

Detection efficiency and noise occupancy were then calculated. From their dependence on module parameters further characteristics were determined, as median charge, ballistic deficit, Lorentz angle, spatial resolution, pulse shapes, etc.

Z. Dolezal(corresp. author)(1), J. Broz(1), T. Cechak(2), D. Chren(2), T. Horazdovsky(2), J.Kluson(2), C. Leroy(3), S. Pospisil(2), B. Sopko(2) and I. Wilhelm(1)

(1) Charles University, Prague
(2) Czech Technical University, Prague
(3) Montreal University

dolezal@ipnp.troja.mff.cuni.cz

A direct study of neutron induced Single Event Effects (SEE) has been performed in Prague using collimated and monoenergetic neutron beams available on the Charles University Van de Graaff accelerator. For that, silicon diodes and LHC Voltage Regulator were irradiated by neutrons of different energies (60 keV, 3.8 MeV, 15 MeV). Furthermore, the associated particle method was used, in which 15 MeV neutrons produced in the 3H(d,n)4He reaction were tagged. The measurements allowed to estimate a probability of neutron interactions per sensitive volume of the junction and an upper level of SEE occurrence in the LHC Voltage regulator chip.

CMOS integrated circuits (CMOSICs) are largely used in space, aviation and particle accelerator environments, i.e. at high radiation environments. The use of submicron CMOS processes in these adverse radiation environments requires the application of special architectural and layout techniques. Failures could come not only from total dose effects but also from so-called Single Event Effects (SEE) believed to be responsible for latchup that can destroy ICs completely or render them unusable indefinitely or for various periods of time. Therefore, there is a need to understand the importance of SEE in specific operational environments and to find ways of quatifying the tolerance of the different technologies to these effects. We tried to find out whether neutrons could cause latchup phenomena in CMOSICs.

The occurrence of SEE can be provoked by specific interactions of the neutrons with the silicon chip ((n, alpha), (n,p), (n,n') etc... reactions). In this work, neutron induced SEE were studied directly on silicon diodes as well as on silicon chips.

Several steps have been fulfilled to achieve that goal. At first, the experimental set-up of a collimated, monochromatic and tagged neutron beam has been realised at the van de Graaff accelerator of Charles University, in the collaboration with Montreal University and Czech Technical University, Prague. Neutron beam energies of 60 keV (with an energy spread 10 keV), 3.8 MeV (100 keV) and 15 MeV (100 keV) are available through the reactions 3H(p,n)3He, 2H(d,n)3He and 3H(d,n)4He, respectively. Secondly, tests of the neutron beams quality have been performed including collimation, measurement of energy spread, and monitoring of the flux of neutrons. Finally, the associated particle method for the direct study of SEE, using the 3H(d,n)4He reaction, was developed and tested. The achievement of these steps provide a neutron beam energy range allowing one to recognise the expected energy threshold behaviour of SEE and at the same time to observe the history of each tagged neutron (known with an accuracy of 10 ns) in a collimated beam.

Two types of devices under test (DUT) have been tested. First silicon diodes of different sizes were put to the neutron beam and their response was studied. Levels of hits and pulse height distributions have been recorded for different neutron energies and fluences. The second step consists in the observation of the history of each neutron in a collimated neutron beam generated in 3H(d,n)4He reaction and the registration of a diode hits (pulses) correlated with a neutron of known history by the coincidence unit as simple and as fast as possible. These measurements allowed to estimate a probability of the reaction per sensitive volume of the junction and an amount of energy of reaction products deposited in this volume.

The same measurements were carried out with LHC Voltage Regulator (RD49 project). Here, only the upper limits of SEE for various neutron energies were established, as the measurements continue with the goal of achieving sufficient statistics to determine SEE probabilities.

B. Allongue, F. Arteche, F. Szoncso
CERN
CH-1211 Geneve 23 Switzerland

C. Rivetta
FERMILAB
P.O.500 MS 222 Batavia Il 60510 U.S.A.
rivetta@fnal.gov

The design of DC power distribution for LHC front-end electronics imposes new challenges. Some CMS sub-detectors have proposed to use a DC-power distribution based on DC-DC power switching converters located near to the front-end electronics.

DC-DC converters operate as a constant power load. They exhibit a dynamic negative impedance at low frequencies that can generate interactions between switching regulators and other parts of the input system resulting in system instabilities. In addition, switching converters generate interference at both input and output terminals and can compromise the operation of the front-end electronics and neighboring systems. Appropriated level of filtering is necessary to reduce this interference.

This papers address the instability problem and present methods of modeling and simulation to assess the system stability and performance. The paper, also, addresses the design of input and output filters to reduce the interference and achieve the performance required.

EMI Filter Design and Stability Assessment of DC Voltage Distribution based on Switching Converters

A distinguish feature of LHC detectors is the enormous number of channels in the front-end electronics (FE) in all the sub-parts. It requires low-voltage output power supplies in the range of multi-kilowatts to bias such electronics read-outs. To minimize the volume of the distribution cables, some CMS sub-detectors are developing a DC power distribution based on DC-DC switching converters located near to the FE in the detector caverns.

Switching power supplies, in general, generate more noise than equivalent linear power supplies. In DC power distributions for FE, it is very important to keep the noise up to a level that does not compromise the operation of the FE and neighboring systems. Output filters into these converters are included to smooth the switched output voltage waveform to levels than can be tolerated by the FE. Input filters are needed to attenuate the switching input current waveform to prevent electromagnetic interference problems and to assure electromagnetic compatibility with neighboring systems. These input filters can also significantly affect the stability and performance of DC-DC converters.

Input filters can introduce instabilities in the system. DC-DC switching converters with tight output voltage regulation operate as constant power loads. In such cases, the instantaneous value of the input impedance is positive, but the incremental input impedance is negative. Due to the negative impedance characteristic of switching regulators, interaction between those units and other parts of the system may result in system instability.

Interference that is emitted by DC-DC converters can be either conducted or radiated. In general, interference covers a broad range of frequencies. Inputs and output filters consist of two distinct filter sections. The larger, lower frequency section is included to minimize the differential-mode noise (DMN) produced by the converter. The higher frequency section has a special topology to attenuate both differential and common-mode noise (CMN). The last component is due to currents flowing to ground through parasitic elements of the converter.

Commercial converters include part of these filters. Our goal is to include additional filtering to further reduce both common-mode and differential mode noise at the input and output of the converter. The most critical is the input filter because the primary requirements are: Sufficient attenuation of both DMN and CMN components, stability and good performance of the complete system and also minimum size and reliability.

To define the additional level of attenuation, DMN and CMN measurements of the input and output currents are necessary. The separation of noise components into CM and DM components simplify the filter design. The filter topology allows designing the elements that attenuate the CM noise almost independently of those elements that affect the DM noise components. Also this filter has influence at high frequency and its effect at low frequency can be ignored.

To assess stability and performance a model of the complete system is necessary. It includes not only all the DC-DC converters connected in parallel at the input but also the cable impedance and the output impedance of the primary AC/DC converter. Large-signal and small signal analysis is used to define the necessary damping to include into the input filter to satisfy the required performance.

CMS-ECAL collaboration

Corresponding author : Alessandro Bartoloni – INFN ROMA
I.N.F.N. Sezione di Roma
Ple Aldo Moro 2 - 00185 - Roma
( +39-0649913535/4423
cell. +39-347-3730183
Fax +39-06-4957697

This paper describes the power supply system that will be used to bias the Avalanche Photo Diodes (APD) used in the barrel part of the CMS Electromagnetic Calorimeter detector (ECAL).

Such part is composed by 61200 PbWO crystals each equipped with 2 APD that need a bias voltage in the order of 300 Volts with high stability and ultra low noise figures (40 mV peak-peak).

Such system, that will be located in the CMS control room 150 meters far from the APDs, is currently under development under the responsibility of the INFN-ROMA department.

Prototypes tests showing the system feasibility and reliability are also discussed in the following.

The barrel part of the CMS–ECAL detector is composed by 61200 PbWO2 crystals each equipped with 2 APDs developed for the CMS collaboration by the Hamamatsu corporation.

The APDs have to be reversed biased in the breakdown region at an operating gain (M) of 50 that will allow producing the necessary current value to be processed by the front-end electronics.

For this a bias voltage of about 300 Volts is required.

The stability of the voltage bias seen by the APD directly affects the ECAL resolution through the gain sensitivity, as a constant contribution to s(E)/E. The design goal for the constant term is 0.5%. Other expected contributions to the constant term (intercalibration, light collection uniformity, energy leakage) are estimated of the order of 0.2% or less each. To preserve the resolution, the contribution from the gain stability must be of the same order. As a consequence, considering a safety factor of 2, gain fluctuations due to the APD (and its bias supply) should be limited to the ± 0.1% (RMS) level.

A 3%/V (the typical dM/dV value for the selected APD at M=50) gain sensitivity means that ± 0.1% corresponds to ± 33 mV (66 mV p-p).

For the system specification all the system characteristics (Noise, Ripple, Stability, Regulation ) have then been fixed to 40 mV as maximum value.

Another issue of the system is its locations, because of the high radiation dose expected close to the detector (up to 1 MRad along with a neutron fluence of 2´ 10¹³ n/cm² over the entire life of the experiment) , the power supply system will sit in the control room connected to the detector by cables approximately 150 m long.

This approach leads to the choice of a modular power supply system organized in 144 High Voltage Boards (HVB) each containing 9 High Voltage Channels (HVC) used to supply 900 APDs (100 per channel).

The system will take care also of the variations of the APD leakage current (I_dark) due to the radiation. Measurements made on this subject allows to evaluate that the I_dark from a starting value of 10 nA will increase up to 20 µA during an LHC running time of 10 years.

A leakage current monitor integrated into the system will allows to measure continuously the surged current from 100 APD on each channel.

In order to understand the feasibility and the critical points of the final system, a series of test was performed using laboratory power supplies and some prototypes of the HVB and HVC produced by two different firms (CAEN and ISEG).

For such measurements some test-bed using APDs arrays, programmable electronic load and resistors boxes was built to create load condition similar to the detector.

At the moment laboratory qualification of the final system is going on, qualification on a real system using 400 crystals, 800 APDs and the relative front-end electronics (M0’ module) is scheduled for September 2001 in the H4 beam facility at CERN.

Per Gällnö, CERN, Geneva, Switzerland
EP/ATE
Cellular: +41 (0)79 4527065
Fax +41 (0)22 7679495
( +41 (0)22 7672404
email: per.gallno@cern.ch

The ATLAS detector data flow from the Front End to the Read Out Buffers (ROD) has to be controlled in order to avoid that the ROD data buffers get filled up and hence data getting lost. This is achieved using a throttling mechanism for slowing down the Central Trigger Processor (CTP) Level One Accept rate. The information about the state of the data buffers from hundreds of ROD modules are gathered in daisy-chained fan-in ROD-BUSY modules to produce a single Busy signal to the CTP. The features and the design of the ROD-BUSY module will be described in this paper.

The RD-12 TTC system VMEbus interface, TTCvi, will be produced and maintained by an external electronics manufacturer and will then be made available to the users from the CERN Electronics Pool. The status of this project is given.

Authors :
V. Bocci, A. Di Mattia, E. Petrolo, R. Vari, A. Salamon, S. Veneziano
INFN Rome and Universita`
degli Studi di Roma "La Sapienza"
(+39-06-49914223
Fax +39-06-49914320
Andrea.Salamon@roma1.infn.it

The Atlas Barrel Level-1 muon trigger processes hit information from the RPC detector, identifying candidate muon tracks and assigning them to a programmable pt range and to a unique bunch crossing number.

The on-detector electronics reduces the information from about 350k channels to about 400 32-bit data words sent via optical fiber to the so-called Sector Logic boards.

Each Sector Logic board covers a region Dh x Df = 1.0 x 0.2, it receives the input from up to eight fibers and from thirty-two TileCal trigger towers. The output of the SL board is sent to the Muon Central Trigger Processor Interface (MUCTPI).

Each SL board selects the muons with the two highest thresholds in a sector and associates each muon to a Region of Interest of Dh x Df = 0.1 x 0.1. It also solves RPC chamber overlaps inside the sector and flags all the muons overlapping with a neighboring sector, and it performs the coincidence with the Tile Calorimeter.

In order to keep the full LVL1 system latency below 2 us, the Sector Logic has to perform its functions in five bunch crossing periods.

The design and performance of the Sector logic demonstrator, based on commercial and custom modules and firmware is presented, together with the design of the final VME Sector Logic board.

CONCLUSIONS

The Sector Logic demonstrator design is based on the Multi Function Computing Core (MFCC) 8441 from CES. The MFCC 8441 is a PCI Mezzanine Card (PMC) which is hosted by the VME board RIO2 from CES and is composed of the following parts, which share a common PPC bus: a PCI-bridge interfacing the PMC card with the VME host, a Power PC microprocessor with an SDRAM system memory, a user programmable Front-End FPGA which is connected to a FrontEnd Connector and to the VME backplane.

The FE FPGA contains both the Sector Logic code and the PPC interface. A set of registers and shadow memories were included in the Sector Logic to add flexibility and to test the design.

A custom FE Adaptor Card is used to connect the Sector Logic demonstrator with the Muon Central Trigger Processor Interface (MUCTPI), via a 32-bit LVDS link runnig at 40 MHz.

Various kind of tests were performed to validate the design. Functionality tests were based on data samples from the Atlas standard simulation package. Error rate tests were done by processing input patterns stored on-board. Integration tests with the MUCTPI demonstrator were done to test the connection.

The performance of the Sector Logic demonstrator including the PPC interface and the configuration registers are adequate for the 40 MHz operation and maximum latency of 125 ns.

All the FE FPGA test software were written in C language using the ATLAS DAQ-1 libraries. The test software also includes a high-level behavioral model of the Sector Logic, used to check on-line the functionality of the circuit.

This work has proven that the use of commercial hardware is a valid solution during the first part of the development of custom boards, because it reduces the demonstrator development time and gives the designer good support during the test phase.

The first Sector Logic VME board prototype is currently been designed on the basis of the present demonstrator.

Piotr MALECKI,
Institute of Nuclear Physics,
ATLAS Experiment Lab.
30-055 Krakow, ul Kawiory 26A
( :(48 12) 633 33 66
Fax: (48 12) 633 38 84
malecki@chall.ifj.edu.pl

The Silicon Strip Detector of the ATLAS experiment has modular structure. The granularity of its power supply system follows the granularity of the detector. This system of 4088 multi-voltage channels providing power and control signals for the readout electronics as well as bias voltage for silicon detectors is described. Problems and constraints of the power distribution lines are also presented. In particular, optimal choice between concurrent requirements on material, maximum voltage drop, space available for services, technological constraints and cost are discussed"

The multi-voltage power supply system of the ATLAS SCT provides high current (of the order of 1 A) low voltages for analog and digital parts of the module readout chips as well as a number of low current voltages and control signals for the optical data transmission and clock distribution circuits. Low voltage power supply modules are associated with the high voltage modules which provide bias voltage (up to 500 V) for silicon detectors. Integration of low and high voltage power supply modules is on the level of a common crate equipped with a custom backplane, custom inter-module communication protocol, a common crate controller and a common crate bulk supply. One crate consists of 48 independent, fully isolated power supply channels. Common LV/HV power supply crates communicate with higher level of the Detector Control System (DSC) via the CAN bus protocol.

Power supply modules are located outside of the ATLAS detector. Every SCT module is serviced by a multiwire cable/tape which consists of two pairs of high current lines, two pairs of the corresponding sense wires and a number of low current lines.

This power transmission path is divided on three parts.

The first part running from detector modules through the innermost part of

the detector is made of thin aluminum-Kapton tapes, called low_low_mass tapes. Similar material constraints resulted in the choice of low_mass tapes for the second part of the power transmission lines. Conventional, but custom design copper multiwire cables are applied in the third part of that path.

Many details of the design of the power supply units are closely related to parameters of the power transmission lines. The optimal selection of these parameters on the other hand is the subject for dificult compromises. In this paper we summarize the main requirements, specifications for the SCT power supply and transmission system, present design concepts of both, low and high voltage power modules and concentrate on integration solutions. An optimization process for the selection of the tranmission line parameters and its feed back on the power supply system design is also discussed.

The Final Multi-Chip Module of the ATLAS Level-1 Calorimeter Trigger Pre-processor

G. Anagnostou, P. Bright-Thomas, J. Garvey, S. Hillier, G. Mahout, R. Staley, W. Stokes, S. Talbot, P. Watkins, A. Watson University of Birmingham, Birmingham, UK
R. Achenbach, P. Hanke, W. Hinderer, D. Kaiser, E.-E. Kluge, K. Meier, U. Pfeiffer, K. Schmitt, C. Schumacher, B. Stelzer University of Heidelberg, Heidelberg, Germany
B. Bauss, K. Jakobs, C. Noeding, U. Schaefer, J. Thomas University of Mainz, Mainz, Germany
E. Eisenhandler, M.P.J. Landon, D. Mills, E. MoyseQueen Mary, University of London, London, UK
P. Apostologlou, B.M. Barnett, I.P. Brawn, J. Edwards, C.N.P. Gee, A.R. Gillman, R. Hatley, V.J.O. Perera, A.A. Shah, T.P. Shah Rutherford Appleton Laboratory, Chilton, Didcot, UK
C. Bohm, M. Engstrom, S. Hellman, S.B. Silverstein University of Stockholm, Stockholm, Sweden
Presented by Werner Hinderer (hinderer@kip.uni-heidelberg.de)

Abstract

The final Pre-processor Multi-Chip Module (PPrMCM) of the ATLAS Level-1 Calorimeter Trigger is presented. It consists of a four-layer substrate with plasma-etched vias carrying nine dies from different manufacturers. The task of the system is to receive and digitise analog input signals from individual trigger towers, to perform complex digital signal processing in terms of time and amplitude, and to produce two independent output data streams. A real-time stream feeds the subsequent trigger processors for recognising trigger signals, and the other provides a deadtime-free readout of the Pre-processor information for the events accepted by the entire ATLAS trigger system. The PPrMCM development has recently been finalised after including substantial experience gained with a demonstrator MCM.

Summary

This paper describes the final version of the ATLAS Pre-processor Multi-Chip Module (PPrMCM). Considerable experience has been gained from a demonstrator version previously presented at this workshop series.In the ATLAS Level-1 Calorimeter Trigger, the ATLAS PPrMCM combines pre-processing and readout for four trigger-tower signals on a single substrate. The electrical boundaries of the PPrMCM package were placed at locations in the processing chain where a minimum number of signals enter and leave of the package. The MCM features analog input and digital output, and therefore houses both mixed-signal and purely digital chips. Some of them are commercially available and others are application specific. A Pre-processor ASIC (PPrAsic) developed at the ASIC laboratory of the University of Heidelberg forms the heart of the system and carries out digital processing of four trigger towers. In total the PPrMCM contains nine dies: four FADCs, one Pre-processor ASIC, three LVDS serialisers for the digital data transmission to the subsequent processors, and a timer chip required for the phase adjustment of the FADC strobes with respect to the analog input signals.The tasks of the PPrMCM are:* To digitise four analog trigger-tower signals at 40 MHz with 10-bit resolution. Digitisation at 12-bits is used to extend the effective number of bits.* To process digital trigger-tower data in terms of energy calibration and bunch-crossing timing identification.* To serialize processed trigger tower data using high-speed Bus LVDS chip-sets.* To provide deadtime-free readout of the data from four trigger towers.In order to achieve these, the MCM consists of:* Four 12-bit FADCs manufactured by Analog Devices (AD9042).* One four-channel PPrAsic, providing readout and pre-processing;* One timer chip (Phos4) for the phase adjustment of the FADC strobes with respect to the analog input signals.* Three Bus LVDS Serialisers, 10-bits at 40 MHz (400 Mbps user data rate, 480 MBd including start- and stop-bit).The physical substrate of the PPrMCM is a combination of three flexible Polyimid foils, laminated onto a rigid copper substrate to form four routing layers. Plasma etching is used for so-called buried via connections to adjacent layers, and routing structures are formed in copper using conventional etching techniques. The surface of the top layer is gold-plated to permit safe bonding of aluminium wires. The technology described is implemented in the TwinFlex MCM-L technology provided by the company Wuerth (Germany).Detailed simulations of electrical, thermal and timing properties of the PPrMCM have been carried out. The layout of the substrate has been finalised. The production of a pre-series consisting of 10 PPrMCMs is expected for the autumn of 2001.

Prototype Readout Module for the ATLAS Level-1 Calorimeter Trigger Processors

G. Anagnostou, P. Bright-Thomas, J. Garvey, S. Hillier, G. Mahout, R. Staley, W. Stokes, S. Talbot, P. Watkins, A. Watson University of Birmingham, Birmingham, UK
R. Achenbach, P. Hanke, W. Hinderer, D. Kaiser, E.-E. Kluge, K. Meier, U. Pfeiffer, K. Schmitt, C. Schumacher, B. Stelzer University of Heidelberg, Heidelberg, Germany
B. Bauss, K. Jakobs, C. Noeding, U. Schaefer, J. Thoma University of Mainz, Mainz, Germany
E. Eisenhandler, M.P.J. Landon, D. Mills, E. MoyseQueen Mary, University of London, London, UK
P. Apostologlou, B.M. Barnett, I.P. Brawn, J. Edwards, C.N.P. Gee, A.R. Gillman, R. Hatley, V.J.O. Perera, A.A. Shah, T.P. Shah Rutherford Appleton Laboratory, Chilton, Didcot, UK
C. Bohm, M. Engstrom, S. Hellman, S.B. Silverstein University of Stockholm, Stockholm, Sweden
Corresponding author: Viraj Perera (viraj.perera@rl.ac.uk)

Abstract

The level-1 calorimeter trigger consists of three subsystems, namely the Preprocessor, electron/photon and tau/hadron Cluster Processor (CP), and Jet/Energy-sum Processor (JEP). The CP and JEP will receive digitised calorimeter trigger-tower data from the Preprocessor and will provide trigger multiplicity information to the Central Trigger Processor and region-of-interest (RoI) information for the level-2 trigger. It will also provide intermediate results to the data acquisition (DAQ) system for monitoring and diagnostic purposes. This paper will outline a readout system based on FPGA technology, providing a common solution for both DAQ readout and RoI readout for the CP and the JEP.

Summary

The ATLAS level-1 Calorimeter Trigger consists of three subsystems, namely the Preprocessor, electron/photon and tau/hadron Cluster Processor (CP), and Jet/Energy- sum Processor (JEP). The CP and JEP will receive digitised calorimeter trigger-tower data from the Preprocessor, and will provide trigger multiplicity information to the Central Trigger Processor via Common Merger Modules (CMMs; accompanying paper). Using Readout Driver (ROD) modules, the CP and JEP will also provide region-of-interest (RoI) information for the level-2 trigger, and intermediate results to the data acquisition (DAQ) system for monitoring and diagnostic purposes.The ROD module for both the Cluster Processor and the Jet/Energy-sum Processor is based on FPGA technology. We have designed these modules to be common to both subsystems, using appropriate firmware to handle several different types of data: RoIs, and DAQ data for both the CP and the JEP.The collection of both DAQ and RoI data starts at the processor FPGAs on the processor modules, where for every LHC bunch-crossing data are captured in dual-port RAMs. They are transferred from these RAMs to FIFOs, following a level-1 accept signal received from the Central Trigger Processor via the Timing Control Module. Dual- port RAMs and FIFOs are implemented on the FPGAs. Data from up to 20 of these FPGAs on a processor module are merged onto a single high-speed serial link (HP G- link).The prototype ROD module receives data from four processor modules. It processes and stores the data (with zero suppression if required) in FIFO buffers, formats the data to ATLAS DAQ fragments, and transmits them to DAQ and to the level-2 trigger via S-links at the level-1 accept rate. The data that are sent on the S-links can be spied on for monitoring, and are available on dual-port memories to be read out to a single-board computer via VME for analysis. If more processing power is required, a PCI mezzanine card (PMC) processor can be plugged onto the module.The prototype ROD is implemented as a triple-width 6U VME module with four common mezzanine card (CMC) positions (two either side): one G-link receiver CMC card interfacing to four processor modules, two S-link positions for DAQ and RoIs, and one position for a commercial PMC co-processor card. It also hosts a TTC receiver card with a CERN TTCrx chip to supply the 40 MHz clock, level-1 accept, and other signals such as bunch-crossing number, event number, trigger type, etc.Firmware for CP readout to DAQ and RoI readout to the level-2 trigger has been developed and tested, and initial integration tests have been carried out with the RoI builder (ROIB) and the readout subsystem (ROS). The experience gained from this prototype module will benefit the design of the final 9U production ROD module.

One Size Fits All: Multiple Uses of Common Modules in the ATLAS Level-1 Calorimeter Trigger

G. Anagnostou, P. Bright-Thomas, J. Garvey, S. Hillier, G. Mahout, R. Staley, W. Stokes, S. Talbot, P. Watkins, A. Watson   
University of Birmingham, Birmingham, UKR.
Achenbach, P. Hanke, W. Hinderer, D. Kaiser, E.-E. Kluge, K. Meier, U. Pfeiffer, K. Schmitt, C. Schumacher, B. Stelzer
University of Heidelberg, Heidelberg, Germany
B. Bauss, K. Jakobs, C. Noeding, U. Schaefer, J. ThomasUniversity of Mainz, Mainz, GermanyE. Eisenhandler, M.P.J. Landon, D. Mills, E. MoyseQueen Mary, University of London, London, UK
P. Apostologlou, B.M. Barnett, I.P. Brawn, J. Edwards, C.N.P. Gee, A.R. Gillman, R. Hatley, K. Jayananda, V.J.O. Perera, A.A. Shah, T.P. Shah
Rutherford Appleton Laboratory, Chilton, Didcot, UK
C. Bohm, M. Engstrom, S. Hellman, S.B. Silverstein    University of Stockholm, Stockholm, Sweden
Corresponding author: Eric Eisenhandler (e.eisenhandler@qmw.ac.uk)

Abstract

The architecture of the ATLAS Level-1 Calorimeter Trigger has been improved and simplified by using a common module to perform different functions that originally required three separate modules. The key is the use of FPGAs with multiple configurations, and the adoption by different subsystems of a common high-density custom crate backplane that takes care to make data paths equal widths and includes minimal VMEbus. One module design can now be configured to count electron/photon and tau/hadron clusters, or count jets, or form missing and total transverse-energy sums and compare them to thresholds. In addition, operations are carried out at both crate and system levels by the same module design.

Summary

The ATLAS Level-1 Calorimeter Trigger executes trigger algorithms in two parallel subsystems: Cluster Processor (CP) and Jet/Energy-sum Processor (JEP). Cluster Processor Modules identify electron/photon and tau/hadron clusters, sending the numbers found to merger modules that sum cluster multiplicities for 16 thresholds, first by crate and then for the four-crate subsystem. In the original design these were Cluster Merger Modules, fed by cables to a separate crate. Jet/Energy Modules (JEM) identify jets, and also sum transverse energy and its components over small regions. The numbers of jets found are sent to merger modules that sum jet multiplicities for eight thresholds, first by crate and then for the two- crate subsystem. In the original design this was done by Jet Merger Modules in each crate, fed via the backplane. In parallel, transverse-energy sums were formed by Sum Merger Modules in each crate, also fed via the backplane, followed by subsystem summing and comparison of total and missing transverse energy with sets of thresholds.The functionality of Cluster and Jet Merger Modules was very similar, so first those two designs were unified. A simulation showed that data signals could be transmitted over the full backplane width at 40 MHz single-ended (mandatory due to pin-counts), so the same in-crate layout could be adopted for both the CP and the JEP. It was then shown that the energy merging could be done by the same Common Merger Module (CMM) since the 36-bit wide JEM transverse-energy information could be compressed to 24 bits without significant effect on trigger performance. The FPGA code for summing multiplicities, or for computing total and missing transverse energy, could also run in the same FPGAs. The final rationalisation was to adopt a common high-density custom backplane for both processors. Although this required careful module design, it has advantages for the trigger in addition to simplifying it.There are two CMMs for counting hits or adding transverse energy in each crate. Which operations they carry out is determined automatically by crate and slot occupied. To keep to one design, all modules have facilities for carrying out the final subsystem-wide merging, even though only four of the 12 CMMs are needed for this function.Pins on the common backplane are at a premium (820 pins/module, 5 rows at 2 mm pitch), and full VMEbus cannot be accommodated. Therefore a minimal set of VME lines is used. Inter-module fan-in/fan-out and input data to the CMMs occupy most of the pins, while timing signals and a CANbus for monitoring voltages and temperatures are also present.This backplane and CMM arrangement has allowed addition of new trigger algorithms, namely: forward jets, approximate total transverse energy in jets, and total transverse energy exceeding local thresholds. The programmability of the logic allows other variations to be added later.In addition, two other modules perform multiple roles. A common Readout Driver (accompanying paper) handles both readout data and level-1 trigger regions-of-interest in both CP and JEP, and a common Timing Control Module will service the CP, JEP, and also the Preprocessor subsystem.

A.van den Brink(a), F.Daudo(b), S.Coli(b), G.Feofilov(c), G.Giraudo(b), O.Godisov(d), S.Igolkin(d), P.Kuijer(a), G.-J.Nooren(e), A.Swichev(d), F.Tosello(b)

a/    Utrecht University, Netherlands
b    /INFN, Torino,Italy
c/    St.Petersburg State University, Russia
d/    CKBM,St.Petersburg, Russia
e/    NIKHEF, Amsterdam, Netherlands

Reporter: G.Feofilov
(For the ALICE collaboration)

P.G.Kuijer@fys.ruu.nl
giraudo@to.infn.it
A.vandenBrink@fys.ruu.nl
DAUDO@to.infn.it
tosello@to.infn.it
igolkin@hiex.phys.spbu.ru>
godisov@nataly.spb.su
nooren@nikhef.nl
coli@to.infn.it

We present analysis, technology developments and test resultsof the heat drain system of the SDD and SSD front-end electronicsfor the ALICE Inner Tracker System (ITS). The application of the superthermoconductive carbon fibre thin plates provides a practicalsolution for the development of miniature motherboardsfor the FEE chips situated inside the sensitive ITS volume.Unidirectional carbon fibre motherboards of 160 -300 micron thicknessensure the mounting of the FEE chips and the efficient heat sink tothe cooling arteries. Thermal conductivity up to 1.3 times better thencopper is achieved while preserving a negligible multiple scatteringcontribution by the material (less then 0.07-0.15 percent of X/Xo).

1) State-of-the art Front-end electronics of coordinate-sensitive Si detectors of ALICE at the LHC is situated inside the Inner Tracking System region. Therefore the heat drain of about 7kW of power is to be done under the stringent requirement of minimisation of any materials placed in this area. Analysis of various possible cooling schemes was performed earlier as a starting point of the general ITS services design.

The application of super thermoconductive carbon fibre plastics was proposed in order to get the most efficient integration of the extremely lightweight FEE motherboards and the local heat sink units. ANSYS simulations show the value of temperature gradients along the boards which are in line with the requirements of the systematic aspects of detector performance (gradients of less then 1 degree C).

2) The implementation of these ideas in a single unit called "the heat bridge"

required the development of a new technology of thin unidirectional carbon fibre plates manufacturing. This technology was successfully developed and is being progressing further at present. The application of super thermoconductive fibre Thornell KX1100 for this purpose is the key point.

The conductivity along the fibre is about 1100W/M/K, while the mechanical strength is ensured at the level of steel. The thermal expansion coefficient of the carbon fibre based compounds is very low (close to zero), meaning the mechanically stabilised devices. The flat carbon unidirectional fibre plates were manufactured ranging in thickness from 150 to 330 microns.

The dimensions of the plates used could be from 1*7 - to 10*10 cm2. Summary of the different configurations of heat bridges produced is presented. Various types of surface coatings were also tested: pure carbon fibre surfaces and insulating Al ceramics coatings.

The carbon fibre heat bridge surface quality tests were done for a batch of CF plates. The roughness of the surface was measured and found to better than 10 microns. The choice of technology for ALICE SDD and SSD FEE chips was performed. The prototype heat bridges were tested for mounting and microcable bonding technology.

3) Thermal conductivity tests were performed for a variety of heat bridges. Results show the performance of the best samples at the level of 1.3 of copper of the same geometry.

Authors:
K.E. Arms, K.K. Gan, M. Johnson, H. Kagan, R. Kass, C. Rush, S. Smith and M. Zoeller
Department of Physics, The Ohio State University,
Columbus, Ohio 43210, USA

J. Hausmann, M. Holder, M. Kraemer, A. Niculae and M. Ziolkowski *
Fachbereich Physik, University of Siegen,
57068 Siegen, Germany

*corresponding author: e-mail michal.ziolkowski@cern.ch

The aim of our work is to design radiation-hard CMOS electronics for optical data transmission in the ATLAS Pixel detector. Two ASICs are under development: a VCSEL driver chip for 80 Mb/s data transmision from the detector and a Bi-Phase Mark decoder chip to recover control data and 40 MHz clock received optically by a PIN diode on the detector side. Both ASICs are implemented in radiation-hard 0.8um DMILL technology. Samples of chips were irradiated recently with 25 GeV protons up to the total dose of 55 Mrad and the conclusive results are expected in the Summer of 2001.

Originally the optical driver and Bi-Phase Mark decoder ASICs have been designed by SemiConductor Tracker community and have been implemented in AMS 0.8 um npn Bi-Polar process. In order to satisfy the needs of the Pixel community we have re-designed both circuits and fabricated them in DMILL radiation-hard CMOS technology providing low power dissipation and enabling assembling flexibility. First encouraging results are now available. Most of the ASICs can survive up to an irradiation dose of 55 Mrad in the initial irradiation trial. As expected, unfavorable effects of irradiation in the decoder chip are compensated by increased supply voltage: from 3.2 V initially - up to 5.0 V after total exposure. Detailed comparison of the decoder chip characteristics before and after irradiation will be carried out by mid of May,~2001, following post-irradiation samples release. In particularly low input current threshold found before exposure will be re-examine. Also the VCSEL driver chip has sustained its good performance during irradiation trial. Minor bright current drop after irradiation is easily correctable by means of tuned bias current whereas the observed increase of dim current is a favorable change, since irradiated VCSELs show higher bias threshold. Third DMILL iteration of Bi-Phase Mark decoder chip is now in preparation. The performance at low input current will be equalized by including a feedback circuit for voltage offset correction. Three independent decoder channels will be arranged on single chip as required by array-like assembling plan. New DMILL samples will be under tests in early October 2001. In addition to DMILL implementation, we have recently designed both ASICs in a deep submicron 0.25um technology with expectation to minimize power dissipation and to achieve very good inherent radiation tolerance. First samples will be evaluated in June 2001.

A. Rivetti (1,2), G. Anelli (3), G. Mazza(2), I. Martinez (2,4), F. Rotondo (2), F. Tosello (2), R. Wheadon (2)

for the ALICE collaboration

1. Università di Torino, Dipartimento di Fisica Sperimentale, Via P. Giuria 1, 10125, Torino - ITALY
2. INFN, Sezione di Torino, Via P. Giuria 1, 10125, Torino - ITALY
3. CERN, EP Division, CH1211, Geneve 23, Switzerland.
4. Cinvestav, Mexico-City, Mexico.

Abstract

The front-end system of the Silicon Drift Detectors (SDDs) of the ALICE experiment is made of two ASICs. The first chip performs the preamplification, temporary analogue storage and analogue-to-digital conversion of the detector signals. The second chip is a digital buffer that allows for a significant reduction of the connection from the front-end module to the outside world. In this paper the results achieved on the first complete prototype of the front-end system for the SDDs of ALICE are presented.

Summary

Silicon Drift Detectors will be used in the third and fourth layer of the Inner Tracking System (ITS) of the ALICE experiment. In order to exploit the capabilities of the SDDs in terms of both spatial and energy resolution, analogue read-out must be performed. Therefore, for each anode of the sensor, the signal must be amplified and converted to a digital representation with high accuracy. The very limited space that will be available on the final hybrid made it mandatory to implement the whole analogue processing chain on the same chip. A half-size prototype of this unit has been developed. It contains 32 preamplifiers, a 32-channel analogue memory and sixteen 10-bit charge redistribution converters. The chip has been designed in a 0.25um CMOS process, using radiation tolerant layout techniques. After digitisation, the data must be transferred outside the front-end hybrid to an ASIC, which performs data compression and formatting. Since the use of one digital bus per each front-end chip would lead to an impractical number of connections, a multi-event buffer strategy has been adopted. The data are stored in a digital memory with a two-event capability. In this way, only a single 8-bit bus every four front-end chips can be used. A full-size prototype of the digital buffer has been produced as a custom ASIC in a 0.35um CMOS process. Since the digital buffer and the front-end chip are located very close to each other on the same hybrid, it is very important to assess the functionality of the whole system. The aim is to guarantee that the performance of the front-end are not impaired by the significant amount of digital activity. For this purpose, extensive measurements have been carried-out on a preliminary version of the system that contains one front-end chip and one digital memory. The results of these tests will be described in detail in this paper for the first time. These results are extremely positive, since no degradation in the performance of the front-end due to the digital buffer has been observed. The overall system fulfils the requirements of the experiment in terms of speed (peaking time 45 ns), dynamic range (9 mips), resolution (10 bits) and with a preliminary noise performance already compatible with the ALICE read-out requirements. On the basis of this experience, a complete hybrid hosting four front-end chips and four digital buffers is under design and will be tested by the end of the year.

Jacques Lecoq, Gerard Bohner, Remy Cornat, Pascal Perret,
Cyrille Trouilleau. LPC Clermont Ferrand

lecoq@clermont.in2p3.fr

The LHCb preshower signals show so many fluctuations at low energy that a classical shaping is not usable at all. Thanks to the fact that the fraction of the collected energy during a whole LHC beam crossing time is 85%, we studied the special solution we presented at Snowmass 1999 workshop. This solution consists of 2 interleaved fast integrators, one being in integrate mode when the other is digitally reset. Two track and hold and an analog multiplexor are used to give at the output 85% of the signal plus 15% of the previous one. These 15% are digitally computed from the previous sample, and subtracted. A completely new design of this solution had to be made. This new design is described, including new methods to decrease the supply voltage and the noise, as well as to increase the quality of the reset and the linearity. An output stage, consisting of a AB class push-pull using only NPN transistors is also described. Laboratory and beam test results are given.

The LHCb preshower is used for the level 0 trigger, for which a threshold corresponding to 5 minimum ionization particle ( MIP) is applied, with a 2% accuracy. This detector is also used to improve electron and photon measurement up to 100 MIP. Theses two functions give us a dynamic range of 0.1 to 100 MIP.

The study of the signal given by a scintillator cell and the 64 Hammamatsu PMT,

with a good agreement with their simulation, shows us that at low energy, the dominant effect is the statistical fluctuation of the photoelectron collection, while at high energy the dominant effect is the PMT saturation which begin at 0.6 mA.

These conditions, and the fact that the signal length is always longer than 25ns, drive us to the solution described before.

We don't change the main electronic choices we made on 1999:

A fully differential design to minimize the noises.

Bipolar transistors at the input stages to reduce the offsets.

CMOS transistors to save power and design integrator switches.

However, we had to redesign the chip due to the following considerations:

Because of the PMT saturation, we had to increase the gain by a factor 20, and then we had to take more care of the noise and offset effects. For the noise, the integrator input stage was changed, and for the offset and the operating point stability a special common mode feedback loop was added.

We need a very high quality reset, to be able to compute the subtraction with a negligible error, even in the cases of a maximum signal immediately followed by a "trigger level" one: the integrator itself was changed.

The supply voltage had to be decreased down to +/- 2.75 V to match the foundry specifications, and to obtain the "small consumption" of 100mW/channel.

To carry the 6000 output analog signals, we plan to use simple ethernet

differential cables on up to 20m long, in this case, we must adapt this cable at both end, and then have to double the dynamic. (2 volts instead of 1). To save power, this dynamic is done in the last stage by designing a differential analog multiplexor

with a gain of two, and a 2V dynamic range with a +/- 2.75 V supply. This required the design of parallel linearity correction instead of the previous serial one.

We have to drive the cable efficiency without extra chips: an "all NPN

A-B class push-pull " was designed.

A first prototype of this new design was successfully realized, and tested both in laboratory and in test beam at CERN. The results were in very good agreement

with simulation, and with noise estimation: The 10 bits dynamic range with a linearity error smaller than few per thousand is achieved, while the measured noise is half a LSB, as expected from our estimation.

After realization and test of the new output stage on a separate chip, a 4 channels

chip was built, including all the functionalities.

At least, the final 8 channels version was sent to AMS foundry on april 2001.

The design of the chip,and specially its new features, are detailed, the method used to estimate and to compute the noise of a switched system is described.

Finally, laboratory and test beam results , including noise measurement, are given.

H. Chen, F. Lanni, M.A.L. Leite, S. Rescia and H. Takai
Brookhaven National Laboratory - Physics Department
Upton, NY - 11973 - USA

An optically coupled charge injection system for ionization based radiation detectors which allows a test charge to be injected without the creation of ground loops has been developed. An ionization like signal from an external source is brought into the detector through an optical fiber and injected into the detector electrodes by means of a photodiode.

For the performance tests of ionization based radiation detectors it is desirable to have a system which is capable of injecting a charge of known value in a condition that is as close as possible to the operating environment, where charge is locally generated by the ionization of the sensitive media in the detector. One of the main problems with the conventional approach of the direct injection through an electrical cable connected to the detector electrodes is the change of the detector electrical characteristics. In particular, the grounding configuration of the system can be completely modified by the introduction of the injection circuit new ground path. The use of an optically coupled injection, in which a light to current converter is placed on the electrodes of the detector to generate the ionization signal, allows for a full galvanic isolation between the detector and the test pulser. A photodiode installed on the electrodes and biased by means of the high voltage system achieves the light to current conversion. It has a capacitance of only a few pf, small if compared with detector capacitances of the order of nF. The photodiode should also have a fast time response and low dark current. Size is also an issue, as this device may needs to fit in spaces of only a few millimeters. The light, generated by a laser diode stimulated to produce a suitable signal for the detector, is brought to the photodiode using a multimode optical fiber.

As an example of this method, the ATLAS Electromagnetic Liquid Argon Calorimeter test stand at BNL has been modified by adding photodiodes on several electrodes. The optical signal is created using a light pulse generator whose output is modulated to produce the same triangular shaped pulse generated by an ionization signal. Crosstalk studies can also be performed by injecting one electrode and recording the crosstalk pattern on neighbor channels. Results of measurements showing how the detector-readout system can be characterized based on the analysis of the signal shape and how the crosstalk at several system levels can be evaluated in this particular case will be presented.

Roberto Beccherle
INFN - Sez. di Genova
Via Dodecaneso, 33
I-16146 GENOVA
( +39 10 353-6485
Fax +39 10 353-6319
Roberto.Beccherle@ge.infn.it

The main building block of the Atlas Pixel Detector is a "module" made by a Silicon Detector bump-bonded to 16 Analog Front-End chips. All FE's are connected by a star topology to the MCC. MCC does system configuration, event building, control and timing distribution. The electronics has to tolerate radiation fluences up to 10^15 cm^-2 1Mev in equivalent neutrons during the first three years of operation. The talk describes the first implementation of the MCC in DMILL (a .8um Rad-Hard technology). Results on tested dices and irradiation results of this devices at the CERN PS, up to 30 MRad, will be presented. The chip was operating during irradiation and allowed to measure SEU effects.

The Module Controller Chip (MCC) is an ASIC which provides complete control of the Atlas Pixel Detector module. Besides the MCC the module hosts 16 FE chips bump-bonded to a Silicon Detector.

The talk is divided in three sections.

In the first section we describe the requirements that the MCC has to fulfil. Main features of this device are the ability to perform event building which provides some data compression on data coming from 16 Front-End chips read out in parallel. The system clock frequency is 40MHz. Inside the MCC 16 Full Custom FIFO's temporary store data received by the FE chips. Event Building is performed by extraction of hits from those FIFO's and formatting the event in one or two serial streams that allow a data transfer up to 160 Mbit/s. All the operations on the module (configuration of MCC and FE's, trigger and resets) are performed by means of a serial protocol which is decoded inside the MCC. The Trigger command decoding is done allowing for a single bit flip on the data line without loss of timing information.

First a prototype and then a full version of the chip where designed and tested. This is described in the second section of the talk. The prototype chip, called MCC-D0 is made of a Full Custom FIFO, the whole Command Decoder and an array of configuration registers. The second chip is a full scale MCC (MCC-D2) designed to be integrated in a Rad-Hard version of the module.

The third part describes in detail the tests made on both chips focusing on the irradiation tests done at PS at CERN where 8 MCC-D0's were successfully irradiated up to 30 MRad. The chips were irradiated while operating them. This allowed us to perform a detailed measurement of both static and dynamic Single Event Upset (SEU) effects. We also describe our test system, developed in Genova, which allows a comparison between the actual hardware, hosted on a VME board, and a C++ simulation of the MCC.

Author:
Kerry Bernstein
STSM, IBM Server Technology
863K, 1000 River Rd, Essex Jct, VT 05452
(: (802)769-6897 HOME: (802) 899-2216
Fax: (802)769-6744 PAGE: (802) 769-1844 x 3946

kbernste@us.ibm.com

Entropy is a worthy adversary! High performance logic design in next-generation CMOS lithography must address an increasing array of challenges in order to deliver superior performance, power consumption, reliability and cost. Technology scaling is reaching fundamental quantum- mechanical boundaries! This talk will review example mechanisms which threaten deep submicron VLSI circuit design, such as tunneling, radiation- induced logic corruption, and on-chip delay variability. We will also examine architectures, circuit topologies, and device technologies under development which extend "evolutionary" concepts and introduce "revolutionary" paradigms. It will be these revolutionary technologies which will bring us to the threshold of human compute capability.

Author:
Kerry Bernstein
STSM, IBM Server Technology
863K, 1000 River Rd, Essex Jct, VT 05452
(: (802)769-6897 HOME: (802) 899-2216
Fax: (802)769-6744 PAGE: (802) 769-1844 x 3946
kbernste@us.ibm.com

Market demand of microprocessor performance has motivated continued scaling of CMOS through a succession of lithogrpahy generations. Quantum-mechanical limitations to continued scaling are becoming readily apparent. Partially-Depleted Silicon-on-Insulator (PD-SOI) technology has emerged as an evolutionary means of circumnavigating these limitations. This tutorial will first introduce the audience to high performance SOI device physics, and its idiosyncrasies. Preferred circuit design practices and considerations for microprocessor components will be examined. Finally, future buried oxide devices inpired by the PD-SOI MOSFET will be reviewed. This talk will draw heavily from the textbook "SOI Circuit Design Concepts" published by Kluwer Academic Publishers.

Yasuaki Ishida, Chikara Fukunaga, Ken-ichi Tanaka, Naofumi Takahata
(Department of Physics, Tokyo Metropolitan University)
for ATLAS TGC Electronics Group
E-mail:ishida@comp.metro-u.ac.jp <Main>
URL:http://tmubsun.center.metro-u.ac.jp/ishida/

We present the development of an emulator of TTC system. This emulator is made using an ASIC and includes functionalities of generation of LHC bunch pattern as well as random trigger, relevant functionalities of TTCvi, TTCvx, and TTCrx in one IC chip. Therefore, a test system environment of detector front-end modules using TTC system can be simplified dramatically. And thanks to the random trigger generation, this emulator can give us a realistic experimental environment for an electronics system. We discuss the function of this emulator and test results of the ASIC.

We have developed a TTC emulator for the ATLAS Endcap Muon Electronic test setup. This emulator involves generation of the LHC bunch pattern and generation of some signals of TTCvi, TTCvx, and TTCrx on one IC chip.

The signal generation of TTC requires a relatively large-scale setup (two VME modules (TTCvi and TTCvx), TTCrx chip as well as OE/EO converters) even we need a few signals for electronic development and debugging. It is not necessary to use such a complicated system and purchase many modules if we use this emulator, cost can also be held down, and test setup will be simplified.

This emulator is made using ASIC of 0.6mm, and can generate the following TTC signals; Trigger (L1A), Bunch Counter Reset (BCR), Event Counter Reset (ECR), Pre-trigger, Orbit, BC, BCID[11:0], Event ID (EVID[23:0]), Trigger Type, and 40MHz Clock.

Trigger is Level 1 Accept signal, and Pre-trigger announces a Level 1 Accept signal beforehand early by 2.5us. Since it brings close to more nearly actual experiment environment, Trigger is generable at random. However, since completely random signals could not be made, only pseudo random pulse pattern has been producible with this emulator.

BC is generated with the LHC, SPS and PS bunch signals structure. 1 bunch is 25ns, and 72 bunches with 12 missing bunches are 1 PS batch. Bunch Disposition in the LHC, SPS and PS is repeating 3-batch and 4-batch. 3-batch and 4-batch cycles will be interleaved in the form; 334 334 334 333, in order to fill each ring with a total of 2808 bunches. And 3564 bunches (include missing bunches) are 1 Orbit signal. 1 Orbit signal is 88.924us, which is LHC (1-ring) cycle.

BCR and ECR are counter reset signals. BCR is generated automatically when BCID is 0. And BCR and ECR are generated manually when appropriate input signals are high.

Initially, we have implemented the emulator using a Xilinx XCS40PQ208 that is easy to modify. However, when this FPGA was used, we were not able to reproduce 40MHz clock, and BC pattern stably and properly. Therefore, this emulator chip has been rebuilt with an ASIC rather than with another fast FPGA. We have added new signal emulation (Trigger Type, Event ID) for the ASIC.

We implement a TTCrx chip with the test board developed by CERN/MIC group as a mezzanine for the actual setup. If, therefore, the emulator chip is mounted on the same board instead of TTCrx, we can emulate all the TTC signals required for the system.

Joel Bovier
Director R&D
CES Creative Electronic Systems SA
70 route du Pont Butin
CH 1213 Petit Lancy, Switzerland
joel@ces.ch
((+41 22) 879 51 00

This paper describes the different aspects of modern board level electronic design with the consequences on the fabrication process. New technology packages such as BGA and FBGA implies the use of secure design techniques because the rework is very difficult. CES’s experience of the different steps will be covered : design for testability, EMI/RFI concern, signal integrity, in situ programming, new PCB layout techniques, JTAG testing strategy, and yield in production.

Commissioning results of the First Level Trigger in HERA-B during 2000

Imma RIU
Riu@mail.desy.de

Abstract

During year 2000, the First Level Trigger was installed, operated and commissioned in HERA-B. This paper describes the pattern recognition algorithm, its implementation in electronics and the commissioning results.

The basic task is to accept events with lepton pairs that originate from the decay of the J/psi meson. With a latency smaller than 10 microseconds, the First Level Trigger has to process about 100,000 channels of detector data that are readout every 96 ns. Using a kalman filter technique, the First Level Trigger searches for tracks produced in the detector through up to seven layers.

Summary

The basic task of the HERA-B First Level Trigger is to accept events

with lepton pairs that originate from the decay of a J/psi meson. In order to filter these events out of the immense data stream produced out of the 920 GeV proton nucleon interactions at 10 MHz in HERA-B, a very fast trigger had to be developed. A rate reduction to 50 kHz is required due to the bandwidth of the Second Level Trigger. It explores the full detector granularity and is able to reconstruct tracks from 5 to 200 GeV momentum.

The First Level Trigger receives pretriggers from the electromagnetic calorimeter and the muon detector systems that point to the location of possible electron or muon candidates in the event. Being Kalman filter inspired, the First Level Trigger starts from these points and tries to find a track through a sequence of tracking chambers (up to seven) towards the target. The filter process is implemented in hardware processors (so-called TFUs), each assigned to a certain section of a given tracking chamber. They sit on memory boards containing all relevant hit data of their chamber section and communicate the results of the filter step by short messages containing the current track information. In order to simplify the filter logic, it is assumed that the tracking chambers used in the First Level Trigger are 100% efficient. For that reason, all layers participating in the First Level Trigger are double layers. The last processor in the filter communicates the position and direction of a found lepton track to a specialized processor (so-called TPU), which determines the primary momentum vector of the lepton and applies some cuts on the momentum and transverse momentum of the track. A final processor (so-called TDU) issues the trigger after applying some cut on the invariant mass between the accepted leptons, or on number of tracks.

These processors are based on massive use of EPLDs and Look Up Tables and are the core of the system. Approximately 100 of them operate fully pipelined and in parallel. The processors are interconnected with 2 Gbit/s links to communicate the results. The detector data arrive to the processors through about thousand 500 Mbit/s optical fibers. All these processors are housed in nine VME crates which are controlled by Power PC computers.

The complete First Level Trigger system has been set up during year 2000 and an intense commissioning and debugging phase has taken place. It can be shown that it finds tracks and its performance is mainly driven by the performance of the different detectors. This is the first time a dead timeless trigger system has been successfully

used to reconstruct tracks in events at a very high rate of 10^7 events per second. Since the trigger technologies planned for the LHC experiments are similar to our system, these results can provide a proof of principle for the LHC trigger designs.

Prototype Slice of the Level-1 Muon Trigger in the Barrel Region of the ATLAS Experiment

V.Bocci, G.Chiodi, S.Di Marco, E.Gennari, E.Petrolo, A.Salamon, R.Vari, S.Veneziano
INFN Roma, Dept. of Physics, Università degli Studi di Roma "La Sapienza"
p.le Aldo Moro 2, 00185 Rome, Italy

Abstract

The ATLAS barrel level-1 muon trigger system is split in an on-detector and an off-detector part. Signals coming from the first two RPC stations are sent on detector to dedicated ASICs mounted on the low-pT Pad boards, that select muon candidates compatible with a programmable pT cut of around 6 GeV/c, and produce an output pattern containing the low-pT trigger results. This information is transferred to the corresponding high-pT Pad boards, that collect the overall result for low-pT and perform the high-pT algorithm using the outer RPC station, selecting candidates above a threshold around 20 GeV/c. The combined information is sent via optical fibre off-detector to the optical receiver boards and then to the Sector Logic boards, that count the muon candidates in a region of Dh ´ Df =1.0´ 0.1 ,and encode the trigger results. The elaborated trigger data is sent to the Central Trigger Processor Muon Interface on dedicated copper link. The read-out data for events accepted by the level-1 trigger are stored on-detector and then sent to Read-Out Drivers via the same receiver boards mentioned before sharing the bandwidth with the trigger data.

A trigger slice is made of the following components: a low-pT board, containing four Coincidence Matrix boards; a high-pT board, containing 4 CM boards, the Pad logic board and the optical link transmitter; an optical link receiver; a Sector Logic board; a Read-Out Driver board. Prototype functionality will be presented.

Summary

The ATLAS barrel level-1 muon trigger system has the following main requirements: coarse measurement and discrimination of the muon transverse momentum pT; bunch crossing identification; fast and coarse tracking to identify tracks in the precision chambers that are related to the muon candidate; 2nd-coordinate measurement with a required resolution of 5–10 mm.

A trigger station is made of two detector layers, each one is composed by two RPC detectors, read out by two orthogonal series of pick-up strips of about 3 cm pitch: the h strips parallel to the MDT wires (z direction) provide the "bending" coordinate of the trigger detector; the f strips, orthogonal to the wires, provide the second "non-bending" coordinate.

To reduce the rate of accidental triggers, due to low-energy background particles in the ATLAS cavern, the algorithm is performed in both the h and f  projections for both low-pT and high-pT triggers. The first stage of the trigger algorithm is performed separately and independently for the two projections. A valid trigger is generated only if the trigger conditions are satisfied for both projections. The trigger logic requires three out of four layers in the middle stations for the low pT trigger and, in addition, one of the two outer layers for the high-pT trigger. The . and f trigger information is combined to generate the Regions-of-Interest (RoI), identifying areas in the apparatus in which track candidates are found with a granularity of ~0.1 ×0.1 in the h-f pivot plane.

The signals from the RPC detector are amplified, discriminated and digitally shaped on-detector. In the low-pT trigger, for each of the h and the f projections, about 200 RPC signals of the two detector doublets, RPC1 and RPC2, are sent to a Coincidence Matrix (CM) board, that contains a CM chip. This chip performs almost all of the functions needed for the trigger algorithm and also for the read-out of the strips. It aligns the timing of the input signals, performs the coincidence and majority operations, and makes the pT cut on three different thresholds. It also contains the level-1 latency pipeline memory and de-randomising buffer. The CM board produces an output pattern containing the low-pT trigger results for each pair of RPC doublets in the hor f projection. The information of two adjacent CM boards in the h projection, and the corresponding information of the two CM boards in the f projection, are combined together in the low-pT Pad Logic (Pad) board. The four low-pT CM boards and the corresponding Pad board are mounted on top of the RPC2 detector. The low-pT Pad board generates the low-pT trigger result and the associated RoI information. This information is transferred, synchronously at 40 MHz, to the corresponding high-pT Pad board, that collects the overall result for low-pT and high-pT. In the high-pT trigger, for each of the h and f projections, the RPC signals from the RPC3 doublet, and the corresponding pattern result of the low-pT trigger, are sent to a CM board, very similar to the one used in the low-pT trigger. This board contains the same coincidence-matrix chip as in the low-pT board, programmed for the high-pT algorithm. The high-pT CM board produces an output pattern containing the high-pT trigger results for a given RPC doublet in the h or f projection. The information of two adjacent CM boards in the h projection and the corresponding information of the two CM boards in the f projection are combined in the high-pT Pad Logic board. The four high-pT CM boards and the corresponding Pad board are mounted on top of the RPC3 detector. The high-pT Pad board combines the low-pT and high-pT trigger results. The combined information is sent, synchronously at 40 MHz, via optical links, to a Sector Logic (SL) board, located in the USA15 counting room. Each SL board receives inputs from up to height Pad boards, combining and encoding the trigger results of one of the 64 sectors into which the barrel trigger system is subdivided. The trigger data elaborated by the Sector Logic is sent, again synchronously at 40 MHz, to the Muon Interface to the Central Trigger Processor (MUCTPI), located in the same counting room. Data are read out from high-pT Pad boards only. These data include the RPC strip pattern and some additional information used in the LVL2 trigger. The read-out data for events accepted by the LVL1 trigger are sent asynchronously to Read-Out Drivers (RODs) located in the USA15 underground counting room and from here to the Read-Out Buffers (ROBs). The data links for the read-out data are independent of the ones used to transfer partial trigger results to the SL boards. Pad, SL and MUCTPI modules generate themselves read-out data on partial trigger results, in order to monitor the system.

This work describes an alternative to the current ALICE baseline solution for a TO detector, still under development. The proposed system consists of two MCP-based T0/Centrality Start Detectors (backward-forward isochronous disks) equipped with programmable, TTC  synchronized front-end electronic cards (FEECs) which would be positioned along the LHC colliding beam line on both sides of the ALICE interaction region. The purpose of this arrangement, providing both precise timing and fast multiplicity selection, is to give a pre-trigger signal at the earliest possible time after a central event. This pre-trigger can be produced within one 25 ns LHC bunch crossing. It can be delivered within 100 ns directly to the Transition Radiation Detector and would be the earliest L0 input coming to the ALICE Central Trigger Processor. A noise-free passive multichannel summator of 2ns signals is used to provide a determination of the collision
time with a potential accuracy better than 10 ps in the case of Pb-Pb collisions, the limit coming from the electronics.Results from in-beam tests confirm the functionality of the main elements. Further development plans are presented.

Summary

A fast pre-trigger decision (within one 25 ns bunch crossing) for the ALICE experiment at the LHC should handle the following functions:

(i) precise T0 determination (better than 50-100 ps resolution);
(ii) centrality of the collision determination;
(iii) min-bias pre-trigger production within 100 ns after the collision for the Transition Radiation Detector;
(iv) coordinate of primary vertex;
(v) beam-gas interaction supression;
(vi) pile-up suppression.

This paper describes a solution involving two MCP-based T0/Centrality Start Detectors (backward-forward isochronous disks composed of 16 multipad sectors
each) and the relevant programmable, TTC synchronized front-end electronic cards (FEECs), positioned along the colliding beam line on both sides of the
interaction region. It is an alternative to the current ALICE baseline solution for the T0 detector, and has very promising features. The detector and electronics provide precise timing, multiplicity selection and a collision pre-trigger signal for the Transition Radiation Detector (TRD) at the earliest possible time after the central event.  An analogue, noise-free summation of signals from the sensitive detector pads allows precise determination of event timing and multiplicity parameters in the simplest way.

Estimates for Pb-Pb collisions (high multiplicity events) show that with suitable electronics a limiting time resolution better than 10 ps could be achieved, while for single MIPs a measured value of 75 ps has been achieved, close to the predicted result for a single particle.

A minimum-bias pre-trigger signal could be delivered within 100 ns directly to the ALICE Transition Radiation Detector (the TRD start). Selection on multiplicity, which is done by the fast Multiplicity Discriminator(MD),  would provide the earliest L0 input signal coming to the Central Trigger Processor. The last signal gives a precise collision time (T0).

The benefits of this approach, based on the use of noise-free passive summators, are in the considerable decrease  in number of the electronics channels providing the development of just  a few precise timing channels. Fast multiplicity analysis (by the Multiplicty Discriminator) and precise timing measurements are followed by a logical pre-trigger decision within 25 ns of the time of the collision.

Some results and tests of the main functional elements of the ALICE pre-trigger scheme are presented. They include the implementation of a microelectronic  multichannel passive summator (1.5 GHz frequency range), low-noise 50-Ohms impedance preamplifiers (3000e noise in 1GHz range), a fast Multiplicity Discriminator, standard Constant Fraction Discriminators, the Philips Scientific Instruments Timing discriminator and the Double Treshold Timing  Discriminator (DTD).

Results of in-beam tests at CERN of the main system elements, including the MD and the DTD, confirmed their functionality. Further developments of the electronics are discussed.

Further Developments in the ALICE Trigger

Anton Jusko (Slovak Academy of Sciences, Kosice) for the ALICE Collaboration

Abstract

The ALICE experiment is completing its technical specification stage, with most sub-projects about to start building. The development of the trigger system must mirror this process by specifying the interfaces and protocols for each stage in the trigger. In addition, in ALICE, sub-detector  groups will be able to test their systems using a Local Trigger Unit (LTU), which provides the sub-detector front-end systems with the correct sequence of signals driven either by the Central Trigger Processor (CTP) or by a simple pulser.

In the last year a draft User Requirement Document (URD) has been prepared for the CTP. Recently, changes have been recommended for the number of inputs and trigger classes. A study of the implementation of these new reuirements will be presented.

Summary

Most of the detectors in ALICE have now completed their Technical Design Reports (TDRs) and are preparing to start production. A TDR has not yet been produced for the trigger system and the data-acquisition system, and this is not expected to happen until the second half of next year. However, the interfaces of these systems to each other, and also the interface to each sub-detector, are  being specified well before this so as to to guide the electronics designers for the sub-detector systems. This process was started in 1999 for the trigger system, leading to the release of a draft User Requirement Document (URD) for the Central Trigger Processor in May 2000. The main points in this were reviewed las year at the LEB workshop in Cracow.

The principal challenges for the ALICE trigger come from the fact that the front-end systems chosen for many of the detectors can tolerate a short latency (about 1.2 microseconds in the worst case), and that others have very long sensitive periods (up to about 100 microseconds) leading to potential problems with pile-up. In order to cope with the first problem, the trigger must be split into two "fast" levels, with latencies of 1.2 microseconds and  5.5 microseconds (L1), as not all trigger levels are ready in time for the earliest level (L0). The second requires a third trigger level (L2) and monitoring of "past-future protection", in this case to ensure taht no more than a certain number of interactions take place in a designated past-future protection interval, related to the sensitive time for the detector.

It turns out that a convenient method for combining these properties is through the notion of trigger classes. A set of parameters, such as the list of detectors to be read out, the required conditions on the inputs, the past-future protection conditions to be imposed and the scaling factors to be applied are associated with each trigger class, and these govern the operation of the trigger. In order to do this straighforwardly, it is envisaged that each trigger class brings with it a block of electronics repeated according to the number of allowed concurrent trigger classes.

In ALICE, it is envisaged that a Local Trigger Unit (LTU) will act as the interface between the CTP and each sub-detector's front-end electronics. This unit will also allow sub-detectors to work in stand-alone mode, providing the correct sequence of signals from a  pulser input. This allows each sub-detector group to operate autonomously throughout the development and installation stages.

A new evaluation of the physics aims for the ALICE trigger is in progress, which will lead to a clearer idea of the trigger requirements. The originally proposed numbers for inputs and classes are close to the practical limits for a completely general system. A   re-appraisal of the CTP is in progress, The final numbers in the system parameters, and the restrictions, if any, to be applied, are being determined.

An optical link interface for the Atlas Tile-Calorimeter

Daniel Eriksson, Jonas Klereborn, Magnus Ramstedt and Christian Bohm
University of Stockholm, Sweden

Abstract

An optical (1300 nm) link interface has been developed in Stockholm for the Atlas Tile-Calorimeter. The link serves as a readout for one entire TileCal drawer, i.e. with up to 48 front-end channels. It is also contains a receiver for the TTC clocks and messages distributing these to the full digitizer system. Digitized data is serialized in the digitizer boards and supplied with headers and CRC control fields. Data with this protocol is then sent via G-link to an Odin S-link receiver card where it is unpacked and parallelized in a specially developed Altera code. The entire read-out part of the interface has been duplicated for redundancy with two dedicated output fibers. The TTC distribution has also been made redundant by using two receivers (and two input fibers) both capable of distributing the TTC signal. A high pass filter tuned to the frequency of an active TTC-link, decides which receiver to use. To decrease the sensitivity to radiation the complexity of the interface has been kept at a minimum. This is also beneficial to the system cost. To facilitate the mechanically installation the interface has been given an L-shape so that it can be mounted closely on top of one of the digitizer boards without interfering with its components.

Summary

The interface link functions as both data read out and TTC distribution for up to 48 front end channels. The basic design idea of the interface card is move as much logic as possible outside the detector, where it's not exposed to radiation.

Since there is very little room in the middle of the Tile-Calorimeter electronics drawer the interface card has been made as small as possible. To minimize the combined height of the front end electronics plus the interface card, the interface card has been designed almost like a mezzanine card, leaving room for the necessary cables in the drawer interconnection. The card has an L shape to enable the connection of the data input cables after mounting the interface card and still be able to use a regular data output connector. The card use only 3.3V taken directly from the digitizer board beneath via a purpose mounted 8 pin connector.

A passive high pass filter senses which TTC input channel to use. A functioning TTC signal will force an enable signal high. If the TTC signal fails, the frequency will with high probability decrease enabling the other channel. Since it only uses discrete components, the filter is very radiation tolerant.

The present card use the HDMP 1032 G-Link chip from Agilent. This is specified to run up to 1.4 Gbaud, which is less than 32 bit data at 40 MHz. We use presently 20MHz, which is adequate for the needs of the digitizer system.

The high speed lines to the VCSEL cathodes are very sensitive to noise, and must be made as short as possible. Therefore, a reciever card was placed on top of the interface card. This will also improve the iimpedance definition of the VCSEL connections.

To get a PIN-TIA operating at 3.3 V we had to use separate components. Instead of having the TIA integrated with the diode, we used a PIN diode and a separate TIA chip. Since we use lvds repeaters, a complete optic receiver IC is more than we need. A simple PIN-TIA gives an lvds compatible signal, significantly reducing space and cost. The transmitter is based on the MAX3286 laser driver. This is a compact solution well suited to the requirements of the board.

Full bit error rate and radiation tests will be conducted during the summer.

Hopefully, the next version of the interface card will use the G-link clone GOL chip developed by CERN Microelectronics Group. We will also try to find a 3.3 V PIN-TIA

Tests and Production of the ATLAS Tile Calorimeter Digitizer

Jonas Klereborn, Magnus Ramstedt, Svante Berglund, Christian Bohm,
Kerstin Jon-And, Sam Silverstein.
Stockholm University

Abstract

After a successful pre-production series the full scale production of the Tile-Cal digitizer will begin during the summer of 2001. To be able to ensure functionality and quality a test scheme has been developed Before production all components have been radiation tested. After mounting the component the digitizer is tested at the producer in a specially designed reduced test-bench to verify the functionality. All digitizers are then passed through burn-in and are tested again in a full test-bench reproducing operational conditions using a custom designed software, which ensures that full functionality is maintained. Test data is stored in an auto-generated file for future reference. A similar test software is later used at Clermont-Ferrand where the drawer containing all detector electronics are assembled. Their test results
will be cross-referenced with the original test data entry.

Summary

During both neutron and ionizing radiation test the TileDMU, a gate array which is responsible for most of the digitizer functionallity, was continuously tested with an external test-bench and no errors was registered. All other components have been radiation tested where failing component types have been replaced by equivalent components with better radiation tolerance.

All TileDMUs are tested on the wafer and then more thoroughly after the packaging. The boards are tested for continuity and against unintentional shorts. A special test-bench has been developed for producing realistic stimuli to the mounted digitizer boards checking most of the functionality. Failing boards are diagnosed and fixed if the errors are simple. The delivered boards are then subjected to a Burn-in procedure for one week in 70 degrees centigrade while the boards are powered up.

Subsequent system tests use an Atlas TileCal drawer as test-bench. It is supposed to verify full functionality in Atlas, making sure that the board fulfils all specifications. All known previously encountered or envisaged malfunctions of the digitizer system can be detected automatically by the tests. They reproduce the production operation of the digitizers in the Atlas environment. For future references the full test reports of the boards are saved in a auto generated html file.

Calculated test time per board is 20 min giving 120 boards per week. The burn-in oven has 120 digitizer slots and last for one week. Therefor we
will just have one week extra latency because of the burn-in but no further delay. Boards that not pass the test are just put aside and easy
bugs will later be fixed. In case of need, the other malfunctioning boards will be fixed.

Design and Test of the Track-Sorter-Slave ASIC for the CMS Drift Tube Chambers

Authors
G.M.Dallavalle, A.Montanari, F.Odorici, R.Travaglini
INFN and University, Bologna, Italy

Oral presentation: F. Odorici (INFN Bologna)
Conference Topic: High Energy Physics Instrumentation
Fabrizio.Odorici@bo.infn.it

Abstract

Drift Tubes Chambers (DTCs) are used to detect muons in the CMS barrel. Several electronic devices installed on the DTCs will analyse data every bunch crossing, in order to produce a trigger decision. In particular, the Trigger Server system has to examine data from smaller sections of a DTC, in order to reduce the chamber trigger output by a factor of 25. The basic elements of the Trigger Server system are the Track-Sorter-Slave (TSS) units, implemented in a 0.5 micron CMOS ASIC. This paper describes the TSS ASIC, with emphasis on the methodology used for design verification with prototypes and IC simulation and test.

Summary

In the CMS muon barrel the Drift Tubes Chambers (DTCs) represent an important detector to produce a trigger decision. Several electronic devices installed on the DTCs will analyse data every bunch crossing, in particular the Trigger Server system has to examine data from smaller sections of a DTC.

The Trigger Server is implemented as a two-stage sorting system and has the task to complete the muon segments selection initiated by the previous DTC trigger stages. The basic elements of the Trigger Server system are the Track-Sorter-Slave (TSS) units, implemented in a 0.5 micron CMOS ASIC.

In the IC design particular effort has been devoted to speed optimization (event processing has to be completed within 25 ns), programmability and monitoring. Programmability allows to choose among different processing options, depending on the local trigger demands of each DTC section, and permits to partially cover for malfunctioning trigger channels. Since TSS units will be hosted onto the DT chambers and their access will not be easy nor frequent, much effort has been dedicated to redundancy of remote programming and monitoring logic. In particular, two independent access protocols, via serial JTAG and/or via an ad-hoc 8-bit parallel interface, allow programming and exhaustive monitoring of each device.

In order to master and verify the considerable design complexity, the TSS unit has been realized by following a joined approach between IC simulation and prototype testing phases. In both phases we adopted a common base of software tools, developed in order to provide an event generator, a device emulator and an output comparator. The hardware test tool was based on a programmable I/O Pattern Unit module, able to operate at the LHC bunch crossing frequency, that we designed as a general testing tool for digital electronic devices.

High-speed multichannel ICs for front-end electronics systems

A.Goldsher*, Yu.Dokuchaev*, E.Atkin**, Yu.Volkov** 
*-- State unitary enterprise “Science and Technology Enterprise “Pulsar”,
Russia, 105187, Moscow, Okruzhnoy proezd, 27.

** -- Moscow State Engineering Physics Institute (Technical University),
Russia, 115409, Moscow, Kashirskoe shosse, 31. 

Abstract

 The basic set of high-speed multichannel analog ICs for front-end electronics systems, designed and put into production in Russia, is described. It is implemented as a number of application specific ICs (ASIC) and ICs, based on an application specific semicustom array (ASSA).
By their electrical parameters the created ICs are on a par with foreign functional analogs. The prospects of their further development are expounded. 

Summary 

1. Contemporary front-end electronics systems, intended, particularly, to carry out research in high-energy and elementary particle physics, show an increase in the number of data collecting and processing channels, reaching nowadays some hundreds thousand and expected to reach several millions during the nearest 5…7 years.

2. At present the basic set of ICs particularly includes:
·        an ASIC, containing a high-speed comparator and D-trigger, intended for application in high-speed (fractions of nanosecond) timing circuits;
·        a four-channel ASIC of an amplifier-shaper with differential input and output, intended for processing the amplitude data (amplification and filtering);
·        a four-channel ASIC of a differential low-power comparator of the nanosecond range, intended for analog signal discrimination;
·        a four-channel ASIC of a differential comparator of the nanosecond range, having an output stage with open collector and implementing the OR-function with four inputs.

3. The LSIC, implemented on the basis of an analog ASSA, containing 7000 components, among them about 1400 n-p-n transistor structures with a unity gain frequency f_UG ~7.0GHz, includes 8 channels, collecting and processing the signals of wire tracking detectors. Each of the channels contains a low-noise preamp, a linear shaper, comparator, output driver and an OR-circuit, common to 8 channels.

4. The printed circuit units (PCU), created on the basis of the above mentioned ASICs and LSICs, by their electric characteristics are on a par with those, implemented with the ASD-8 IC of Pennsylvania University (USA) and used widely at present by physical research centers in the West.

5. The further improvement of ICs for front-end electronics systems is linked with the use of complementary n-p-n and p-n-p high-frequency (f_UG ~5.0GHz) transistor structures and component insulation by dielectrics.

Experiences from the Electronic Commissioning of HERA-B

Bernhard Schwingenheuer, Max-Planck-Institut Heidelberg

Abstract:

In 2000 the HERA-B experiment was for the first time  fully assembled including different trigger levels and the complete data acquisition structure. This talk reviews the design and performance of the electronics involved  starting from the detector readout to the data routing to the PC farm of the Second Level Trigger. Special emphasis is given to concepts which have proven to be successful and to observed deficits.

Summary

 HERA-B has tried to limit the number of electronic components in the experiment. There are only two readout chips used by the tracking detectors (HELIX and ASD8) resulting in two versions of FrontEnd boards (plus one additional one for the calorimeter). The data buffering and data transfer to the Second Level Trigger is implemented with SHARC processors common for all. This concept has proven to work reliably and the limited resources in man power were employed very efficiently.
The HELIX readout chips worked well except for minor difficulties. 
The fast rise time of the ASD8 posed a challenge. Careful grounding of chambers, PCBs and cables was mandatory to avoid oscillations. 

The most complex custom made boards of HERA-B are those of the First Level Trigger. Careful design and a lengthy testing procedure made them robust processors.

The data transmission between the tracking chambers and the First Level Trigger did not fulfill our quality requirements. Especially the custom made optical transmission was unstable and the efforts to improve its performance have not stopped.

The time needed for commissioning strongly depends on the the implemented testing features of the hardware. The amount of software tools needed for commissioning has been underestimated at HERA-B.

The LHC experimental programme - a status report'

 J. Engelen, NIKHEF 

The LHC experimental programme will be briefly reviewed. Special attention wil
be given to the status of the various projects, with a view to the LHC
pilot and physics runs in 2006.

Radiation tolerance and behavior in magnetic field of CAEN HV and LV boards for LHC experiments

G. M. Grieco
C.A.E.N. S.p.A., Via Vetraia 11. I-55049 Viareggio, Italy
E-Mail GRIECO@CAEN.IT, URL http://www.caen.it

The radiation and magnetic field levels at LHC impose severe design criteria and components selection on the power supply systems to guarantee safe and reliable operations. A study of radiation and magnetic field tolerance of CAEN HV and LV boards has been performed. Results of the proton beam tests performed in Louvain-la-Neuve and magnetic field tests performed at CERN are presented. The HV and LV boards have succesfully passed the scheduled tests and can be a good candidate for several LHC experiments.

Electronics for Pixel Detectors

Michael Campbell

Most modern HEP experiments use pixel detectors for vertex finding because these detectors provide clean and unabiguous position information even in a high multiplicity environment. At LHC three of the four main experiments will use pixel vertex detectors. There is also a strong development effort in the US centred around the proposed BTeV experiment. The chips being developed for these detectors will be discussed giving particular attention to the archiectural choices of the various groups. Radiation tolerant deep sub-micron CMOS is used on most cases. In light of predicted developments in the semiconductor industry it is possible to foresee the trends in pixel detector design for future experiments.

Use of Network Processors in the LHCb Trigger/DAQ System

 J.-D. Dufey, R. Jacobsson, B. Jost and N. Neufeld
Cern, Geneva, Switzerland

 Network Processors are a recent development targeted at the high-end network switch/router market. They usually consist of a large number of processing cores, multi-threaded in hardware, that are specialized in analyzing and altering frames arriving from the network. For this purpose there are hardware co-processors to speed-up e.g. tree-lookups, checksum calculations etc. The usual application is in the input stage of switches/routers to support de-centralized packet or frame routing and hence obtain a better scaling behaviour.

In this paper we will present the use of Network Processors for data merging in the LHCb dataflow system. The architecture of a generic module will be presented that has the potential to be used also as a building block of the event-building network for the LHCb software trigger.