*Corresponding author, E-mail: brettel@mppmu.mpg.de

Authors: G. Antchev, E. Cano, S. Cittolin, S. Erhan, W. Funk, D. Gigi, F. Glege, P. Gras, J. Gutleber, C. Jacobs, F. Meijers, E. Meschi, L. Orsini, L. Pollet, A. Racz, D. Samyn, W. Schleifer, P. Sphicas, C. Schwick

Attila Racz <racz@cmsmail.cern.ch>

In the context of the CMS data acquisition system, simple and robust data links are required to transfer data from the underground counting rooms up to the surface buildings where complex processing of the data takes place. In the case of CMS, ~500 of these links, with an individual throughput of 400MB/sec over a distance of 200m, is required. The interface specification for these links as well as recent hardware developments are presented in this paper.

Dr.Sci. Vyacheslav Vinogradov
Institute for Nuclear Research RAS
prosop.60-let october 7-a , Moscow,
117312 Russia
vin@inr.troitsk.ru
( 3340190
Fax 3340184

Abstract

Modular approach to development of Distributed Modular System Architecture for Detector Control, Data Acquisition and Trigger Data processing is proposed. Multilevel parallel-pipeline Model of Data Acquisition, Processing and Control is proposed and discussed. Multiprocessor Architecture with SCI-based Interconnections is proposed as good high-performance System for parallel-pipeline Data Processing. Tradition Network (Ethernet –100) can be used for Loading, Monitoring and Diagnostic purposes independent of basic Interconnections. The Modular cPCI –based Structures with High-speed Modular Interconnections are proposed for DAQ and Control Applications. Distributed Control RT-Systems. To construct the Effective (cost-performance) systems the same platform of Intel compatible processor board should be used.

Basic Computer Multiprocessor Nodes consist of high-power PC MB (Industrial Computer Systems), which interconnected by SCI modules and link to embedded microprocessor-based Sub-systems for Control Applications. Required number of Multiprocessor Nodes should be interconnected by SCI for Parallel-pipeline Data Processing in Real Time (according to the Multilevel Model) and link to RT-Systems for embedded Control/

Institute of Physics of Azerbaijan Republic Science Academy,

370143, Baku, Husseyn Javid Avenue, 33.

State Oil Academy of Azerbaijan Republic,

370010, Baku, Azadlig avenue, 20.

E. M. Kerimova, S.N. Mustafaeva, S.I. Mekhtieva, S.M. Bidzinova, N. Z. Gasanov, A. I. Gasanov

Institute of Physics,
Academy of Sciences of Azerbaijan,
G. Javid Prospect,
33,370143 Baku, Azerbaijan
E-mail:_Physics @_lan.ab.az

This paper deals with the investigation of optical properties of TlGaS₂, TlInS₂, TlGaSe₂ single crystals and influence of Fe and Cu doping and also intercalation by Li ions on these properties. The following main results have been obtained.

Intercalation of TlGaSe₂ single crystals by Li ions brings about the shift of energy position of exciton absorption peak, related with direct transition to long-wave side of spectrum. In particular at 5K this energy shift is D E=15 meV. As a result of intercalation the coefficient of temperature shift of this exciton peak decreased half as many in absolute value and is ¶ E^ex/¶ T within the range 20£ T£ 105 K and -0.25^.10^-4 eV/K at 5£ T£ 20 K.

Study of absorption spectra of TlM_1-xFe_xS₂ (M-In,Ga) single crystals in wide temperature range 5¸ 200K showed, that, in particular the width of bandgap of TlGa_1-xFe_xS₂ (x=0.001; 0.005; 0.01) crystals as of TlGaS₂ crystals increases with temperature rise. For TlGa_0.999Fe_0.001S₂ there have been observed exciton absorption band (hn =2.58eV at T=5K) which with temperature rise is broadened and shifted to side of higher energy. There have been also determined values of direct optical transition in TlIn_1-xFe_xS₂ (x=0.005; 0.01) single crystals at 5 and 300K.

Study of exciton absorption spectra of TlInS₂ single crystals doped by Cu showed that doping leads to the shift of energy position of exciton peak to long-wave region and it also increases exciton bond energy at the absorption edge: if for TlInS₂ =20meV, for Tl_0.995Cu_0.005InS₂ =31meV, for Tl_0.985Cu_0.015InS₂ =54meV. Bohr radius of exciton and its effective mass are calculated.

Thus, doping and intercalation of TlMC₂^VI leads to modification of their absorption spectra, change of exciton characteristics, i.e. allow optical properties to be controlled.

B. Hallgren, H. Burckhart, H. Kvedalen

CERN, EP-ATI/CS
Bjorn.Inge.Hallgren@cern.ch
Hallvard.Kvedalen@cern.ch
Helfried.Burckhart@cern.ch

The ELMB is a plug-in board to be used in LHC detectors as a general-purpose system for the front-end control and monitoring. It is based on CANbus, is radiation tolerant and can be used in magnetic fields. Results of the radiation tests will be presented and examples of applications will be described.

Overview of the DMILL ASICs developments for the ATLAS LAr calorimeter

S. Cadeddu, A. Lai*

INFN Sezione di Cagliari, Cittadella Universitaria, 09042 Monserrato
(Cagliari) - Italy

*Corresponding author,
( . Off +39 070 675 4913 * labs. +39 070 675 4973/5/8
Fax +39 070 510212
( . @ CERN +41 22 76 74968 - Bat. 14-04-005

alessandro.cadeddu@ca.infn.it
adriano.lai@ca.infn.it.
http://www.ca.infn.it/~elettro

In order to ensure the radiation tolerance of its front-end electronics located close to the detector, the LArG collaboration has migrated
several COTS and FPGAs into DMILL ASICs. Up to seven digital chips and three analog chips have been submitted in 2000 and tested in the spring of 2001. The measurements results, including several irradiation and SEU tests will be summarized as well as the production issues.

C. de La Taille, J.P. Richer, N. Seguin-Moreau, L. Serin LAL Orsay FRANCE

Christophe de LA TAILLE
Laboratoire de l'Accelerateur Lineaire
Centre d'Orsay - bat
F 91 898 ORSAY Cedex
taille@lal.in2p3.fr
( : (33) 1 64 46 89 39
Fax: (33) 1 64 46 89 34

In order to calibrate the LAr calorimeter to 0.25% accuracy, precision pulsers have been designed to provide a fast and precise pulse that simulates the detector pulse over its full 16bit dynamic range. They are based on a precision DC current source (2mA-200mA) built with a low offset opamp and a 0.1% 5ohm external resistor. Several COTs having failed the irradiation tests, a custom chip has been designed and fabricated, first in AMS 0.8um BiCMOS and then in DMILL. It has been successfully tested and the electrical performance and irradiation results will be shown."

R. Kluit, P. Timmer, J.D. Schipper, V. Gromov; NIKHEF Amsterdam

r.kluit@nikhef.nl
A.P. de Haas; NIKHEF Utrecht

The design of the control electronics of the front-end of the ALICE SSD is described. This front-end is build with the HAL25 (LEPSI) chip. The controls are placed in the ladder EndCap. The main EndCap functions are power regulation and latch-up protection for the front-end, control functions for the local JTAG bus, distribution of incoming control signals for the front-end and buffering of the outgoing analog detector data. The system uses AC-coupled signal transfer for double-sided detector readout electronics.
Due to radiation-, power-, and space requirements, two ASIC’s are under development, one for analog buffering and one with all other functions combined.

P. Moreira (1), T. Toifl (2), A. Kluge (1), G. Cervelli (1), F. Faccio (1), A. Marchioro (1) and J. Christiansen (1)

1. CERN-EP/MIC, Geneva, Switzerland
2. IBM Research, Zurich, Switzerland

Correspondin author:
Paulo Moreira, EP Division, CERN
Email: Paulo.Moreira@cern.ch

Gbit/s data transmission links will be used in several LHC detectors in trigger and data acquisition systems. In these experiments, the transmitters will be subject to high radiation doses over the experiment's lifetime. In this work, a radiation tolerant transmitter ASIC is presented. It supports two standard data transmission protocols, the G-Link and the Gbit-Ethernet, and sustains transmission of data at both 800 Mbit/s and 1.6 Gbit/s. The ASIC was implemented in a mainstream 0.25um CMOS technology employing radiation tolerant layout practices. A prototype was tested and its behavior under total dose irradiation as well as its susceptibility to single event upsets was studied. The experimental results are reported in the paper.

Authors list:
Niels van Bakel, Jo van den Brand, Hans Verkooijen
(Free University of Amsterdam / NIKHEF Amsterdam)

Daniel Baumeister, Werner Hofmann, Karl-Tasso Knoepfle,
Sven Loechner, Michael Schmelling
(Max-Planck-Institute for Nuclear Physics, Heidelberg)

Martin Feuerstack-Raible
(University of Heidelberg)

Neville Harnew, Nigel Smale
(University of Oxford)

Edgar Sexauer
(now at Dialog Semiconductors, Kirchheim-Nabern, Germany)

Daniel Baumeister
baumeis@asic.uni-heidelberg.de

MPI for Nuclear Physics Heidelberg
ASIC laboratory
Schroederstr. 90
D-69120 Heidelberg
(: ++49 6221 544324
Fax : ++49 6221 544345

The Beetle front end chip for LHCb is a 128 channel pipeline chip developed in 0.25 um standard CMOS technology. After intensive testing of the first version (Beetle1.0), an improved design (Beetle1.1) has been submitted in March 2001. The key measurements on the Beetle1.0, which mainly drove the design changes for the Beetle1.1, are described together with first performance data of the new chip.

John W. Dawson, David J. Francis, William N. Haberichter,and James L. Schlereth

Argonne National Laboratory and CERN
John.Dawson@cern.ch

The TTCPR receiver is a mezzanine card intended for use in distributing TTC information to Data Acquisition and Trigger Crates in the Atlas Prototype Integration activities. An original prototype run of these cards was built for testbeam and integration studies, implemented in both the PMC and PCI form factors, using the TTCrx chips from the previous manufacture. When the new TTCrx chips became available, the TTCPR was redesigned to take advantage of the availability and enhanced features of the new TTCrx, and a run of 20 PMC cards was manufactured, and has since been used in integration studies and the testbeam. The TTCPR uses the AMCC 5933 to manage the PCI port, an Altera 10K30A to provide all the logic so that the functionality may be easily altered, and provides a 4K deep FIFO to retain TTC data for subsequent DMA through the PCI port. In addition to DMA's which are mastered by the Add On logic, communication through PCI is accomplished via mailboxes, interrupts, and the Pass-thru feature of the 5933. An interface to the I2C bus of the TTCrx is provided so that internal registers may be accessed, and the card supports reinitialization of the TTCrx from PCI. Software has been developed to suport operation of the TTCPR under both LynxOS and Linux.

S. Zimmermann, J. Andresen, J.A. Appel, G. Cardoso, D.C. Christian, B.K. Hall, J. Hoff, S.W. Kwan, A. Mekkaoui, R. Yarema.

Sergio Zimmermann
Fermi National Accelerator Laboratory
Computing Divison/Electronic Systems Engineering Dept.
P.O. Box 500
Batavia, IL 60510
USA
e-mail: zimmer@fnal.gov
( : (630) 840-4276
fax: (630) 840-8208

At Fermilab, a pixel detector multichip module is being developed for the BTeV experiment. The module is composed of three layers. The lowest layer is formed by the readout ICs. The back of the ICs are in thermal contact with the supporting structure while the other side is bump-bonded to the pixel sensor. A low mass flex-circuit interconnect is glued on the top of this assembly, and the readout IC pads wire-bounded to the flex circuit. This paper will present recent results on the development of a module prototype and summarize its performance characteristics.

Author List:
K. Hasuko(1), C. Fukunaga(5), R. Ichimiya(3), M. Ikeno(2), Y. Ishida(5), H. Kano(5), Y. Katori(1), T. Kobayashi(1), H. Kurashige(3), K. Mizouchi(4), Y. Nakamura(1), H. Sakamoto(4), O. Sasaki(2) and K. Tanaka(5)

(1) International Center for Elementary Particle Physics (ICEPP), University of Tokyo
(2) High Energy Accelerator Research Organization (KEK)
(3) Department of Physics, Kobe University
(4) Department of Physics, Kyoto University
(5) Department of Physics, Tokyo Metropolitan University

University of Tokyo
7-3-1 Hongo
Bunkyo-ku, Tokyo 113-0033, JAPAN

hasuko@icepp.s.u-tokyo.ac.jp
www.icepp.s.u-tokyo.ac.jp/~hasuko

We present the development of a remote control system for on-detector VME modules of the ATLAS endcap muon trigger. The system consists of a local controller in an on-detector VME crate and a remote interface in a Readout Driver crate. The controller and interface are connected with dedicated optical links based on G-LINK. The control system can fully configure and control modules, especially FPGA-embedded ones using G-LINK words and VME bus from remote host. The system supports periodical readback and reconfiguration to assure correct configuration data against SEUs. The idea, prototype and initial performance tests of the system are discussed.

G. Hallewell, Centre de Physique des Particules de Marseille
S. Kersten, University Wuppertal
Susanne.Kersten@cern.ch

The pixel detector of the ATLAS experiment at the CERN LHC will contain around 1750 individual detector modules. The high power density of the electronics - requiring an extremely efficient cooling system – together with the harsh radiation environment constrains the design of the detector control system.

An evaporative fluorocarbon system has been chosen to cool the detector. Since irradiated sensors can be irreparably damaged by heating up, great emphasis has been placed on the safety of the connections between the cooling system and the power supplies. An interlock box has been developed for this purpose, and has been tested in prototype form with the evaporative cooling system.

We report on the status of the evaporative cooling system, on the plans for the detector control system and upon the performance and irradiation tests of the interlock box.

Authors :
Yasuo Arai
KEK, National High Energy Accelerator Research Organization
Institute of Particle and Nuclear Studies
1-1 Oho, Tsukuba, Ibaraki 305-0801, JAPAN
( +81-298-64-5366, fax +81-298-64-2580
yasuo.arai@kek.jp
and
T. Emura
Tokyo University of Agriculture and Technology

ATLAS Muon TDC (AMT) LSI has been successfully developed and performance of a prototype chip (AMT-1) was reported in the LEB 2000. A new AMT chip (AMT-2) was developed aiming for mass production. The AMTs were processed in a 0.3 um CMOS Gate-Array technology, To proceed to a mass production of 400 k channels (~17,000 chips) scheduled in 2002, a systematic test methods must be established. Furthermore, the chip must be qualified to have adequate radiation tolerance in ATLAS environment. The test method and results of the radiation tests for gamma rays and charged particles will be presented.

M. IMORI
( : +81 3 3815 8384
Fax: +81 3 3814 8806
E-mail: imori@icepp.s.u-tokyo.ac.jp

ICEPP
University of Tokyo
7-3-1 Hongo,
Bunkyo-ku,
Tokyo 113-0033, Japan

The article describes a network of high voltage power supplies which can work efficiently under a magnetic field of 1.5 tesla. The high voltage power supply incorporates a piezoelectric ceramic transformer. The power supply includes feedback to stabilize the high voltage output, supplying from 2000V to 4000V with a load of more than 20 megohm at efficiency higher than 50 percent. The high voltage power supply includes a Neuron chip, a programming device processing a variety of input and output capabilities. The chip can also communicate with other Neuron chips over a twisted-pair cable, which allows establishing a high voltage control network consisting of a number of power supplies each of which incorporates the chip individually. The chip sets the output high voltage. The chip detects the short circuit of the output high voltage and controls its recovery. The chip also monitors the output current. The functions of the power supply under the control of the chip are managed through the network. The high voltage power supplies are networked, being monitored and controlled through the network.

Authors: Jose Castelo, Vicente Gonzalez, Enrique Sanchis
IFIC and Dpt of Electronic Engineering. University of Valencia

Vicente Gonzalez
DSDC - Grupo de Diseño de Sistemas Digitales y de Comunicación
Dept. Ingenieria Electronica. Universitat de Valencia
vicente.gonzalez@uv.es

Abstract

"This works describes the present status and future evolution of the Read Out Driver for the ATLAS Tile Calorimeter. The developments currently under execution include the test of the adapted LAr ROD to Tile Cal needs and the design and implementation of the PMC board for algorithm testing at ATLAS rates. We will describe the test performed at University of Valencia with the LAr ROD motherboard and a new developped transition module with 4 SLINK inputs and one output which match the initial TileCal segmentation for RODs. We will also describe the work going on with the design of a DSP based PMC with SLINK input for real time data processing to be used as a test environment for optimal filtering."

N.Smale, M.Adinolfi, J.Bibby, G.Damerell, N.Harnew, S.Topp-Jorgensen
University of Oxford, UK

V.Gibson, S.Katvars, S.Wotton
University of Cambridge, UK

K.Wyllie
CERN, Switzerland

Development of a front-end readout system for the LHCb Ring Imaging Cherenkov (RICH) detectors is in progress. The baseline solution for the RICH detector readout electronics is the HPD Binary Pixel chip. This paper describes a system to transmit data with addresses, error codes and synchronisation from a radiation harsh environment. The total data read out in 900ns is 32x36x440 bits per L0 trigger, with a sustained L0 trigger rate of 1MHz. Multimode fibres driven by VCSEL devices are used to transmit data to the off-detector Level-1 electronics located in a non-radiation environment. This data is stored in 64Kbit deep QDRbuffers.

Agapito J. A.³, Cardeira F. M. ² , Casas J. ¹ , Fernandes A. P. ² , Franco F. J. ³ , Gomes P. ¹, Goncalves I. C. ² , Cachero A. H. ³ , Lozano J. ³, Marques J. G. ² , Paz A. ³, Ramalho A. J. G. ², Rodriguez Ruiz M. A. ¹ and Santos J. P. ³.

A study of several comercial instrumentation amplifiers (INA110, INA111, INA114, INA116, INA118 & INA121) under neutron and very low gamma radiation was done. Some parameters (Gain, CMRR, input offset voltage, input bias currents) were measured on-line and bandwith, slew rate and supply current were determined before and after radiation. Different digital-to-analog and analog-to-digital converters were tested under radiation . Finally, the results of the testing of some voltage reference and analog switchs will be shown.

Helio Takai and James Kierstead
Brookhaven National Laboratory
takai@bnl.gov

The power supplies for the ATLAS liquid argon calorimeter using 300V input DC-DC converters will be located in a high radiation environment. Over the life of the experiment (i.e. 10 years) the total ionizing dose is expected to reach 25 krad. Along with the total dose is a projected total fluence of 2x10^12 particles/cm^2 of 1 MeV equivalent neutrons of which a fraction of the total neutron fluence, 1x10^11 neutrons/cm^2, has energies above 20 MeV. These values include the standard ATLAS recommended safety factors. The anticipated effects in order of potential seriousness are: (a) single event burnout (SEB) of the input power MOSFET, (b) total dose effects on active CMOS and bipolar components and (c) neutron induced lattice displacements causing conductivity and other changes in active components. The power supply will also be subjected to a magnetic field at a strength of 50 Gauss.

Tests performed on commercially available modules manufactured by Vicor found that none satisfy the requirements. Therefore we are seeking a solution that involves a semi-custom design. This typically introduces questions of reliability and cost. The approach for the development of a prototype is to select a vendor with experience in designing power supplies for radiation environments, e.g. space environments. This provides some assurance that the power supply will be hardened to ionizing and neutron radiation. Then to reduce cost, the radiation hardened power MOSFET will be replaced with a less expensive commercial power MOSFET. It is known that by operating a commercial MOSFET at a lower (derated) voltage it is possible to use them safely in an environment with high-energy particles. For instance a 600 volt MOSFET operated at 500 volts might show a large SEB cross section but has a negligible SEB cross section at 300 volts.

We will report on the progress of the design and comment on the different practical issues of the process such as purchasing of components in lots and specifying parts. Results of power MOSFET qualification will also be presented as well as preliminary test results. Packaging and operational issues will also be discussed as time allows.

Jean-Michel Sainson
SI Engineering & Support
CERN - IT Division CE Group
CH - 1211 Genève 23
( :(41) 22 767 75 61
Fax:(41) 22 767 71 55
SUISSE / SWITZERLAND
mailto:J-M.Sainson@cern.ch
Intranethttp://cern.ch/support-specctraquest/

Because of increasing clock frequencies, faster rise times and wider busses, printed circuit board (PCB) design layout becomes an issue. The Cadence® SPECCTRAQuest™ SI (signal integrity) package allows the pre- and post-layout signal integrity analysis of a PCB designed in the Cadence flow under Allegro. Case studies of work done for some LHC detectors will be presented. These will show how the tools can help Engineers in design choice, optimizing electrical performance of board layout, to reduce prototype iterations and to improve production robustness. Examples will include work done on PCI 66MHz and GTL busses.

Antinori, F.(1,2), Ban, J.(3), BURNS, M.(1), Campbell, M.(1), CHOCHULA, P.(1, 4), Formenti, F.(1), Kluge, A.(1), Meddi, F.(1, 7), Morel, M.(1), Petra, Rober to, Snoeys, W.(1), Stefanini, G.(1), Wyllie K.(1).

(For the ALICE Collaboration)

Described is a system that has been developed for testing the ALICE Silicon Pixel Detector Readout Chip. It is capable of covering all aspects of testing, from the selection of know good dies on a wafer, characterisation, and as a DAQ when performing beam tests Considerable effort has been invested in the software to provide a comprehensive suit of facilities and test routines to enable the complete testing and characterisation of the device. In this paper we would like to present the objectives and requirements of the test system, a description of the hardware, software and database and present some of the results obtained.

N. Bondar*, T. Ferguson**, A. Golyash*, V. Sedov*, N.Terentiev**
bondar@fnal.gov
* Petersburg Nuclear Physics Institute, Gatchina, 188350, Russia
** Carnegie Mellon University, Pittsburgh, PA, 15213, USA

The very front-end electronics system for the anode signals of the CMS Endcap Muon cathode strip chambers has been designed. Each electronics channel consists of an input protection network, amplifier, shaper, constant-fraction discriminator, and a programmable delay with an output pulse width shaper. The essential part of the electronics is an ASIC consisting of a 16-channel amplifier-shaper-discriminator (CMP16). The ASIC was optimized for the large cathode chamber size (up to 3 m x 2.5 m) and for the large input capacitance (up to 300 pf). The ASIC combines low power consumption (30 mW/channel) with excellent time resolution (~2 ns). A second ASIC provides a programmable time delay which allows the alignment of signals with an accuracy of 2.5 ns. The electronics test results, including "on-chamber" test and radiation test, are presented.

C. Posch*, E. Hazen, J. Oliver:
christoph.posch@cern.ch
hazen@bu.edu
oliver@huhepl.harvard.edu

Development and performance of the final 8-channel front-end for the MDT segment of the ATLAS Muon Spectrometer is presented. This last iteration of the read-out ASIC contains all the required functionality and meets the envisaged design specifications. In addition to the basic "amplifier-shaper-discriminator"-architecture, MDT-ASD uses a Wilkinson ADC on each channel for precision charge measurements on the leading fraction of the muon signal. The data will be used for discriminator time-walk correction, thus enhancing spatial resolution of the tracker, and for chamber performance monitoring (gas gain, ageing etc.). The feasibility of the MDT system to perform particle identification through dE/dX measurement using the Wilkinson ADC is evaluated. Results of performance and functionality tests in the lab and on-chamber along with an outlook to volume-production and production testing are presented.

The HAL25 is a mixed low noise, low power consumption and radtol ASIC intended for read-out of Silicon Strip Detectors (SSD) in the ALICE tracker. It is designed in a 0.25 micron CMOS process and is similar in concept to the previous chip ALICE128C. The chip contains 128 channels of preamplifier, shaper and a capacitor to store the charge collected on a detector strip. The analogue data is held by an external logic signal and can be serially read out through an analogue multiplexer. A slow control mechanism based on JTAG protocol was implemented for a programmable bias generator, an internal calibration system and selection of functional modes.

P.Aspell, D.Barney, P.Bloch, A.Go, C.Palomares
Paul.Aspell@cern.ch

DeltaStream is a 36 channel preamplifier and shaper ASIC that provides low noise, charge to voltage readout for capacitive sensors over a large dynamic range. The chip has been designed in the DMILL BiCMOS radiation hard technology for the CMS Preshower project. Two gain settings are possible. High gain (HG), has gain 30mV/MIP (7.5mV/fC) for a dynamic range of 0.1 to 50 MIPS (0.4fC – 200fC) and low gain (LG), has gain 4mV/MIP (1mV/fC) for a dynamic range of 1 to 400 MIPS (4fC – 1600fC). The peaking time is ~25ns and the noise has been measured at ~ENC = 680e + 28e/pF. Each channel contains a track & hold circuit to sample the peak voltage followed by an analog multiplexer operating up to 20MHz. The response of the signal is linear throughout the system. The design and measured results for input capacitance < 55pF are presented.

Authors list with Institutions:
Franco Gonella from Dip. di Fisica dell'Universita' di Padova and Sezione INFN di Padova, Padova, Italy
franco.gonella@pd.infn.it

Matteo Pegoraro from Sezione INFN di Padova, Padova, Italy

Paper category :
LHC Experiment: CMS
LHC Experiment Subsystem: MU
LEB2001 Workshop topic: Electronics for muon detectors

To meet frontend electronics needs of CMS barrel muon chambers a full custom ASIC, named "The MAD", has been first developed by INFN of Padova and then produced in over 50.000 pieces to equip the 180.000 drift tubes. The chip provides 4 identical chains of amplification, discrimination and cable driving circuitry; also it integrates a flexible channel enabling/disabling capability and a temperature probe for monitoring purposes. The ASIC has been deeply tested resulting in good performances; particularly, big effort was put in radiation (neutron, gamma rays and ions) and ageing tests to check behavior and reliability in LHC environment.

M. Ullan*, D. Dorfan*, T. Dubbs*, A. A. Grillo*, E. Spencer*, A. Seiden*,H. Spieler**, M. Gilchriese**, M. Lozano***

*Santa Cruz Institute for Particle Physics (SCIPP)
University of California at Santa Cruz
Santa Cruz, CA 95064, USA
(: 1 831 459 3567
Fax: 1 831 459 5777
E-mail: ullan@scipp.ucsc.edu

**Lawrence Berkeley National Laboratory (LBNL)
University of California at Berkeley
***Centro Nacional de Microelectrónica (CNM-CSIC)
Barcelona, Spain

Ionization damage has been investigated in the IC designed for the readout of the detectors in the Semiconductor Tracker (SCT) of the ATLAS experiment at the LHC, the ABCD chip. The technology used in the fabrication has been found to be free from Low Dose Rate Effects which facilitates the studies of the radiation hardness of the chips. Other experiments have been done on individual transistors in order to study the effects of temperature and annealing, and to get quantitative information and a better understanding of these mechanisms. With this information, suitable irradiation experiments have been designed for the chips to obtain a better answer about the survivability of these chips in the real conditions of the ATLAS detector.

T.Ferguson ferguson@cmuhep2.phys.cmu.edu, N.Terentiev (teren@fn781a.fnal.gov)

(Carnegie Mellon University, Pittsburgh, PA, 15213, USA)

N.Bondar bondar@fnal.gov, A.Golyash, V.Sedov

(Petersburg Nuclear Physics Institute, Gatchina, 188350, Russia)

We report the results of several radiation tests on pre-production samples of the anode front-end electronics boards for the CMS endcap muon system. The crucial component tested was the 16-channel preamplifier ASIC (BiCMOS). The boards were exposed to doses up to 80 krad in a 63 MeV proton beam, and to a neutron fluence up to 2*10**12 n/cm**2 from a nuclear reactor. The static (current and voltage) and dynamic (noise,threshold, gain and timing) characteristics were measured versus the radiation dose.

G.M.Dallavalle, A.Montanari, F.Odorici, G.Torromeo, R.Travaglini, M.Zuffa
INFN and University, Bologna, Italy
Marco.Dallavalle@bo.infn.it

The Track-Sorter-Master (TSM) is an element of the on-chamber trigger electronics of a Muon Barrel Drift Tube Chamber in the CMS detector. The TSM provides the chamber trigger output and access to the trigger electronic devices for monitoring and configuration. The specific robustness requirements on the TSM are met with a partitioned architecture based on antifuse-FPGAs. These have been successfully tested with a 60 MeV proton beam: SEE and TID measurements are reported.

Recent Progress in Field-Programmable Gate Arrays.
by
Peter Alfke, Xilinx, Inc.

Abstract

Some progress is evolutionary, some is revolutionary.
Evolutionary progress is based on improved semiconductor technology, architectural enhancements and more efficient design tools. Over the past 15 years, Xilinx has introduced many FPGA families; only the latest ones are recommended for new designs.
Recent evolutionary improvements are better routing, better clock distribution, better clock management, and faster arithmetic, including fast multipliers.
Recent revolutionary improvements are distributed shift registers, fully synchronous dual-port BlockRAMs, and multi-standard board interfaces. A controlled-output impedance option improves board-level signal integrity and eliminates many external termination resistors. Source-synchronous design eliminates clock skew by routing clock and data together, while bit-serial I/O is self-clocking and can run at up to 3.125 Gigabits/sec ( 2.5 Gbps data), available early 2002. On-chip soft and hard microprocessors expand the range of FPGA capabilities.
This paper gives tips for achieving high performance, signal integrity, and radiation hardened designs, and it closes with a list of valuable URLs and an outlook at FPGA capabilities four years in the future.

Authors :
G.Mazza [INFNTo], M.Idzik[INFNTo], A.Rivetti[UniTo], F.Rotondo[INFNTo]

Institutes :
INFN sezione di Torino, Italy
Universita` di Torino, Italy

G.Mazza
Lab. di Elettronica, Sez. Torino
Via P. Giuria 1
10125 Torino - Italy
( +39 011-6707380
Fax +39 011-6699579
E-mail mazza@to.infn.it

New building blocks have been developed for the electronic readout of the ALICE Silicon Drift Detector. Those blocks include a 10 bit A/D converter with a reduced input capacitance, an 8 bit D/A converter based on the current mirror scheme, a voltage regulator and biasing schemes.
The blocks will be used in the PASCAL chip to improve the performances of the existing prototype and will be the building blocks for the SDD Detector Control System ASIC.
The circuits have been developed in a commercial CMOS 0.25 um technology using radiation tolerant layout techniques.

The front-end prototypes for the electronic readout of the ALICE experiment Silicon Drift Detector have been designed and succesfully tested. Nevertheless, a number of system requirements as minimize dead time, avoid external biasing and develop the Detector Control System have to be addressed. At this purpose, new building blocks have been developed. These blocks include a 10 bit A/D converter, an 8 bit D/A converter based on the current mirror scheme, a voltage regulator and biasing schemes. The A/D converter is based on the successive approximation principle. In order to reduce the input capacitance, the internal DAC has been splitted into a 5 bit main DAC and a 5 bit sub DAC. This arrangement makes possible to reduce the input capacitance of a factor of 8 compared to the previous version. The D/A converter is based on a matrix of 256 current mirrors. This technique relaxes the matching requirements and therefore improves DNL and INL. A transimpedance amplifier has been designed in order to convert the output current into a voltage. The voltage regulator and bias circuits will be integrated in the final front-end ASIC ( named PASCAL ) in order to have no external analog signals in the front-end board. Those components will be also the building blocks for the Detector Control System ASIC which will be located on both ends of the SDD ladder. The circuits have been developed in a commercial CMOS 0.25 um technology using radiation tolerant layout techniques.

P.K.Skorobogatov, A.Y.Nikiforov

Specialized Electronic Systems,
Kashirskoe shosse, 31,
115409, Moscow,
Russia pkskor@spels.ru

Temperature dependence of p-n junction radiation-induced charge collection under 1.06 and 0.53 micrometer focused laser beams was investigated in the temperature range from 22 to 110 C using experiments and numerical simulation. It was shown that in the case of 0.53 micrometer laser irradiation the temperature practically does not affect the collected charge. In the case of 1.06 micrometer laser irradiation the theory and experiments have shown the essential growth (from 2 to 3 times) of collected charge with temperature. The result obtained must be taken into account in device SEE selection for LHC electronic.

P.K.Skorobogatov, A.S.Artamonov, B.A.Ahabaev

Specialized Electronic Systems, Kashirskoe shosse, 31, 115409, Moscow,
Russia pkskor@spels.ru

The dependence of p-i-n diode ionizing current amplitude vs 1.06 micrometer pulsed laser irradiation intensity is investigated. It is shown that analyzed dependence becomes nonlinear beginning with relatively low laser intensities near 10 W/cm2. This effect is connected with the modulation of pi-n diode intrinsic region by laser irradiation. As a result the distribution of electric field becomes non-uniform that leads to decrease of excess carriers collection. The ionizing current pulse form becomes more prolonged and does not repeat the laser pulse waveform. It is necessary to take into account when p-i-n diode is used as a laser intensity dosimeter.

L. Baksay, P. Raics, Zs. Szabó, L. Molnár, G. Pszota
Institute of Experimental Physics, Debrecen University, Debrecen, Hungary

A. Fenyvesi, J. Molnár,
Institute of Nuclear Research (ATOMKI), Debrecen, Hungary

Gy. L. Bencze
Institute of Particle and Nuclear Physics, Budapest, Hungary
CERN, Geneva, Switzerland

L. Brunel
Institute of Experimental Physics, Debrecen University, Debrecen, Hungary
CERN, Geneva, Switzerland

D. Novak
Royal Institute of Technology, Stockholm, Sweden

Abstract

Components (LED light sources, LED driver and controller electronics, lens and video-sensor) of the barrel muon position monitoring system of the LHC CMS experiment have been irradiated with p(17.5 MeV)+Be neutrons. The tests were performed at the MGC-20E cyclotron of ATOMKI (Debrecen, Hungary). The neutron fluences delivered to the components were 2.6E+12 n/cm2 and 8.0E+13 n/cm2 (the expected values for the Barrel Muon and ME1/1 chambers, respectively). Changes of the electrical and optical characteristics were investigated.

This work was supported by the Hungarian National Research Fund (OTKA). Contract Nos.: T026184 and T026178.

Leonid Efimov Efimov@sunhe.jinr.ru [1],
Vito Lenti Vito.Lenti@cern.ch [2]
Orlando Villalobos-Baillie orlandov@mail.cern.ch [3]

for the ALICE Collaboration

Abstract

The design details and test results of a prototype Mutiplicity Discriminator (MD) for the ALICE L0 Trigger electronics are presented. The MD design is aimed at the earliest trigger decision founded on a fast multiplicity signal cut, in both options for the ALICE centrality detector: Micro Channel Plates or Cherenkov counters. The MD accepts detector signals with an amplitude range of plus-minus 2.5 V, base duration of 1.8 ns and rise time of 300-400 ps. The digitally controlled threshold settings give an accuracy better than 0.4% at the maximum amplitude of the accepted pulses. The MD internal latency of 15 ns allows for a decision every LHC bunch crossing period, even for the 40 MHz of p-p collisions.

Giovanni Cervelli
Alessandro Marchioro, Alessandro.Marchioro@cern.ch
Paulo Moreira, pmoreira@sunvlsi.cern.ch
Francois Vasey
CERN, EP Division, CH 1211 Geneva 23, Switzerland

A 3-way Laser Driver ASIC has been implemented in deep-submicron CMOS technology, according to the CMS Tracker design and rad-tolerance requirements. While being optimised for analogue operation, the full-custom IC is also compatible with LVDS digital signalling. It will be deployed for analogue and digital transmission in the 50.000 fibre link of the Tracker. A combination of linearization methods allows achieving good analogue performance (8-bit equivalent dynamic range, over 100MHz), while maintaining wide input common-mode range (±250mV) and limited power dissipation (30mW). The linearly amplified signals are superposed to a DC-current, pre-settable over a wide range (0-60mA). The driver gain is pre-settable via a SEU-robust serial interface. ASIC qualification and system test results are discussed in the paper.

J.J. van Hunen (For the ALICE collaboration)
CERN, European Organization for Nuclear Research
CH - 1211 Geneva 23
Switzerland
Jeroen.van.Hunen@cern.ch
Office : 160-1-012
( : 41-(0)22-7679961
GSM : 41-(0)79-2014785
Fax : 41-(0)22-7679480

The Alice1LHCb front-end chip has been designed in a 0.25um CMOS commercial technology, with special design rules to obtain radiation tolerance, for the ALICE pixel and the LHCb RICH detectors. The chip has been irradiated with low energy protons and heavy ions, to determine the cross-section for Single Event Upsets, and with X-rays to evaluate the sensitivity to the Total Ionizing Dose. We report the results of those measurements. We also report preliminary results of measurements done with minimum ionising particles in a test beam at the CERN SPS.

C.Buttar, I.Dawson, A.Moraes
(University of Sheffield, UK)
Ian.Dawson@cern.ch

One of the consequences of the harsh radiation environments at LHC experiments will be induced-activation of detector systems. This has implications for operation and maintenance scenarios. We have simulated the radiation environment of the ATLAS SCT system and made first estimates on the levels of induced activation of an SCT module. This has included studying both neutron-induced and spallation-induced activation. Dose rates are also obtained and compared to other parts of the ATLAS detector where estimates have also been made.

G. M. Bilei, M. T. Brunetti (corresponding author), F. Ceccotti, B.Checcucci,V. Postolache, A. Santocchia
mariateresa.brunetti@pg.infn.it

A new circuit for the conversion of analogue electrical signals into the corresponding optical ones has been built and tested by the CMS group of Perugia. This opto-hybrid circuit will be used in the read out electronics of the inner barrel part of the CMS tracker. The opto-hybrid is a vetronite circuit equipped with one programmable laser driver chip and up to 3 laser diodes, all being radiation tolerant. The description of the circuit and its performances are reported and discussed.

E. Chesi, A. Clark, W. Dabrowski, D. Ferrere, J. Kaplon, C. Lacasta, J. Lozano, S. Roe, R. Szczygiel, P. Weilhammer, A. Zsenei.
dabrowsk@ftj.agh.edu.pl

We present a new version of 128-channel analogue front-end chip SCT128A for readout of silicon strip detectors. Following the early prototype developed in the DMILL technology we have elaborated a design with the main goal to improve its robustness and radiation hardness. The improvements implemented in the new design are based on experience gained on the DMILL technology while developing the binary readout chip for the ATLAS Semiconductor Tracker. The architecture of the chip and critical design issues will be discussed. The performance of modules built of ATLAS baseline detectors read out by 6 SCT128A chips will be presented and discussed.

K. Gill, R. Grabit, M. Hedberg, J. Troska, F. Vasey and A. Zanet
CERN EP Division.

Corresponding Author :
karl.gill@cern.ch

Dr Jan Troska
(: +41 (0)22 767 2063
Fax: +41 (0)22 767 2800
CERN, EP Division
CH-1211 Geneva 23
Switzerland
Email: jan.troska@cern.ch

The QA programme for the environmental tests of the COTS components for the CMS Tracker Optical link system is presented. These tests will take place in the pre-production and final production phases of the project and will measure radiation resistance, component lifetime, and sensitivity to magnetic fields. The results are summarized from the extensive series of earlier prototype sample testing and the evolution of these small-scale tests to the pre-production final manufacturing tests is outlined.

Jonathan Butterworth, jmb@hep.ucl.ac.uk
Dominic Hayes(*),Dominic.Hayes@ra.gsi.gov.uk
John Lane, jbl@hep.ucl.ac.uk
Martin Postranecky, mp@hep.ucl.ac.uk
Matthew Warren, warren@hep.ucl.ac.uk

University College London, Department of Physics and Astronomy
( * now at Radiocommunications Agency, London )

Martin Postranecky |
( : [00-44]-(0)20-7679 3453
( : [00-44]-(0)20-7679 2000
Fax: [00-44]-(0)20-7679 7145

The design, functionality, description of hardware and firmware and preliminary results of the ROD ( Read Out Driver ) System Tests of the the TIM ( TTC Interface Module ) are described.
The TIM is the standard SCT and PIXEL detector interface module to the ATLAS Level-1 Trigger, using the LHC-standard TTC ( Timing, Trigger and Control ) system.
TIM has been designed and built during the year 2000 and two prototypes have been used since. More modules are being built this year to allow for more tests of the ROD system at different sites around the world.

Z. Guzik, R. Jacobsson and B. Jost
Richard.Jacobsson@cern.ch

To be presented by R. Jacobsson

In this paper we describe the LHCb Timing and Fast Control (TFC) system. It is different from that of the other LHC experiments in that it has to support two levels of high-rate triggers. Furthermore, emphasis has been put on partitioning and on locating the TFC mastership in one type of module: the Readout Supervisor. The Readout Supervisor handles all timing, trigger, and control command distribution. It generates auto-triggers as well as control the trigger rates.
Partitioning is handled by a programmable patch panel/switch introduced in the TTC distribution network between a pool of Readout Supervisors and the Front-End electronics.

The on-detector electronics of the ALICE silicon pixel detector (nearly 10 million pixels) consists of 1,200 readout chips, bump-bonded to silicon sensors and mounted on the front-end bus, and of 120 control (PILOT) chips, mounted on a MCM together with opto- electronic transceivers. The radiation environment in the pixel detector requires radiation tolerant components. The front-end chips are all ASICs designed in a commercial 0.25 micron CMOS technology using radiation hardening layout techniques. An 800 Mbit/s Glink- compatible serializer and laser diode driver, also designed in the same 0.25 micron process, is used to transmit data over an optical fibre to the control room where the actual data processing und event building are performed. We describe the system and report on the status of the PILOT system.

CERN
CH-1211 Geneva 23
Bat 14-4-006
( : +4122 767 6152
Fax: +4122 767 9425
Email: Danielle.Moraes@cern.ch

Pos-Graduacao
Instituto de Fisica - UFRJ
Cidade Universitaria - CP 68528
21945-970 Rio de Janeiro - RJ, Brasil
( : +5521 562-7463
Fax: +5521 562-7368
Email: danielle@if.ufrj.br

D. Moraes(1,2), F. Anghinolfi(1), W. Bonivento(1), P. Jarron(1),
W. Riegler(1), B. Schimdt(1), F. Vinci dos Santos(1),

(1) CERN, CH-1211 Geneva 23, Switzerland
(2) Univ. Federal do Rio de Janeiro, C.P. 68528, BR-21945-970 Rio de Janeiro, Brazil

We present recent results of an ASD frontend development in 0.25um CMOS for the LHCb muon chambers. Characteristic features of the chip are a peaking time of 10ns, input resistance of <10 Ohm, a noise of 500+39e-/pF and a fast tail cancellation shaper. We present results of a 14 channel amplifier+discriminator submission showing crosstalk and parameter variations. A negative polarity preamp version suitable for wire readout and results from a fast 2x pole/zero tail cancellation shaper are also shown.

The unit is designed to control and monitor the front end electronics, and to collect and ship data onto the Detector Data Link (optical fibre). Handling and distribution of the central trigger is also done, with the use of the onboard mounted TTCrx chip. For the prototype of the RCU the Altera EP20K400 FPGA has been used for application specific system integration.

N. Almeida, V. Antonio, N. Cardoso, A. Correia, P. Machado, J. C. Silva, I.Teixeira, J. Varela,
LIP, Lisbon and INESC, Lisbon
joao.varela"@cern.ch

The Data Concentrator Card is a module in the CMS Electromagnetic Calorimeter Readout System responsible for data collection in a readout crate, verification of data integrity and data transfer to the central DAQ. The DCC should sustain an average data flow of 200 Mbyte/s. In the first part of the paper we summarize the physics requirements for the ECAL readout and give results on the expected data volumes obtained with the CMS detector simulation (ORCA software package). In the second part we present the module's design architecture and the adopted engineering solutions. Finally we give results on the expected performance derived from a detailed simulation of the module's hardware.

Authors
J. Troska, K. Gill, R. Grabit, M. Hedberg, F. Vasey and A. Zanet
CERN
A. Go
Department of Physics, National Central University, Taiwan
M.-L. Chu
High Energy Physics Laboratory, Institute of Physics, Academia Sinica, Taiwan

Corresponding Author
Jan Troska jan.troska@cern.ch
( : +41 (0)22 767 2063
Fax: +41 (0)22 767 2800

CERN, EP Division
CH-1211 Geneva 23, Switzerland

Prototype analogue optohybrids have been designed and built for the CMS Tracker Outer Barrel and End Cap detectors. The total requirement for both types in CMS is 12900 that will be assembled between 2002 and 2004. Using very close to final optoelectronic and electronic components several optohybrids have been assembled and tested using standardised procedures very similar to those to be implemented during production. Analogue performance has met the specifications in all cases when operated in isolation and when inserted into the full prototype optical readout system.

Daniel Dzahini, for the ATLAS Liquid Argon Collaboration
Institut des Sciences Nucléaires
53 avenue des Martyrs,
38026 Grenoble Cedex France
dzahini@isn.in2p3.fr

A high speed digital optical data link has been developed for the front-end readout of the ATLAS electromagnetic calorimeter. It is based on a commercial serialiser commonly known as Glink, and a vertical cavity surface emitting laser. To be compatible with the data interface requirements, the Glink must be coupled to a radhard multiplexer that has been designed in DMILL technology to reduce the impact of neutron and gamma radiation on the link performance. This multiplexer features a very sever timing constraints related both to the Front-End Board output data and the Glink control and input signals. The full link has been successfully neutron radiation tested by means of a custom Bit ERror Tester.

Authors:
H.J.Burckhart, J.Cook, B. Hallgren, F.Varela, CERN-EP
Viatcheslav Filimonov, PNPI, St.Petersburg, Russia

Dr. Helfried Burckhart
European Laboratory for Particle Physics
CERN, EP
CH-1211 Geneva 23
( : (+41) 22 767 12 54
Fax: (+41) 22 767 83 50

Helfried.Burckhart@cern.ch
James.Cook@cern.chZ
Fernando.Varela.Rodriguez@cern.ch
Bjorn.Inge.Hallgren@cern.ch

The ATLAS Detector Control System (DCS) consists of two main components:

a distributed supervisor system, running on PCs, and the different front-end systems. For the former the commercial SCADA package, PVSS-II, has been chosen together with the CERN Joint Controls Project, JCOP. For the latter, a general purpose I/O concentrator called the "Embedded Local Monitor Board" (ELMB) has been developed, which is based on the CAN fieldbus. The paper describes a full vertical slice of the DCS, including the interplay between the ELMB and PVSS-II. Examples of typical control applications will be given.

Authors :
G.Magazzu' - INFN Sezione di Pisa
A.Marchioro, P.Moreira - CERN

A key component for monitoring environmental parameters like temperature, silicon detector leakage currents, power supply voltages and currents in the LHC detector environment is a rad-hard, low-power multi-channel A/D converter. For these applications in the CMS central tracker we have designed and developed an integrated circuit, the Detector Control Unit (DCU). The core of the DCU is an 8-channel 12-bit A/D converter controlled through a standard I2C interface. The structure and the performance of this ADC are desribed in the paper.

P. Chumney, S. Dasu, F. di Lodovico, M. Jaworski, J. Lackey, P. Robl, W.H.Smith
University of Wisconsin – Madison
Wesley H. Smith
University of Wisconsin Physics Department
1150 University Ave. Madison, Wisconsin 53706 USA
( : (608)262-4690,
Fax: (608)263-0800,
email: wsmith@wishep.physics.wisc.edu
http://hep.wisc.edu/wsmith/

The CMS regional calorimeter trigger system detects signatures of electrons/photons, taus, jets, and missing and total transverse energy in a deadtimeless pipelined architecture. This system contains 19 crates of custom-built electronics. Recent changes to the Calorimeter Trigger have been made to improve the efficiency and purity of jet and tau triggers. The revised algorithms, their implementation in hardware, and their performance on physics signals and backgrounds are discussed.

Alex Madorsky
University of Florida/Physics
Museum rd & NS dr
Gainesville, FL, 32606, USA

(1-352-392-9849
fax: 352-392-8863

Development and Test of a Prototype Track-Finder for the Level-1 Trigger of the CMS Endcap Muon System

We report on the development and test of a prototype track-finding processor for the Level-1 trigger of the CMS endcap muon system. The processor links track segments identified in the cathode strip chambers of the endcap muon system into complete three-dimensional tracks, and measures the transverse momentum of the best track candidates from the sagitta induced by the magnetic bending. The algorithms are implemented using SRAM and Xilinx Virtex FPGAs, and the measured latency is 15 clocks. We also report on the design of the pre-production prototype, which achieves further latency and size reduction using state-of-the-art technology.

Authors list :
Niels van Bakel, Jo van den Brand, Hans Verkooijen
(Free University of Amsterdam / NIKHEF Amsterdam)
Daniel Baumeister, Werner Hofmann, Karl-Tasso Knoepfle,
Sven Loechner, Michael Schmelling, Edgar Sexauer^(*),

Ulrich Trunk
(Max-Planck-Institute for Nuclear Physics, Heidelberg)
ASIC Labor Heidelberg
Schroederstrasse 90
D-69120 Heidelberg
(: +49 6221 544324
Fax: +49 6221 544345
trunk@kip.uni-heidelberg.de
http://wwwasic.kip.uni-heidelberg.de/~trunk/

Martin Feuerstack-Raible
(University of Heidelberg)
Neville Harnew, Nigel Smale
(University of Oxford)
^(*) now at Dialog Semiconductors, Kirchheim-Nabern, Germany

Beetle 1.0 and 1.1 are pipelined 128 channel front end chips for the LHCb experiment, manufactured in 0.25 mu m standard CMOS technology. The final version of this chip will be equipped with SEU resistant control circuitry and a fast front end with improved analogue performance. Three chips containing prototype components have been submitted in May 2001. Descriptions of the concepts implemented in the BeetleFE1.1, BeetleFE1.2 and BeetleSE1.0 chips are presented together with simulation- and first test results.

Authors :
E.Carrone , M. Davenport , G. De Cataldo†, A. Franco†, P.Martinengo , E. Nappi†
Presenter :
Enzo Carrone for the ALICE collaboration - CERN CH1211, Geneva 23, Switzerland
Contact :
Enzo Carrone
Enzo.Carrone@cern.ch
CERN 1-R-035 CH1211, Geneva 23 - Switzerland
( +41-22-76 71935

The HMPID (High Momentum Particle Identification Detector) detector is one of the ALICE (A Large Ion Collider Experiment) subdetectors planned to take data at LHC at the beginning of 2005. Since ALICE will be located underground, the HMPID will be remotely controlled by a Detector Control System (DCS), which consists of three layers: physical, control and supervisory.

The first one includes sensors, actuators and the detector, the second one deals with the device where the control programs run, and finally the supervisory layer contains the Machine-Man Interface (MMI), which lets the user run the DCS.

In this paper we will present the DCS design, accomplished via GRAFCET (GRAphe Fonctionel de Commande Etape/Transition), a tool which represents the DCS as a finite state machine, and then translated into code readable by the PLC (Instruction List) via an ad hoc algorithm. The SCADA DCS is based on PVSS, a commercial software. The results achieved so far show that this way of proceeding is effective and time saving, since every step of the work is autonomous, making simpler the debugging and updating phases.

Politecnico di Bari, Italy and CERN, Switzerland
CERN, Switzerland
INFN Bari, Italy

E. Hazen, J. Rohlf, S. Wu - Boston University
hazen@joule.bu.edu
rohlf@bu.edu
wusx@bu.edu

Eric Hazen
Boston University Physics Dept
( 617/353-6120
Fax 617/353-3331
http://ohm.bu.edu/~hazen
Schedule at http://calendar.yahoo.com/public/eshazen/

The CMS HCAL data concentrator must combine data from about 600 front-end channels, with real-time synchronization and error-checking and an average throughput of 200 Mbytes/s. A modular implementation is described which is based on industry and CERN standards: PCI bus, PCI-MIP and PMC carrier boards, S-Link and LVDS serial links. A prototype has been built and tested using modular components. PC-MIP triple LVDS receivers collect data from front-end boards. A PMC logic board performs application-specific processing. A VME motherboard provides a standard platform and transparent access to monitoring and error registers. Test results and implementation details are described.

Gabriele_Chiodini
chiodini@fnal.gov
Particle Physics Division,
Fermi National Accelerator Laboratory
P.O. Box 500Z
Batavia, IL 60510
(: (630) 840-5151
Fax: (630) 840-3867
chiodini@fnal.gov

We report on several irradiation studies performed on BTeV pixel readout chip prototypes exposed to a 200 MeV proton beam at Indiana University Cyclotron Facility. The pixel readout chip preFPIX2 has been developed at Fermilab for collider experiments and implemented in standard 0.25 um CMOS technology following radiation tolerant design rules. The tests confirmed the radiation tolerance of the chip design to proton total dose up to 14 MRad. In addition, non destructive radiation-induced single event upsets have been observed in on-chip static registers and the single bit upset cross section has been measured. We also show irradiation test results that we are planning to do on June-July 2001, where preFPIX2 readout chips bump-bonded to pixel sensors will be exposed to high dose.

Tony Weidberg
Physics Department
Oxford University
Oxford OX1 3RH, UK
( +44 (0) 1865 273370
Fax +44 (0) 1865 273417
t.weidberg1@physics.ox.ac.uk

The readout of the ATLAS SCT and Pixel detectors will use optical links. The results of new radiation hardness and lifetime after irradiation for Truelight VCSELs are discussed. Final prototype ATLAS style opto-packages have been integrated into the SCT opto-harnesses and tested using a dedicated test system. These opto-harnesses have been used in the system tests of the SCT forward and barrel detectors. This has enabled different grounding configurations to be assessed. The plans for the production of the opto- harnesses are described.

Selcuk Cihangir
Fermilab
Particle Physics Division
selcuk@fnal.gov

W.L. Simon Kwan

swalk@fnal.gov

Pixel detectors proposed for the new generation of hadron collider experiments will use either indium or Pb/Sn solder bump-bonding technology. We have carried out a study of long term effects of both types of bump bonds using daisy-chained silicon on silicon parts. We also studied the effect of thermal cycles. Some of the parts were then exposed to intense radiation using a gamma source and the integrity of the bumps were studied afterwards.

ATLAS SCT Collaboration

Corresponding author, Zdenek Dolezal
Zdenek.Dolezal@mff.cuni.cz

ATLAS Semiconductor Tracker (SCT) prototype modules equipped with ABCD2T chips were tested with 180 GeV pion beams at CERN SPS. Binary readout method is used so many threshold scans at a variety of incidence angles, magnetic field levels and detector bias voltages were taken. Results of analysis showing module efficiencies, noise occupancies, cluster sizes and magnetic field effects will be presented. Several modules have been built using detectors irradiated to the full ATLAS dose of 3x10E14
p/cm**2 and one module was irradiated as a complete module. Effects of irradiation on the detector and ASIC performance will be shown.

Z. Dolezal(corresp. author)(1), J. Broz(1), T. Cechak(2), D. Chren(2), T. Horazdovsky(2), J.Kluson(2), C. Leroy(3), S. Pospisil(2), B. Sopko(2) and I. Wilhelm(1)

(1) Charles University, Prague
(2) Czech Technical University, Prague
(3) Montreal University

dolezal@ipnp.troja.mff.cuni.cz

A direct study of neutron induced Single Event Effects (SEE) has been performed in Prague using collimated and monoenergetic neutron beams available on the Charles University Van de Graaff accelerator. For that, silicon diodes and LHC Voltage Regulator were irradiated by neutrons of different energies (60 keV, 3.8 MeV, 15 MeV). Furthermore, the associated particle method was used, in which 15 MeV neutrons produced in the 3H(d,n)4He reaction were tagged. The measurements allowed to estimate a probability of neutron interactions per sensitive volume of the junction and an upper level of SEE occurrence in the LHC Voltage regulator chip.

B. Allongue, F. Arteche, F. Szoncso
CERN
CH-1211 Geneve 23 Switzerland

C. Rivetta
FERMILAB
P.O.500 MS 222 Batavia Il 60510 U.S.A.
rivetta@fnal.gov

The design of DC power distribution for LHC front-end electronics imposes new challenges. Some CMS sub-detectors have proposed to use a DC-power distribution based on DC-DC power switching converters located near to the front-end electronics.

DC-DC converters operate as a constant power load. They exhibit a dynamic negative impedance at low frequencies that can generate interactions between switching regulators and other parts of the input system resulting in system instabilities. In addition, switching converters generate interference at both input and output terminals and can compromise the operation of the front-end electronics and neighboring systems. Appropriated level of filtering is necessary to reduce this interference.

This papers address the instability problem and present methods of modeling and simulation to assess the system stability and performance. The paper, also, addresses the design of input and output filters to reduce the interference and achieve the performance required.

CMS-ECAL collaboration

Corresponding author : Alessandro Bartoloni – INFN ROMA
I.N.F.N. Sezione di Roma
Ple Aldo Moro 2 - 00185 - Roma
( +39-0649913535/4423
cell. +39-347-3730183
Fax +39-06-4957697

This paper describes the power supply system that will be used to bias the Avalanche Photo Diodes (APD) used in the barrel part of the CMS Electromagnetic Calorimeter detector (ECAL).

Such part is composed by 61200 PbWO crystals each equipped with 2 APD that need a bias voltage in the order of 300 Volts with high stability and ultra low noise figures (40 mV peak-peak).

Such system, that will be located in the CMS control room 150 meters far from the APDs, is currently under development under the responsibility of the INFN-ROMA department.

Prototypes tests showing the system feasibility and reliability are also discussed in the following.

Per Gällnö, CERN, Geneva, Switzerland
EP/ATE
Cellular: +41 (0)79 4527065
Fax +41 (0)22 7679495
( +41 (0)22 7672404
email: per.gallno@cern.ch

The ATLAS detector data flow from the Front End to the Read Out Buffers (ROD) has to be controlled in order to avoid that the ROD data buffers get filled up and hence data getting lost. This is achieved using a throttling mechanism for slowing down the Central Trigger Processor (CTP) Level One Accept rate. The information about the state of the data buffers from hundreds of ROD modules are gathered in daisy-chained fan-in ROD-BUSY modules to produce a single Busy signal to the CTP. The features and the design of the ROD-BUSY module will be described in this paper.

The RD-12 TTC system VMEbus interface, TTCvi, will be produced and maintained by an external electronics manufacturer and will then be made available to the users from the CERN Electronics Pool. The status of this project is given.

Authors :
V. Bocci, A. Di Mattia, E. Petrolo, R. Vari, A. Salamon, S. Veneziano
INFN Rome and Universita`
degli Studi di Roma "La Sapienza"
(+39-06-49914223
Fax +39-06-49914320
Andrea.Salamon@roma1.infn.it

The Atlas Barrel Level-1 muon trigger processes hit information from the RPC detector, identifying candidate muon tracks and assigning them to a programmable pt range and to a unique bunch crossing number.

The on-detector electronics reduces the information from about 350k channels to about 400 32-bit data words sent via optical fiber to the so-called Sector Logic boards.

Each Sector Logic board covers a region Dh x Df = 1.0 x 0.2, it receives the input from up to eight fibers and from thirty-two TileCal trigger towers. The output of the SL board is sent to the Muon Central Trigger Processor Interface (MUCTPI).

Each SL board selects the muons with the two highest thresholds in a sector and associates each muon to a Region of Interest of Dh x Df = 0.1 x 0.1. It also solves RPC chamber overlaps inside the sector and flags all the muons overlapping with a neighboring sector, and it performs the coincidence with the Tile Calorimeter.

In order to keep the full LVL1 system latency below 2 us, the Sector Logic has to perform its functions in five bunch crossing periods.

The design and performance of the Sector logic demonstrator, based on commercial and custom modules and firmware is presented, together with the design of the final VME Sector Logic board.

Piotr MALECKI,
Institute of Nuclear Physics,
ATLAS Experiment Lab.
30-055 Krakow, ul Kawiory 26A
( :(48 12) 633 33 66
Fax: (48 12) 633 38 84
malecki@chall.ifj.edu.pl

The Silicon Strip Detector of the ATLAS experiment has modular structure. The granularity of its power supply system follows the granularity of the detector. This system of 4088 multi-voltage channels providing power and control signals for the readout electronics as well as bias voltage for silicon detectors is described. Problems and constraints of the power distribution lines are also presented. In particular, optimal choice between concurrent requirements on material, maximum voltage drop, space available for services, technological constraints and cost are discussed"

The Final Multi-Chip Module of the ATLAS Level-1 Calorimeter Trigger Pre-processor

G. Anagnostou, P. Bright-Thomas, J. Garvey, S. Hillier, G. Mahout, R. Staley, W. Stokes, S. Talbot, P. Watkins, A. Watson University of Birmingham, Birmingham, UK
R. Achenbach, P. Hanke, W. Hinderer, D. Kaiser, E.-E. Kluge, K. Meier, U. Pfeiffer, K. Schmitt, C. Schumacher, B. Stelzer University of Heidelberg, Heidelberg, Germany
B. Bauss, K. Jakobs, C. Noeding, U. Schaefer, J. Thomas University of Mainz, Mainz, Germany
E. Eisenhandler, M.P.J. Landon, D. Mills, E. MoyseQueen Mary, University of London, London, UK
P. Apostologlou, B.M. Barnett, I.P. Brawn, J. Edwards, C.N.P. Gee, A.R. Gillman, R. Hatley, V.J.O. Perera, A.A. Shah, T.P. Shah Rutherford Appleton Laboratory, Chilton, Didcot, UK
C. Bohm, M. Engstrom, S. Hellman, S.B. Silverstein University of Stockholm, Stockholm, Sweden
Presented by Werner Hinderer (hinderer@kip.uni-heidelberg.de)

Abstract

The final Pre-processor Multi-Chip Module (PPrMCM) of the ATLAS Level-1 Calorimeter Trigger is presented. It consists of a four-layer substrate with plasma-etched vias carrying nine dies from different manufacturers. The task of the system is to receive and digitise analog input signals from individual trigger towers, to perform complex digital signal processing in terms of time and amplitude, and to produce two independent output data streams. A real-time stream feeds the subsequent trigger processors for recognising trigger signals, and the other provides a deadtime-free readout of the Pre-processor information for the events accepted by the entire ATLAS trigger system. The PPrMCM development has recently been finalised after including substantial experience gained with a demonstrator MCM.

Prototype Readout Module for the ATLAS Level-1 Calorimeter Trigger Processors

G. Anagnostou, P. Bright-Thomas, J. Garvey, S. Hillier, G. Mahout, R. Staley, W. Stokes, S. Talbot, P. Watkins, A. Watson University of Birmingham, Birmingham, UK
R. Achenbach, P. Hanke, W. Hinderer, D. Kaiser, E.-E. Kluge, K. Meier, U. Pfeiffer, K. Schmitt, C. Schumacher, B. Stelzer University of Heidelberg, Heidelberg, Germany
B. Bauss, K. Jakobs, C. Noeding, U. Schaefer, J. Thoma University of Mainz, Mainz, Germany
E. Eisenhandler, M.P.J. Landon, D. Mills, E. MoyseQueen Mary, University of London, London, UK
P. Apostologlou, B.M. Barnett, I.P. Brawn, J. Edwards, C.N.P. Gee, A.R. Gillman, R. Hatley, V.J.O. Perera, A.A. Shah, T.P. Shah Rutherford Appleton Laboratory, Chilton, Didcot, UK
C. Bohm, M. Engstrom, S. Hellman, S.B. Silverstein University of Stockholm, Stockholm, Sweden
Corresponding author: Viraj Perera (viraj.perera@rl.ac.uk)

Abstract

The level-1 calorimeter trigger consists of three subsystems, namely the Preprocessor, electron/photon and tau/hadron Cluster Processor (CP), and Jet/Energy-sum Processor (JEP). The CP and JEP will receive digitised calorimeter trigger-tower data from the Preprocessor and will provide trigger multiplicity information to the Central Trigger Processor and region-of-interest (RoI) information for the level-2 trigger. It will also provide intermediate results to the data acquisition (DAQ) system for monitoring and diagnostic purposes. This paper will outline a readout system based on FPGA technology, providing a common solution for both DAQ readout and RoI readout for the CP and the JEP.

One Size Fits All: Multiple Uses of Common Modules in the ATLAS Level-1 Calorimeter Trigger

G. Anagnostou, P. Bright-Thomas, J. Garvey, S. Hillier, G. Mahout, R. Staley, W. Stokes, S. Talbot, P. Watkins, A. Watson   
University of Birmingham, Birmingham, UKR.
Achenbach, P. Hanke, W. Hinderer, D. Kaiser, E.-E. Kluge, K. Meier, U. Pfeiffer, K. Schmitt, C. Schumacher, B. Stelzer
University of Heidelberg, Heidelberg, Germany
B. Bauss, K. Jakobs, C. Noeding, U. Schaefer, J. ThomasUniversity of Mainz, Mainz, GermanyE. Eisenhandler, M.P.J. Landon, D. Mills, E. MoyseQueen Mary, University of London, London, UK
P. Apostologlou, B.M. Barnett, I.P. Brawn, J. Edwards, C.N.P. Gee, A.R. Gillman, R. Hatley, K. Jayananda, V.J.O. Perera, A.A. Shah, T.P. Shah
Rutherford Appleton Laboratory, Chilton, Didcot, UK
C. Bohm, M. Engstrom, S. Hellman, S.B. Silverstein    University of Stockholm, Stockholm, Sweden
Corresponding author: Eric Eisenhandler (e.eisenhandler@qmw.ac.uk)

Abstract

The architecture of the ATLAS Level-1 Calorimeter Trigger has been improved and simplified by using a common module to perform different functions that originally required three separate modules. The key is the use of FPGAs with multiple configurations, and the adoption by different subsystems of a common high-density custom crate backplane that takes care to make data paths equal widths and includes minimal VMEbus. One module design can now be configured to count electron/photon and tau/hadron clusters, or count jets, or form missing and total transverse-energy sums and compare them to thresholds. In addition, operations are carried out at both crate and system levels by the same module design.

A.van den Brink(a), F.Daudo(b), S.Coli(b), G.Feofilov(c), G.Giraudo(b), O.Godisov(d), S.Igolkin(d), P.Kuijer(a), G.-J.Nooren(e), A.Swichev(d), F.Tosello(b)

a/    Utrecht University, Netherlands
b    /INFN, Torino,Italy
c/    St.Petersburg State University, Russia
d/    CKBM,St.Petersburg, Russia
e/    NIKHEF, Amsterdam, Netherlands

Reporter: G.Feofilov
(For the ALICE collaboration)

P.G.Kuijer@fys.ruu.nl
giraudo@to.infn.it
A.vandenBrink@fys.ruu.nl
DAUDO@to.infn.it
tosello@to.infn.it
igolkin@hiex.phys.spbu.ru>
godisov@nataly.spb.su
nooren@nikhef.nl
coli@to.infn.it

We present analysis, technology developments and test resultsof the heat drain system of the SDD and SSD front-end electronicsfor the ALICE Inner Tracker System (ITS). The application of the superthermoconductive carbon fibre thin plates provides a practicalsolution for the development of miniature motherboardsfor the FEE chips situated inside the sensitive ITS volume.Unidirectional carbon fibre motherboards of 160 -300 micron thicknessensure the mounting of the FEE chips and the efficient heat sink tothe cooling arteries. Thermal conductivity up to 1.3 times better thencopper is achieved while preserving a negligible multiple scatteringcontribution by the material (less then 0.07-0.15 percent of X/Xo).

Authors:
K.E. Arms, K.K. Gan, M. Johnson, H. Kagan, R. Kass, C. Rush, S. Smith and M. Zoeller
Department of Physics, The Ohio State University,
Columbus, Ohio 43210, USA

J. Hausmann, M. Holder, M. Kraemer, A. Niculae and M. Ziolkowski *
Fachbereich Physik, University of Siegen,
57068 Siegen, Germany

*corresponding author: e-mail michal.ziolkowski@cern.ch

The aim of our work is to design radiation-hard CMOS electronics for optical data transmission in the ATLAS Pixel detector. Two ASICs are under development: a VCSEL driver chip for 80 Mb/s data transmision from the detector and a Bi-Phase Mark decoder chip to recover control data and 40 MHz clock received optically by a PIN diode on the detector side. Both ASICs are implemented in radiation-hard 0.8um DMILL technology. Samples of chips were irradiated recently with 25 GeV protons up to the total dose of 55 Mrad and the conclusive results are expected in the Summer of 2001.

A. Rivetti (1,2), G. Anelli (3), G. Mazza(2), I. Martinez (2,4), F. Rotondo (2), F. Tosello (2), R. Wheadon (2)

for the ALICE collaboration

1. Università di Torino, Dipartimento di Fisica Sperimentale, Via P. Giuria 1, 10125, Torino - ITALY
2. INFN, Sezione di Torino, Via P. Giuria 1, 10125, Torino - ITALY
3. CERN, EP Division, CH1211, Geneve 23, Switzerland.
4. Cinvestav, Mexico-City, Mexico.

Abstract

The front-end system of the Silicon Drift Detectors (SDDs) of the ALICE experiment is made of two ASICs. The first chip performs the preamplification, temporary analogue storage and analogue-to-digital conversion of the detector signals. The second chip is a digital buffer that allows for a significant reduction of the connection from the front-end module to the outside world. In this paper the results achieved on the first complete prototype of the front-end system for the SDDs of ALICE are presented.

Jacques Lecoq, Gerard Bohner, Remy Cornat, Pascal Perret,
Cyrille Trouilleau. LPC Clermont Ferrand

lecoq@clermont.in2p3.fr

The LHCb preshower signals show so many fluctuations at low energy that a classical shaping is not usable at all. Thanks to the fact that the fraction of the collected energy during a whole LHC beam crossing time is 85%, we studied the special solution we presented at Snowmass 1999 workshop. This solution consists of 2 interleaved fast integrators, one being in integrate mode when the other is digitally reset. Two track and hold and an analog multiplexor are used to give at the output 85% of the signal plus 15% of the previous one. These 15% are digitally computed from the previous sample, and subtracted. A completely new design of this solution had to be made. This new design is described, including new methods to decrease the supply voltage and the noise, as well as to increase the quality of the reset and the linearity. An output stage, consisting of a AB class push-pull using only NPN transistors is also described. Laboratory and beam test results are given.

H. Chen, F. Lanni, M.A.L. Leite, S. Rescia and H. Takai
Brookhaven National Laboratory - Physics Department
Upton, NY - 11973 - USA

An optically coupled charge injection system for ionization based radiation detectors which allows a test charge to be injected without the creation of ground loops has been developed. An ionization like signal from an external source is brought into the detector through an optical fiber and injected into the detector electrodes by means of a photodiode.

Roberto Beccherle
INFN - Sez. di Genova
Via Dodecaneso, 33
I-16146 GENOVA
( +39 10 353-6485
Fax +39 10 353-6319
Roberto.Beccherle@ge.infn.it

The main building block of the Atlas Pixel Detector is a "module" made by a Silicon Detector bump-bonded to 16 Analog Front-End chips. All FE's are connected by a star topology to the MCC. MCC does system configuration, event building, control and timing distribution. The electronics has to tolerate radiation fluences up to 10^15 cm^-2 1Mev in equivalent neutrons during the first three years of operation. The talk describes the first implementation of the MCC in DMILL (a .8um Rad-Hard technology). Results on tested dices and irradiation results of this devices at the CERN PS, up to 30 MRad, will be presented. The chip was operating during irradiation and allowed to measure SEU effects.

Author:
Kerry Bernstein
STSM, IBM Server Technology
863K, 1000 River Rd, Essex Jct, VT 05452
(: (802)769-6897 HOME: (802) 899-2216
Fax: (802)769-6744 PAGE: (802) 769-1844 x 3946

kbernste@us.ibm.com

Entropy is a worthy adversary! High performance logic design in next-generation CMOS lithography must address an increasing array of challenges in order to deliver superior performance, power consumption, reliability and cost. Technology scaling is reaching fundamental quantum- mechanical boundaries! This talk will review example mechanisms which threaten deep submicron VLSI circuit design, such as tunneling, radiation- induced logic corruption, and on-chip delay variability. We will also examine architectures, circuit topologies, and device technologies under development which extend "evolutionary" concepts and introduce "revolutionary" paradigms. It will be these revolutionary technologies which will bring us to the threshold of human compute capability.

Author:
Kerry Bernstein
STSM, IBM Server Technology
863K, 1000 River Rd, Essex Jct, VT 05452
(: (802)769-6897 HOME: (802) 899-2216
Fax: (802)769-6744 PAGE: (802) 769-1844 x 3946
kbernste@us.ibm.com

Market demand of microprocessor performance has motivated continued scaling of CMOS through a succession of lithogrpahy generations. Quantum-mechanical limitations to continued scaling are becoming readily apparent. Partially-Depleted Silicon-on-Insulator (PD-SOI) technology has emerged as an evolutionary means of circumnavigating these limitations. This tutorial will first introduce the audience to high performance SOI device physics, and its idiosyncrasies. Preferred circuit design practices and considerations for microprocessor components will be examined. Finally, future buried oxide devices inpired by the PD-SOI MOSFET will be reviewed. This talk will draw heavily from the textbook "SOI Circuit Design Concepts" published by Kluwer Academic Publishers.

Yasuaki Ishida, Chikara Fukunaga, Ken-ichi Tanaka, Naofumi Takahata
(Department of Physics, Tokyo Metropolitan University)
for ATLAS TGC Electronics Group
E-mail:ishida@comp.metro-u.ac.jp <Main>
URL:http://tmubsun.center.metro-u.ac.jp/ishida/

We present the development of an emulator of TTC system. This emulator is made using an ASIC and includes functionalities of generation of LHC bunch pattern as well as random trigger, relevant functionalities of TTCvi, TTCvx, and TTCrx in one IC chip. Therefore, a test system environment of detector front-end modules using TTC system can be simplified dramatically. And thanks to the random trigger generation, this emulator can give us a realistic experimental environment for an electronics system. We discuss the function of this emulator and test results of the ASIC.

Joel Bovier
Director R&D
CES Creative Electronic Systems SA
70 route du Pont Butin
CH 1213 Petit Lancy, Switzerland
joel@ces.ch
((+41 22) 879 51 00

This paper describes the different aspects of modern board level electronic design with the consequences on the fabrication process. New technology packages such as BGA and FBGA implies the use of secure design techniques because the rework is very difficult. CES’s experience of the different steps will be covered : design for testability, EMI/RFI concern, signal integrity, in situ programming, new PCB layout techniques, JTAG testing strategy, and yield in production.

Commissioning results of the First Level Trigger in HERA-B during 2000

Imma RIU
Riu@mail.desy.de

Abstract

During year 2000, the First Level Trigger was installed, operated and commissioned in HERA-B. This paper describes the pattern recognition algorithm, its implementation in electronics and the commissioning results.

The basic task is to accept events with lepton pairs that originate from the decay of the J/psi meson. With a latency smaller than 10 microseconds, the First Level Trigger has to process about 100,000 channels of detector data that are readout every 96 ns. Using a kalman filter technique, the First Level Trigger searches for tracks produced in the detector through up to seven layers.

Prototype Slice of the Level-1 Muon Trigger in the Barrel Region of the ATLAS Experiment

V.Bocci, G.Chiodi, S.Di Marco, E.Gennari, E.Petrolo, A.Salamon, R.Vari, S.Veneziano
INFN Roma, Dept. of Physics, Università degli Studi di Roma "La Sapienza"
p.le Aldo Moro 2, 00185 Rome, Italy

Abstract

The ATLAS barrel level-1 muon trigger system is split in an on-detector and an off-detector part. Signals  coming from the first two RPC stations are sent on detector to dedicated ASICs mounted on the low-pT Pad boards, that select muon candidates compatible with a programmable pT cut of around 6 GeV/c, and produce an output pattern containing the low-pT trigger results. This information is transferred to the corresponding high-pT Pad boards, that collect the overall result for low-pT and perform the high-pT algorithm using the outer RPC station, selecting candidates above a threshold around 20 GeV/c. The combined information is sent via optical fibre off-detector to the optical receiver boards and then to the Sector Logic boards, that count the muon candidates in a region of Dh×Df =1.0 ×0.1 ,and encode the trigger results. The elaborated trigger data is sent to the Central Trigger Processor Muon Interface on dedicated copper link. The read-out data for events accepted by the level-1 trigger are stored on-detector and then sent to Read-Out Drivers via the same receiver boards mentioned before sharing the bandwidth with the trigger data.

A trigger slice is made of the following components: a low-pT board, containing four Coincidence Matrix boards; a high-pT board, containing 4 CM boards, the Pad logic board and the optical link transmitter; an optical link receiver; a Sector Logic board; a Read-Out Driver board. Prototype functionality will be presented.

V.Bocci⁽¹⁾ , M. Carletti⁽²⁾, G.Chiodi⁽¹⁾, E. Gennari⁽¹⁾, E.Petrolo⁽¹⁾, A.Salamon⁽¹⁾, R. Vari⁽¹⁾,S.Veneziano⁽¹⁾
(1) INFN Roma, Dept. of Physics, Università degli Studi di Roma “La Sapienza”
p.le Aldo Moro 2, 00185 Rome, Italy
(2) INFN Laboratori Nazionai Frascati, Via Enrico Fermi 40, Frascati (Roma) 

Further Developments in the ALICE Trigger

Anton Jusko (Slovak Academy of Sciences, Kosice) for the ALICE Collaboration

Abstract

The ALICE experiment is completing its technical specification stage, with most sub-projects about to start building. The development of the trigger system must mirror this process by specifying the interfaces and protocols for each stage in the trigger. In addition, in ALICE, sub-detector  groups will be able to test their systems using a Local Trigger Unit (LTU), which provides the sub-detector front-end systems with the correct sequence of signals driven either by the Central Trigger Processor (CTP) or by a simple pulser.

In the last year a draft User Requirement Document (URD) has been prepared for the CTP. Recently, changes have been recommended for the number of inputs and trigger classes. A study of the implementation of these new reuirements will be presented.

An optical link interface for the Atlas Tile-Calorimeter

Daniel Eriksson, Jonas Klereborn, Magnus Ramstedt and Christian Bohm
University of Stockholm, Sweden

Abstract

An optical (1300 nm) link interface has been developed in Stockholm for the Atlas Tile-Calorimeter. The link serves as a readout for one entire TileCal drawer, i.e. with up to 48 front-end channels. It is also contains a receiver for the TTC clocks and messages distributing these to the full digitizer system. Digitized data is serialized in the digitizer boards and supplied with headers and CRC control fields. Data with this protocol is then sent via G-link to an Odin S-link receiver card where it is unpacked and parallelized in a specially developed Altera code. The entire read-out part of the interface has been duplicated for redundancy with two dedicated output fibers. The TTC distribution has also been made redundant by using two receivers (and two input fibers) both capable of distributing the TTC signal. A high pass filter tuned to the frequency of an active TTC-link, decides which receiver to use. To decrease the sensitivity to radiation the complexity of the interface has been kept at a minimum. This is also beneficial to the system cost. To facilitate the mechanically installation the interface has been given an L-shape so that it can be mounted closely on top of one of the digitizer boards without interfering with its components.

Tests and Production of the ATLAS Tile Calorimeter Digitizer

Jonas Klereborn, Magnus Ramstedt, Svante Berglund, Christian Bohm,
Kerstin Jon-And, Sam Silverstein.
Stockholm University

Abstract

After a successful pre-production series the full scale production of the Tile-Cal digitizer will begin during the summer of 2001. To be able to ensure functionality and quality a test scheme has been developed Before production all components have been radiation tested. After mounting the component the digitizer is tested at the producer in a specially designed reduced test-bench to verify the functionality. All digitizers are then passed through burn-in and are tested again in a full test-bench reproducing operational conditions using a custom designed software, which ensures that full functionality is maintained. Test data is stored in an auto-generated file for future reference. A similar test software is later used at Clermont-Ferrand where the drawer containing all detector electronics are assembled. Their test results
will be cross-referenced with the original test data entry.

Design and Test of the Track-Sorter-Slave ASIC for the CMS Drift Tube Chambers

Authors
G.M.Dallavalle, A.Montanari, F.Odorici, R.Travaglini
INFN and University, Bologna, Italy

Oral presentation: F. Odorici (INFN Bologna)
Conference Topic: High Energy Physics Instrumentation
Fabrizio.Odorici@bo.infn.it

Abstract

Drift Tubes Chambers (DTCs) are used to detect muons in the CMS barrel. Several electronic devices installed on the DTCs will analyse data every bunch crossing, in order to produce a trigger decision. In particular, the Trigger Server system has to examine data from smaller sections of a DTC, in order to reduce the chamber trigger output by a factor of 25. The basic elements of the Trigger Server system are the Track-Sorter-Slave (TSS) units, implemented in a 0.5 micron CMOS ASIC. This paper describes the TSS ASIC, with emphasis on the methodology used for design verification with prototypes and IC simulation and test.

High-speed multichannel ICs for front-end electronics systems

A.Goldsher*, Yu.Dokuchaev*, E.Atkin**, Yu.Volkov**

*-- State unitary enterprise “Science and Technology Enterprise “Pulsar”,
Russia, 105187, Moscow, Okruzhnoy proezd, 27.

** -- Moscow State Engineering Physics Institute (Technical University),
Russia, 115409, Moscow, Kashirskoe shosse, 31.

Abstract 

The basic set of high-speed multichannel analog ICs for front-end electronics systems, designed and put into production in Russia, is described. It is implemented as a number of application specific ICs (ASIC) and ICs, based on an application specific semicustom array (ASSA). By their electrical parameters the created ICs are on a par with foreign functional analogs. The prospects of their further development are expounded.

Experiences from the Electronic Commissioning of HERA-B

Bernhard Schwingenheuer, Max-Planck-Institut Heidelberg

Abstract

In 2000 the HERA-B experiment was for the first time  fully assembled including different trigger levels and the complete data acquisition structure. This talk reviews the design and performance of the electronics involved  starting from the detector readout to the data routing to the PC farm of the Second Level Trigger. Special emphasis is given to concepts which have proven to be successful and to observed deficits.

'The LHC experimental programme - a status report'

 J. Engelen, NIKHEF 

The LHC experimental programme will be briefly reviewed. Special attention wil
be given to the status of the various projects, with a view to the LHC
pilot and physics runs in 2006.

Radiation tolerance and behavior in magnetic field of CAEN HV and LV boards for LHC experiments

G. M. Grieco
C.A.E.N. S.p.A., Via Vetraia 11. I-55049 Viareggio, Italy
E-Mail GRIECO@CAEN.IT, URL http://www.caen.it

The radiation and magnetic field levels at LHC impose severe design criteria and components selection on the power supply systems to guarantee safe and reliable operations. A study of radiation and magnetic field tolerance of CAEN HV and LV boards has been performed. Results of the proton beam tests performed in Louvain-la-Neuve and magnetic field tests performed at CERN are presented. The HV and LV boards have succesfully passed the scheduled tests and can be a good candidate for several LHC experiments.

Electronics for Pixel Detectors

Michael Campbell

Most modern HEP experiments use pixel detectors for vertex finding because these detectors provide clean and unabiguous position information even in a high multiplicity environment. At LHC three of the four main experiments will use pixel vertex detectors. There is also a strong development effort in the US centred around the proposed BTeV experiment. The chips being developed for these detectors will be discussed giving particular attention to the archiectural choices of the various groups. Radiation tolerant deep sub-micron CMOS is used on most cases. In light of predicted developments in the semiconductor industry it is possible to foresee the trends in pixel detector design for future experiments.

Use of Network Processors in the LHCb Trigger/DAQ System

J.-D. Dufey, R. Jacobsson, B. Jost and N. Neufeld
Cern, Geneva, Switzerland

 Network Processors are a recent development targeted at the high-end network switch/router market. They usually consist of a large number of processing cores, multi-threaded in hardware, that are specialized in analyzing and altering frames arriving from the network. For this purpose there are hardware co-processors to speed-up e.g. tree-lookups, checksum calculations etc. The usual application is in the input stage of switches/routers to support de-centralized packet or frame routing and hence obtain a better scaling behaviour.

In this paper we will present the use of Network Processors for data merging in the LHCb dataflow system. The architecture of a generic module will be presented that has the potential to be used also as a building block of the event-building network for the LHCb software trigger.