S. Cadeddu, A. Lai*

INFN Sezione di Cagliari, Cittadella Universitaria, 09042 Monserrato
(Cagliari) - Italy

*Corresponding author,
( . Off +39 070 675 4913 * labs. +39 070 675 4973/5/8
Fax +39 070 510212
( . @ CERN +41 22 76 74968 - Bat. 14-04-005

alessandro.cadeddu@ca.infn.it
adriano.lai@ca.infn.it.
http://www.ca.infn.it/~elettro

We present a custom integrated circuit, developed in the IBM 0.25 micron technology. The chip is named DIALOG ((DIagnostics, time Adjuster and LOGics) and it is a fundamental ingredient of the LHCb muon front-end electronics. Each integrated circuit handles 16 front-end channels. The circuit generates the information used by the level 0 trigger starting from the front-end signals, by means of a suitable (programmable) logical combination. In addition, it integrates functionalities important for signal time-alignment and front-end channels diagnostics at run time.

The LHCb muon system supplies binary information, used by the fast L0 muon trigger. Nevertheless, the information used by the trigger does not coincide with the signals as output by the front-end Amplifier-Shaper-Discriminators (ASD). This is due to single channel maximum capacitance and sustainable rates. So, an important task of the electronics system is to generate trigger information, corresponding to 26,000 so called logical channels, starting from about 120,000 ASD signals, called physical channels. In order to minimize the number of links (and costs), such a function is performed on detector by DIALOG, our custom integrated circuit. The logical combinations necessary to generate the logical channels are different, according to the different detector regions. Consequently, DIALOG is configurable by writing suitable internal registers, which are accessible via an I2C interface. DIALOG is also important to time-align logical channels, in order to correctly synchronize the entire detector. This task is crucial for all the LHC experiments. DIALOG integrates 16 programmable delays, which allow shifting the signal phase by 32 steps of about 1.5 ns each. This covers two bunch-crossing periods. The programmable delays are used when setting up the detector before data taking, but can be re-programmed at any needed time by writing suitable internal registers. DIALOG contains also diagnostics features to distribute synchronous pulses to the ASD channels and to monitor the physical channels' activity. Moreover, it contains DAC’s to supply voltage thresholds to the front-end discriminators. All these functions are controlled via the I2C interface. DIALOG is being developed in the IBM 0.25 micron radiation hard technology. We plan to submit a first version in the next August run. We present the circuit internal scheme and layout and some characterizing simulations.

Authors list:
Niels van Bakel, Jo van den Brand, Hans Verkooijen
(Free University of Amsterdam / NIKHEF Amsterdam)

Daniel Baumeister, Werner Hofmann, Karl-Tasso Knoepfle,
Sven Loechner, Michael Schmelling
(Max-Planck-Institute for Nuclear Physics, Heidelberg)

Martin Feuerstack-Raible
(University of Heidelberg)

Neville Harnew, Nigel Smale
(University of Oxford)

Edgar Sexauer
(now at Dialog Semiconductors, Kirchheim-Nabern, Germany)

Daniel Baumeister
baumeis@asic.uni-heidelberg.de

MPI for Nuclear Physics Heidelberg
ASIC laboratory
Schroederstr. 90
D-69120 Heidelberg
(: ++49 6221 544324
Fax : ++49 6221 544345

The Beetle front end chip for LHCb is a 128 channel pipeline chip developed in 0.25 um standard CMOS technology. After intensive testing of the first version (Beetle1.0), an improved design (Beetle1.1) has been submitted in March 2001. The key measurements on the Beetle1.0, which mainly drove the design changes for the Beetle1.1, are described together with first performance data of the new chip.

A 128 channel readout chip, the Beetle, has been developed for the LHCb experiment in 0.25 um standard CMOS technology. The latest design has been submitted in March 2001. The chip can be operated as analog or alternatively as binary pipelined readout chip and fulfills the requirements of the silicon vertex detector, the inner tracker, the pile-up veto trigger and the RICH in case of multianode photomultiplier readout.

The chip integrates 128 channels with low-noise charge-sensitive preamplifiers and shapers. The risetime of the shaped pulse is 25 ns, the spill-over left 25 ns after the peak at most 30%. A comparator per channel with configurable polarity provides a fast binary signal. Four adjacent comparator channels are being ORed and brought off chip via LVDS ports. Either the shaper- or the comparator output is sampled with the LHC-bunch-crossing frequency at 40 MHz into an analogue pipeline with a programmable latency of max. 160 sampling intervalls and an integrated derandomizing buffer of 16 stages. For analog readout the data are multiplexed with up to 40 MHz onto 1 or 4 ports. A binary readout mode operates with doubled output rate on two ports. Current drivers bring the serialized data off chip. The chip can accept trigger rates of up to 1 MHz, the readout time per event is within 900 ns. For testing and calibration purposes, a charge injector with adjustable pulse height is implemented. The bias settings and various other parameters can be controlled via a standard I2C-interface.

The first chip version (Beetle1.0) submitted in April 2000 had to be patched with a focused ion beam to be functional. The reason was a layout bug in the control circuit. Beetle1.1 fixes this bug. In addition it solves a problem with the bias network of the pipeline readout amplifier, avoids charge injection in the switch of the resetable amplifier and fixes an error inside the multiplexer. The measurements pointing out bugs and problems on Beetle1.0 are presented, the resulting design modification on the Beetle1.1 are described and first performance measurements with the new readout chip are shown

DEVELOPMENT OF AN OPTICAL DATA TRANSFER SYSTEM FOR THE LHCb RICH DETECTORS

N.Smale, M.Adinolfi, J.Bibby, G.Damerell, N.Harnew, S.Topp-Jorgensen
University of Oxford, UK

V.Gibson, S.Katvars, S.Wotton
University of Cambridge, UK

K.Wyllie
CERN, Switzerland

Development of a front-end readout system for the LHCb Ring Imaging Cherenkov (RICH) detectors is in progress. The baseline solution for the RICH detector readout electronics is the HPD Binary Pixel chip. This paper describes a system to transmit data with addresses, error codes and synchronisation from a radiation harsh environment. The total data read out in 900ns is 32x36x440 bits per L0 trigger, with a sustained L0 trigger rate of 1MHz. Multimode fibres driven by VCSEL devices are used to transmit data to the off-detector Level-1 electronics located in a non-radiation environment. This data is stored in 64Kbit deep QDRbuffers.

There are six stages in processing the pixel data and delivering them to the Level-1 buffer. The Level-0 radiation-hard region has an interface to/from the pixel chip, parallel /serial conversion, fibre optics and drivers. The Level-1 non-radiation region has a fibre optic receiver, serial/parallel conversion, data checking and Level-1 buffer storage. Each are described in turn.

The pixel interface: 'PInt'

The pixel chip requires an interface chip (PInt) that generates chip biasing and calibration test levels, handles the ECS (Experiment Control System) and TTC (Timing and Trigger Control). The interface adds error codes, addresses, parity and Beam crossing ID to the data. The data are synchronised to a Gigabit Optical Link (GOL). The PInt is being developed using a Spartan II FPGA chip, and then later ported into a 0.25uM CMOS radiation-hard ASIC.

Parallel to serial conversion

The GOL chip is a multi-protocol high-speed transmitter ASIC which is able to withstand high doses of radiation. The chip is run in the G-Link mode at 800Mbits/s and therefore transmits 20 bits of data in 25nS. There are 16 bits of data and 4 overhead bits for encoding. The CIMT (Conditional Invert Master Transition) encoding scheme is employed. The 20-bit word is then serialised and transmitted via a VCSEL (Vertical Cavity Surface Emitting Laser) and multimode fibres. The threshold of the laser driver may be adjusted during the lifetime of the experiment with the GOL chip.

Fibre Optic Drivers

VCSELs emit light perpendicular to their p-n junctions, high output luminosity and focussing allows for easy coupling to multimode fibres. Wavelengths are generally in the 760-960nm range and output power is typically 5mW for a multimode fibre. VCSEL arrays can be easily incorporated into single ICs which allow for a much better multiple-fibre package. The VCSELs have been proven to be very robust in terms of radiation and magnetic fields. The proposal is to use 2 VCSELs per pixel chip and drive the data over 80 metres of multi-mode fibre to the counting room at 800Mb/s.

The fibre optic receiver and serial to parallel converter

The data are to be received by a pin diode and processed by either a Hewlett Packard HDMP1034 or the Texas Instruments TLK2501IRCP.

Data checking and Level-1 storage.

Data arriving from the serial/parallel converter are in a 16 bit wide 36 bit deep format, received at a rate of 640Mbits/s. The data contain header and error codes that require checking and stripping so as to leave 32x32 bits of raw data. The raw data, with event ID, are proposed to be time multiplexed and stored in the Level-1 buffer. The Level-1 buffer is a commercially available QDR SRAM (Quad Data Rate SRAM). The QDR SRAM is a memory bank of 9Mbits and can be segmented into multiple 64K bit deep Level-1 buffers. Data can be read in and read out on the same clock edge at a rate of 333Mbits/sec. For the QDR control and address generation a Spartan II FPGA is proposed. The Spartan II is chosen for it's high performance and I/O count at a low cost. The other functions of the Spartan II are to process the data from the serial/parallel converter, interface to the ECS and TTC.

Conclusion

The readout scheme will be presented with results for bit error rates and synchronisation checking. Full compatibility with TTC and ECS for the whole integrated system will be demonstrated.

Z. Guzik, R. Jacobsson and B. Jost
Richard.Jacobsson@cern.ch

To be presented by R. Jacobsson

In this paper we describe the LHCb Timing and Fast Control (TFC) system. It is different from that of the other LHC experiments in that it has to support two levels of high-rate triggers. Furthermore, emphasis has been put on partitioning and on locating the TFC mastership in one type of module: the Readout Supervisor. The Readout Supervisor handles all timing, trigger, and control command distribution. It generates auto-triggers as well as control the trigger rates.
Partitioning is handled by a programmable patch panel/switch introduced in the TTC distribution network between a pool of Readout Supervisors and the Front-End electronics.

The LHCb Timing and Fast Control (TFC) system is in the prototyping phase. Although the backbone of the timing, trigger and control distribution network is based on the CERN RD12 system (TTC), several components are unique to the LHCb experiment due to the fact that the readout system is different from that of the other experiments in several respects. Firstly, the LHCb TFC system has to handle two levels of high-rate triggers: a Level 0 (L0) trigger with an accept rate of maximum 1.1 MHz and a Level 1 (L1) trigger with an accept rate of maximum 60 kHz. Secondly the TFC architecture focuses on partitioning. A partition is in LHCb defined as a configurable ensemble of parts of a sub-detector, an entire sub-detector or a combination of sub-detectors that can be run in parallel, independently and with a different timing, trigger and control configuration than any other partition. Furthermore, the aim has been to locate the entire TFC mastership of a partition in a single module: the Readout Supervisor (RS). The idea is to have a pool of such Readout Supervisors, in which one is interfaced to the two central trigger decision units and is used for physics data taking. The others are fully configurable masters for testing, debugging and calibrating any partition stand-alone.

The Readout Supervisors receive the LHC bunch clock via the LHC machine interface. The RS used for physics data taking also receives the L0 and L1 triggers from the central L0 and L1 decision units. One task of the Readout Supervisor is to distribute these, as well as internally generated triggers and various synchronous control commands, to the Front-End electronics via the TTC network. The L0 decisions are transmitted on channel A of the TTC system, and the L1 decision as well control commands share channel B and are transmitted as short broadcasts. The six user-definable bits of the short broadcasts allow qualifying the L1 triggers and encoding different types of control commands. The RS also acts as a trigger rate controller by converting positive trigger decisions to negative whenever data congestion occurs in the system. Fast buffers such as in the L0 Front-End electronics cannot feed back overflow signals and their occupancies are therefore emulated in the RS. Slower parts of the system signal congestion via hardware.

The partitioning is implemented by introducing a programmable patch panel/switch in the TTC distribution network between a pool of Readout Supervisors and the Front-End electronics. The switch can be configured to define independent distribution networks between the Readout Supervisors and sets of sub-detector components (partitions). The Readout Supervisors can thus trigger and control different partitions independently. In order to feed back the overflow signals from different sub-detector components to the appropriate RS, a second configurable "OR switch" has been devised. It performs an OR of the signals coming from components belonging to the same partition.

CERN
CH-1211 Geneva 23
Bat 14-4-006
( : +4122 767 6152
Fax: +4122 767 9425
Email: Danielle.Moraes@cern.ch

Pos-Graduacao
Instituto de Fisica - UFRJ
Cidade Universitaria - CP 68528
21945-970 Rio de Janeiro - RJ, Brasil
( : +5521 562-7463
Fax: +5521 562-7368
Email: danielle@if.ufrj.br

D. Moraes(1,2), F. Anghinolfi(1), W. Bonivento(1), P. Jarron(1),
W. Riegler(1), B. Schimdt(1), F. Vinci dos Santos(1),

(1) CERN, CH-1211 Geneva 23, Switzerland
(2) Univ. Federal do Rio de Janeiro, C.P. 68528, BR-21945-970 Rio de Janeiro, Brazil

We present recent results of an ASD frontend development in 0.25um CMOS for the LHCb muon chambers. Characteristic features of the chip are a peaking time of 10ns, input resistance of <10 Ohm, a noise of 500+39e-/pF and a fast tail cancellation shaper. We present results of a 14 channel amplifier+discriminator submission showing crosstalk and parameter variations. A negative polarity preamp version suitable for wire readout and results from a fast 2x pole/zero tail cancellation shaper are also shown.

First results of a fast detector frontend prototype designed in 0.25um CMOS were presented at the last LEB meeting [1]. Here we want to present the progress on this project which is aimed at the production of an ASD chip for the 120k channels of the LHCb muon system. In addition to the ASD chip the frontend board will house a logic chip, also designed in 0.25um CMOS, that will perform simple logic functions. The advantage of an analog+digital frontend in deep submicron technology are radiation hardness, low cost and low power dissipation.

The muon system detectors are wire chambers with cathode and anode readout, an average primary ionization of 100 electrons and a gas gain of 10^5. The optimum time resolution of the chambers requires a peaking time of 10ns. The high rates of up to 1MHz/channel require an ion tail cancellation as well as a baseline restoration circuit. The detector capacitance ranges from 20 to 250pF, the input resistance is required to be <50 Ohm.

At the last LEB we reported the results from a positive polarity preamp+discriminator chip. In this paper we present the following:

1) Results from a submission with 14 identical positive polarity amplifier+discriminator channels showing crosstalk <1%. Channel to channel variations of different parameters are discussed as well.
2) Results from a negative polarity amplifier submission.
3) Results from an amplifier+shaper submission. The shaper contains a 2x pole/zero network optimized for an ion tail of t0=1.5ns.

Authors list :
Niels van Bakel, Jo van den Brand, Hans Verkooijen
(Free University of Amsterdam / NIKHEF Amsterdam)
Daniel Baumeister, Werner Hofmann, Karl-Tasso Knoepfle,
Sven Loechner, Michael Schmelling, Edgar Sexauer^(*),

Ulrich Trunk
(Max-Planck-Institute for Nuclear Physics, Heidelberg)
ASIC Labor Heidelberg
Schroederstrasse 90
D-69120 Heidelberg
(: +49 6221 544324
Fax: +49 6221 544345
trunk@kip.uni-heidelberg.de
http://wwwasic.kip.uni-heidelberg.de/~trunk/

Martin Feuerstack-Raible
(University of Heidelberg)
Neville Harnew, Nigel Smale
(University of Oxford)
^(*) now at Dialog Semiconductors, Kirchheim-Nabern, Germany

Beetle 1.0 and 1.1 are pipelined 128 channel front end chips for the LHCb experiment, manufactured in 0.25 mu m standard CMOS technology. The final version of this chip will be equipped with SEU resistant control circuitry and a fast front end with improved analogue performance. Three chips containing prototype components have been submitted in May 2001. Descriptions of the concepts implemented in the BeetleFE1.1, BeetleFE1.2 and BeetleSE1.0 chips are presented together with simulation- and first test results.

Beetle 1.0 and 1.1 are pipelined 128 channel front end chip for the LHCb, experiment manufactured in 0.25 mu m standard CMOS technology. The chip hast to meet the requirements of the silicon vertex detector, inner tracker, the pile-up veto trigger and the RICH in case of multi-anode photomultiplier readout. The chip can be operated in analogue as well as binary readout mode. The latest version was submitted in March 2001.

Each of the chip's 128 channels features an analogue front end consisting of a charge sensitive preamplifier, an active CR-RC pulse shaper and a buffer. Its preamplifier and shaper stages use the well known folded cascode topology, the preamplifier features an NMOS input transistor. The current front end satisfies the requirements of rise below 25 ns and a remainder of at most 30% of the maximum pulse height 25 ns after the peak for a load capacitance below 15 pF. This is sufficient for applications in the LHCb vertex detector.

Higher detector capacitances as expected for the inner tracker and robust operation also for large occupancies, however, call for a faster pulse shapes with a lower remainder after 25 ns. To study possible improvements, four additional front end prototypes were developed and implemented on the BeetleFE1.1 and Beetle FE1.2 chips.

The control circuit of the Beetle heavily relies on registers, either to store configuration data, or to implement state machines. To overcome SEU failures in these registers, a parity based error correction schema (ECC) is implemented for static registers on the BeetleSE1.0, while the registers in its state machines use triple redundancy to suppress SEU failures.

The components on these chips will be included in the pipelined readout chip Beetle1.2 which is intended for submission in 2002. The circuits on the BeetleFE1.1, BeetleFE1.2 and BeetleSE1.0 chips submitted in May 2001 are presented together with simulation- and test results and descriptions of the concepts implemented on these chips.

Jacques Lecoq, Gerard Bohner, Remy Cornat, Pascal Perret,
Cyrille Trouilleau. LPC Clermont Ferrand

lecoq@clermont.in2p3.fr

The LHCb preshower signals show so many fluctuations at low energy that a classical shaping is not usable at all. Thanks to the fact that the fraction of the collected energy during a whole LHC beam crossing time is 85%, we studied the special solution we presented at Snowmass 1999 workshop. This solution consists of 2 interleaved fast integrators, one being in integrate mode when the other is digitally reset. Two track and hold and an analog multiplexor are used to give at the output 85% of the signal plus 15% of the previous one. These 15% are digitally computed from the previous sample, and subtracted. A completely new design of this solution had to be made. This new design is described, including new methods to decrease the supply voltage and the noise, as well as to increase the quality of the reset and the linearity. An output stage, consisting of a AB class push-pull using only NPN transistors is also described. Laboratory and beam test results are given.

The LHCb preshower is used for the level 0 trigger, for which a threshold corresponding to 5 minimum ionization particle ( MIP) is applied, with a 2% accuracy. This detector is also used to improve electron and photon measurement up to 100 MIP. Theses two functions give us a dynamic range of 0.1 to 100 MIP.The study of the signal given by a scintillator cell and the 64 Hammamatsu PMT,with a good agreement with their simulation, shows us that at low energy, the dominant effect is the statistical fluctuation of the photoelectron collection, while at high energy the dominant effect is the PMT saturation which begin at 0.6 mA.These conditions, and the fact that the signal length is always longer than 25ns, drive us to the solution described before.We don't change the main electronic choices we made on 1999:

A fully differential design to minimize the noises.
Bipolar transistors at the input stages to reduce the offsets.
CMOS transistors to save power and design integrator switches.

However, we had to redesign the chip due to the following considerations:

Because of the PMT saturation, we had to increase the gain by a factor 20, and then we had to take more care of the noise and offset effects. For the noise, the integrator input stage was changed, and for the offset and the operating point stability a special common mode feedback loop was added.

We need a very high quality reset, to be able to compute the subtraction with a negligible error, even in the cases of a maximum signal immediately followed by a "trigger level" one: the integrator itself was changed.
The supply voltage had to be decreased down to +/- 2.75 V to match the foundry specifications, and to obtain the "small consumption" of 100mW/channel.
To carry the 6000 output analog signals, we plan to use simple ethernet differential cables on up to 20m long, in this case, we must adapt this cable at both end, and then have to double the dynamic. (2 volts instead of 1). To save power, this dynamic is done in the last stage by designing a differential analog multiplexor with a gain of two, and a 2V dynamic range with a +/- 2.75 V supply. This required the design of parallel linearity correction instead of the previous serial one.
We have to drive the cable efficiency without extra chips: an "all NPN A-B class push-pull " was designed.
A first prototype of this new design was successfully realized, and tested both in laboratory and in test beam at CERN. The results were in very good agreement with simulation, and with noise estimation: The 10 bits dynamic range with a linearity error smaller than few per thousand is achieved, while the measured noise is half a LSB, as expected from our estimation.
After realization and test of the new output stage on a separate chip, a 4 channels chip was built, including all the functionalities.
At least, the final 8 channels version was sent to AMS foundry on april 2001.
The design of the chip,and specially its new features, are detailed, the method used to estimate and to compute the noise of a switched system is described.
Finally, laboratory and test beam results , including noise measurement, are given.