Project status of the CMS tracker optical links
François Vasey, CERN, Geneva, Switzerland
F. Vasey, C. Azevedo, T. Bauer1, B. Checucci2, G. Cervelli, K. Gill, R. Grabit,
F. Jensen, A. Zanet
CERN, Geneva (Switzerland)
1
HEPHY, Vienna (Austria)2
INFN, Perugia (Italy)The development phase of the optical data transfer system for the CMS tracker is now complete. This paper will present the project status and review the preparation for production. In particular, it will focus on the results of the market surveys for front-end components, and on the performance evaluation of a close-to-final readout chain.
Radiation Hard Optical Links for the ATLAS SCT and Pixel Detectors
Tony Weidberg, Oxford University, UK
D. Charlton, J.D.Dowell, R.J.Homer, P. Jovanovic, G.Mahout, H.R.Shaylor, J.A.Wilson.
School of Physics and Astronomy, University of Birmingham, Birmingham, B15 2TT, UK
I.M. Gregor, R.Wastie, A.R. Weidberg
Physics Department, University of Oxford, Keble Road, Oxford, OX1 3RH, UK.
S.Galagedera, M.C.Morrissey, J.Troska, D.J.White.
CLRC Rutherford Appleton Laboratory, Chilton, Didcot, Oxon, OX11 0QX, UK.
A.Rudge
CERN, Geneva, Switzerland.
M.L.Chu, S.C.Lee, P.K.Teng
Institute of Physics, Academia Sinica, Taipei, Taiwan 11529, Republic of China.
A radiation hard optical readout system designed for the ATLAS Semi-conductor Tracker (SCT) is described. Two independent versions of the front-end optical package housing two VCSEL emitters and an epitaxial Si PIN photodiode have been irradiated with neutron fluences over 1015 n.cm-2, the level encountered in the ATLAS pixel detector. Environmental tests have been performed down to -20o C. Extensive radiation and lifetime tests have also been carried out on the opto-electronic components and the front-end VCSEL driver and timing/control ASICs. Bit error rate and cross-talk measurements using irradiated devices show that the system easily meets the performance specification.
Recent Progress in Field-Programmable Logic
Peter Alfke, Director, Applications Engineering, Xilinx, Inc, San Jose, CA, USA
LHC machine timing distribution for the experiments
Bruce G. Taylor, CERN, Geneva, Switzerland, for the RD12 Collaboration
At the LHC the 40.079 MHz bunch crossing clock and 11.246 kHz machine orbit signal must be distributed from the Prevessin Control Room (PCR) to the TTC systems of the 4 LHC experiments, to the test beam facilities in the West and North areas and to beam instrumentation around the ring. To achieve this, a single high-power laser transmitter with optical fanout to all the destinations has been installed at the PCR. A standard TTC machine interface (TTCmi) has been developed which receives the signals and can deliver very low jitter timing signals to LHC experiment TTC distribution systems with multiple trigger partitions.
Updated Design for the ALICE Central Trigger
Orlando Villalobos Baillie, University of Birmingham, UK
I.J. Bloodworth 1, G. Di Marzo 2, D. Evans 1, P. Jovanovic 1, A. Jusko 3, J.B. Kinson 1, A. Kirk 1, V. Lenti 4, M. Luptak 3, L. Sandor 3, P. Vande Vyvre 2 and O. Villalobos Baillie 1 for the ALICE collaboration.
1
School of Physics and Astronomy, The University of Birmingham, Edgbaston, Birmingham, UK B15 2TT2
CERN, European Organization for Nuclear Research, CH-1211 Geneva 23, Switzerland.3
Dipartimento di Fisica dell' Universita and Sez. INFN, Bari, Italy4
Institute of Experimental Physics, Slovak Academy of Sciences, Kosice, Slovakia.The trigger and data acquisition systems in the ALICE experiment have undergone significant changes in the last year. This is (i) in response to the incorporation of new detectors, (ii) the result of the use of front-end buffering schemes in the ALICE sub-detectors, and (iii) because of new more pessimistic estimates of the data volume generated by the Time Projection Chamber (TPC). In this report, we review the specification for the updated ALICE Central Trigger and examine how it might be implemented using currently available electronics components. The User Requirement Document and the Technical Specification for this system are being discussed by the ALICE collaboration.
A front end ASIC for the Dimuon arm trigger of the ALICE experiment
Laurent Royer, Laboratoire de Physique Corpusculaire, Clermont-Ferrand, France
Laurent Royer, Gerard Bohner, Jacques Lecoq
LPC Clermont-Ferrand
For the ALICE collaboration
A first prototype of the front-end ASIC dedicated to the trigger detector of the dimuon arm of ALICE has been designed and tested in the Laboratoire de Physique Corpusculaire of Clermont-Ferrand. This setup is based on the Resistive Plate Chamber (RPC), a gaseous detector which can be operated either in streamer or avalanche mode. The streamer mode has the advantage of providing large signals that can be discriminated without amplification whereas the avalanche mode presents a better rate capability and time resolution with conventional discrimination techniques. Since we proposed to operate the RPCs in streamer mode in ALICE, we have studied a new discrimination technique in order to obtain a time resolution better than 2ns in this mode. The method used in this dedicated circuit is described, performances and tests results are given, as well as the evaluation done in the test beam of summer 2000.
First-Level End-Cap Muon Trigger System for ATLAS
Kazumi Hasuko, University of Tokyo, Japan
K. Hasuko, T. Kobayashi, T. Niki, D. Toya, Y. Katori (University of Tokyo)
O. Sasaki, M. Ikeno, T.K. Ohska (High Energy Accelerator Research Organization KEK),
C. Fukunaga, H. Kano (Tokyo Metropolitan University),
H. Sakamoto, S. Nishida (Kyoto University),
H. Kurashige and R. Ichimiya (Kobe University)
We present the first-level end-cap muon trigger system for ATLAS. The system has the main tasks which are to identify bunch crossings and to make trigger decisions for high transverse-momentum muon candidates. It is being developed under requirements on trigger electronics: e.g. trigger rate, latency, acceptable number of tracks, etc. Such the requirements, trigger scheme, and overview of trigger logic are shown in this presentation. Details of the logic are given in the following presentation.
Study of LVDS Serial Links for the ATLAS Level-1 Calorimeter Trigger
Juergen Thomas, University of Mainz, Mainz, Germany
G.Anagnostou, P.Bright-Thomas, J.Garvey, R.Staley, W.Stokes, S.Talbot, P.Watkins, A.Watson
University of Birmingham, Birmingham, UK
R.Achenbach, P.Hanke, D.Husmann, M.Keller, E.-E.Kluge, J.Krause, K.Mahboubi, R.Megele, K.Meier, U.Pfeiffer, V.Schatz, K.Schmitt, C.Schumacher, B.Stelzer, O.Stelzer, P.Stock, E.Ulses
University of Heidelberg, Heidelberg, Germany
B.Bauss, K.Jakobs, U.Schaefer, J.Thomas, University of Mainz, Mainz, Germany
E.Eisenhandler, W.R.Gibson, M.P.J.Landon, Queen Mary and Westfield College, London, UK
B.M.Barnett, I.P.Brawn, J.Edwards, C.N.P.Gee, A.R.Gillman, R.Hatley, K.Jayananda, V.J.O.Perera, A.A.Shah, T.P.Shah, Rutherford Appleton Laboratory, Chilton, Didcot, UK
C.Bohm, M.Engstrom, S.Hellman, S.B.Silverstein, University of Stockholm, Stockholm, Sweden
This paper presents an evaluation of the proposed LVDS serial data transmission scheme for the ATLAS level-1 calorimeter trigger. Approximately 7000 high-bandwidth links are required to carry data into the level-1 processors from the preprocessor crates. National Semiconductor's Bus LVDS serialiser/deserialiser chipsets offer low power consumption at low cost and synchronous data transmission with minimal latency. Test systems have been built to measure real-time bit error rates using pseudo-random binary sequences. Results show that acceptable error rates better than 10^-13 per link can be achieved through compact cable connector assemblies over distances up to 20m.
CMS Regional Calorimeter Trigger High Speed ASICs
Wesley Smith, University of Wisconsin, Madison, WI, USA
P. Chumney, S. Dasu, M. Jaworski, J. Lackey, W.H. Smith
University of Wisconsin - Madison
The CMS regional calorimeter trigger system detects signatures of electrons/photons, taus, jets, and missing and total transverse energy in a deadtimeless pipelined architecture. This system contains 19 crates of custom-built electronics. Much of the processing in this system is performed by five types of 160 MHz digital ASICs. These ASICs have been designed in the Vitesse submicron high-integration gallium arsenide gate array technology. The five ASICs perform data synchronization and error checking, implement board level boundary scan, sort ranked trigger objects, identify electron/photon candidates and sum trigger energies. The design and simulation of these ASICs and prototyping results are presented.
A Demonstrator for the ATLAS Level-1 Muon Trigger Interface to the Central Trigger Processor
Philippe Farthouat, CERN, Geneva, Switzerland
A. Corre, N. Ellis, P. Farthouat, Y. Hasegawa, G. Schuler, C. Schwick, R. Spiwoks
CERN
The Level-1 Muon Trigger Interface (MUCTPI) to the Central Trigger Processor (CTP) receives trigger information from the detector- specific logic of the muon trigger. This information contains up to two muon-track candidates per sector. The MUCTPI combines the information of all sectors and calculates total multiplicity values for each of six pT thresholds. It avoids double counting of single muons by taking into account that some of the trigger sectors overlap. The MUCTPI sends the multiplicity values to the CTP which takes the final Level-1 decision. For every Level-1 Accept the MUCTPI sends region-of-interest information to the Level-2 trigger and event data to the data acquisition system. A demonstrator of the MUCTPI has been built which has the performance of the final system but uses a simplified algorithm for calculating the overlap. The functionality and the performance of the demonstrator are presented.
The Trigger Menu Handler for the ATLAS Level-1 Central Trigger Processor
Ralf Spiwoks, CERN, Geneva, Switzerland
N. Ellis, P. Farthouat, G. Schuler, R. Spiwoks
CERN
The role of the Central Trigger Processor (CTP) in the ATLAS Level-1 trigger is to combine information from the calorimeter and muon trigger processors, as well as from other sources, e.g. calibration triggers, and to make the final Level-1 decision. The information sent to the CTP consists of multiplicity values for a variety of pT thresholds, and of flags for ET thresholds. The algorithm used by the CTP to combine the different trigger inputs allows events to be selected on the basis of menus. Different trigger menus for different run conditions have to be considered. In order to provide sufficient flexibility and to fulfil the required low latency, the CTP will be implemented with look-up tables and programmable logic devices. The trigger menu handler is the tool that translates the human-readable trigger menu into the configuration files necessary for the hardware, stores several prepared configurations and down-loads them into the hardware on request. An automatic compiler for the trigger menu and a prototype of the trigger menu handler have been implemented.
The performance of a Pre-Processor Multi-Chip Module for the ATLAS Level-1 Trigger
Ulrich Pfeiffer, University of Heidelberg, Heidelberg, Germany
R.Achenbach, P.Hanke, D.Husmann, M.Keller, E.-E.Kluge, J.Krause, K.Mahboubi, R.Megele, K.Meier, U.Pfeiffer, V.Schatz, K.Schmitt, C.Schumacher, B.Stelzer, O.Stelzer, P.Stock, E.Ulses
University of Heidelberg, Heidelberg, Germany
We have built and tested a mixed signal Multi-Chip Module (MCM) to be used in the Pre-Processor of the ATLAS Level-1 Calorimeter Trigger. The MCM performs high speed digital signal processing on four analogue trigger input signals. Results are transmitted serially at a serial data rate of 800 MBd. Nine chips of different technologies are mounted on a four layer copper substrate. Analogue-to-digital converters and serialiser chips are the major consumers of electrical power on the MCM, which amounts to 7.5 Watts for all dies. Special cut-out areas are used to dissipate heat directly to the copper substrate. In this paper we report on design criteria, chosen MCM technology for substrate and die mounting, experiences with the MCM operation and measurement results.
Readout system for the CMS RPC Muon Trigger
Krzysztof Pozniak, Warsaw University of Technology, Institute of Electronics Systems, Warsaw, Poland
Krzysztof Kierzkowski a, Ignacy M. Kudla a, Esko Pietarinen b, Michal Pietrusilski a,
Krzysztof Pozniak c
a
Warsaw University, Institute of Experimental Physics,b
Univ.of Helsinki Fac.of Science, Helsinki Institute of Physics HIP,c
Warsaw University of Technology, Institute of Electronics SystemsThe CMS detector will have a dedicated subdetector (RPC chambers) to identify muons, measure their transverse momenta pt, and determine the bunch crossing from which they originate. Trigger algorithm is based on muon track search and classification in raw data from the RPC chambers. Trigger system can be built in the control room (far away from detector) where all trigger data are concentrated. Dedicated synchronous compression/decompression algorithm is used to sent all data for each bunch crossing via optical links. Readout system uses the same data as Trigger system and will be placed in Trigger Rack. The idea of readout system and its limitations are discussed. Paper includes description of prototype boards and test results on synchronous CERN test beam.
An FPGA-based implementation of the CMS Global Calorimeter Trigger
Dave Newbold, University of Bristol, Bristol, UK
J. Brooke (University of Bristol) D. Cussans (University of Bristol) G. Heath (University of Bristol) A. J. Maddox (Rutherford Appleton Laboratory) D. Newbold (University of Bristol, Corresponding Author) P. Rabbetts (Rutherford Appleton Laboratory)
We present a new design for the CMS Level-1 Global Calorimeter Trigger, based upon FPGA and commodity serial link technologies. For each LHC bunch-crossing, the GCT identifies the highest pt electron, photon and jet candidates; calculates scalar and vector total transverse energies; performs jet-counting, and provides real-time luminosity estimates. The pipelined system logic is implemented using 0.18um Xilinx FPGAs. The traditional system backplane is replaced by fast serial links for trigger data, and Ethernet for control. These technologies allow an improvement in system flexibility and a considerable reduction in cost, complexity and design time compared to an ASIC/VME-based solution.
Performance of a High Voltage Power Supply incorporating a Ceramic Transfomer
Masatosi Imori, ICEPP, University of Tokyo, Japan
Yoshiaki Shikaze (Department of Physics, Faculty of Science, University of Tokyo), Masatosi Imori (ICEPP, University of Tokyo), Hideyuki Fuke (Department of Physics, Faculty of Science, University of Tokyo), Hiroshi Matsumoto (ICEPP, University of Tokyo), Takasi Taniguchi (National Laboratory for High Energy Physics(KEK)
This paper describes the performance of a high-voltage power supply incorporating a ceramic transformer. Since the transformer doesn't include any magnetic material the power supply can be operated under a strong magnetic field. In the article, the efficiency of the power supply is studied against various parameters. It was found that the efficiency reaches more than 50 percent when zero-voltage switching was realized. From a voltage source of 2V, the power supply can supply 3000V at a 21 megohm load. A voltage source of 5V is enough to supply 4000V at the same load.
Multichannel system of fully isolated HV power supplies for silicon strip detectors
Piotr Malecki, Institute of Nuclear Physics, Cracow, Poland
Edward Gornicki (Institute of Nuclear Physics, Cracow, Poland)
Stefan Koperny (Faculty of Physics and Nuclear Techniques of UMM, Cracow)
Piotr Malecki (Institute of Nuclear Physics, Cracow)
A multichannel system of power supplies providing a bias voltage in the range of 0 - 410 V for silicon micro-strip detectors is presented. All channels are fully isolated allowing for flexible detector segmentation. A wide range of functions including e.g. a programmable current trip limit as well as a ramp-up and rump-down control independent for each channel are also described.
Switching Power Supply Technology for ATLAS LAr Calorimeter
Helio Takai, Brookhaven National Laboratory, Upton, NY, USA
H. Takai and J. Kierstead
Brookhaven National Laboratory
(for the ATLAS Liquid Argon collaboration)
The ATLAS liquid argon calorimeter is designing a switching power supply to be meet the harsh environmental requirements imposed by the location where they will be installed. In addition the design addresses the inaccessibility issue. We will present the design and available tests regarding radiation and magnetic field susceptibility.
Grounding and Shielding of the ATLAS TRT
Zbyszek Hajduk, Institute of Nuclear Physics, Cracow, Poland
for the TRT collaboration
This paper addresses practical considerations for the engineering of the grounding and shielding system of the ATLAS-TRT.
A ground system serves three primary functions: personnel safety, equipment and facility protection, and electrical-noise reduction. Defining the potential of each conductive material to be within certain margins achieves safety. A proper signal reference system together with shielding of sensitive as well as noisy parts provide noise reduction. Defining the potential of the conductive structures and building a signal-reference system inside the TRT, can be chosen within two philosophies: either strongly connecting everything together or trying to control the currents which flow in the system. The first one yields the lowest impedance between any two points of the system, but simultaneously allows loops and shield currents to flow inside the system. The second approach allows to break these loops and to ban shield currents from intruding the system through carefully provided low-impedance paths. Each ATLAS sub detector has to follow "The ATLAS Policy on Grounding and Power Distribution" which gives the following guidelines:
• [...] electrical isolation of all detector systems, [...]
• [...] floating low-voltage power supplies, [...]
• [...] floating high-voltage power supplies, [...]
• [...] data transmission, clock and trigger distribution through optical links or shielded twisted-pair cables, [...]
• [...] detector located inside a faraday cage. [...]
This negates the first philosophy at an intersystem level, but still allows it inside the sub detector. Only the final system will show all systematic effects which could not be predicted from a small prototype. Implementing provisions for both philosophies allows us to postpone the choice until more experience has been acquired. Therefore a way of realizing both approaches has been defined.
Design Considerations of Low Voltage DC Power Distribution for CMS Sub-Detectors
Claudio Rivetta, ETH, Zurich and CERN, Geneva, Switzerland
B.Allongue, F. Fontaine, F. Szoncso, G. Stefanini CERN Switzerland
S. Lusin, P. Robl University of Wisconsin, Madison, USA
J. Elias Fermilab, USA
C. Rivetta ETH Zurich/CERN Switzerland
A distinguishing feature of LHC detectors is the enormous number of front-end electronics (FE) channels in all of the sub-detectors. Low-voltage power supply systems in the range of multi-kilowatts are required to bias such electronic read-outs. Several configurations has been proposed and analyzed by the different groups showing particular advantages and disadvantages. For the CMS detector, the Hadronic Calorimeter (HCAL) and the Muon End-caps (EMU) have proposed a DC power distribution system based on DC-DC power switching converters. The topology of this DC power distribution is as follows: AC/DC converters in the control room are used to rectify the three phase mains and generate the primary 311 VDC voltage. Each rectifier supplies several DC-DC converters located in the cavern near the FE. The switching regulators convert the high voltage into appropriated low voltages that are locally distributed to the detector read-outs. Local regulation is performed in the FE at the board level using special linear low-dropout voltage regulators developed by CERN RD-49 collaboration. The main advantage of this topology is the reduction in volume of the distribution cables due to the relative low primary currents. Locating the DC-DC converters in the hostile environment of the detector cavern is a disadvantage due to the presence of magnetic fields and radiation. Analysis and tests are necessary to characterize the behavior of those units under such conditions and find acceptable solutions. Also, further studies and tests are necessary to mitigate the radiated and conducted noise generated by the switching converters, to ensure stability of multi-converter systems against interactions between units, etc. In this paper, tests conducted to validate the application of commercial units are reported and future tests are described. Also, an analysis of the overall system performance is presented along with guidelines for design and selection of the components are presented.
Electronic Design Automation tools for high-speed electronic systems
John Evans, CERN, Geneva, Switzerland
B.J. Evans , E. Calvo Giraldo, T. Motos Lopez
CERN, IT/CE
The LHC detectors will produce a large amount of data that will need to be moved very quickly. The signal-speeds and interconnect-density involved lead to difficult electrical design problems, particularly regarding signal-integrity issues. Various commercial Electronic Design Automation programs are now available to address these problems. These include 3-D full-wave electromagnetic-field solvers, SPICE-based circuit-simulation programs and printed circuit board signal-integrity point products. We will show how these seemingly disparate tools can be used in a complementary fashion to provide detailed studies of detector-electronic design. Two case studies will be presented from LHC experiments.
Development of Fluorocarbon Evaporative Cooling Recirculators and Controls for the ATLAS Pixel and Semiconductor Tracking Detectors
Greg Hallewell, Rutherford Appleton Laboratory, Didcot, UK and CCPM, Marseille, France
C. Bayer (Wuppertal), M. Bosteels (CERN), P. Bonneau (CERN), H. Burckhart (CERN), D. Cragg (RAL), R. English (RAL), G. Hallewell (RAL/CPPM), B. Hallgren (CERN), S. Kersten (Wuppertal), P. Kind (Wuppertal), K. Langedrag (Oslo), S. Lindsay (Melbourne), M. Merkel (CERN), S. Stapnes (Oslo), J. Thadome (Wuppertal), V. Vacek (CERN/Czech Technical University, Prague)
We report on the development of evaporative fluorocarbon cooling recirculators and their control systems for the ATLAS Pixel and Semiconductor Tracking (SCT) detectors. A prototype circulator uses a hermetic, oil-less compressor and C3F8 refrigerant. The mass flow rate to each circuit is individually tuned via feedback according to the circuit load variation, using dome-loaded pressure regulators in the liquid supply lines piloted with analog compressed air from DAC-driven voltage to pressure ("V2P") converters. Evaporated C3F8 exits each circuit through an analog air-piloted back-pressure regulator, which sets the circuit operating temperature. A hard-wired thermal interlock system automatically cuts power to individual silicon modules should their temperature exceed safe values. All elements of the circulator and control system have been implemented in prototype form. Temperature, pressure and flow measurement in the circulation system uses standard ATLAS CanBus LMB ("Local Monitor Box") DAQ and CanBus interfaced DACs in a large (300 + channel) multi-drop Can network administered through a BridgeView user interface. Prototype 16 channel interlock modules have been tested. The performance of the circulator under steady state, partial-load, and transient conditions is discussed and future developments are outlined.
Trigger Throttling System for CMS DAQ
Attila Racz, CERN, Geneva, Switzerland
This document is a first attempt to define the basic functionnalities of the TTS in the CMS DAQ. Its role is to adapt the trigger pace to the DAQ capacity in order to avoid congestions and overflows at any stage of the readout chain. The different possibilities for the TTS to measure the load on parts of the chain are examined. It clearly appears that one part of the chain needs fast reaction time (few tens of useconds) whereas the rest of the chain can afford longer reaction time, available to nowadays processors.
The CMS DT Muon DDU: a PMC based interface between frontend and data-acquisition
Roberto Cirio, INFN, Torino, Italy
F.Benotto, F.Bertolino, R.Cirio, G.Dellacasa
INFN Torino
CMS will use gas drift tubes as active part of the barrel muon sub-detector. In total 200.000 wires will be readout by TDCs and signals will be sent to data acquisition. The entrance door to the standard CMS DAS will be a board (Detector Dependent Unit - DDU) that will be specific to each sub-detector. We have built a PMC based prototype of the DT muon DDU that features two input channels with Optolink, data check and reconstruction with FPGA and PCI slave output through a FIFO. A description of the board and the FPGA schematics will be given and results from lab tests will be shown.
Timing, Trigger and Control distribution and dead-time control in ATLAS
Per Gunnar Gällnö, CERN, Geneva, Switzerland
The RD12 TTC system is the backbone for the timing, trigger and control distribution in ATLAS. The last developments of TTC modules as well as their use in ATLAS will be presented. The strategy for the dead-time control of the experiment will also be presented.
Specification and Simulation of ALICE DAQ System
Giovanna Di Marzo Serugendo, CERN, Geneva, Swtizerland
Giovanna Di Marzo Serugendo, CERN / Predrag Jovanovic, School of Physics and Astronomy, University of Birmingham / Pierre Vande Vyvre, CERN / Orlando Villalobos Baillie, School of Physics and Astronomy, University of Birmingham
for the ALICE Collaboration.
The Trigger and Data Acquisition System of the ALICE experiment has been designed to support the high bandwidth expected during the LHC heavy ion run. A model of this system has been developed. The goal of this model is twofold. First, it allows to verify that the system-level design is consistent and behaves according to the requirements. Second, it is used to evaluate the theoretical system performances using the measurements done on sub-systems prototypes. This paper presents the specification and simulation of a model of the ALICE DAQ system using a commercial tool (Foresight). This specification is then executed to simulate the system behaviour.
The ATLAS Liquid Argon Calorimeters Reaout Out Drivers
Julie Prast, Laboratoire de Physique des Particules, Annecy-le-Vieux, France
for the ATLAS Collaboration
The Read Out Driver (ROD) for the Liquid Argon calorimeters front-end electronics of the ATLAS detector is described. Those ROD modules are designed for the ATLAS electromagnetic, hadronic end-cap and forward calorimeters. Each ROD module receives data from two Front-End Boards (FEB). The FEB amplifies, shapes, samples and stores the signal from 128 calorimeters cells at the frequency of the LHC (40 MHz). Then, the data are digitized and sent to the ROD modules for each Level-1 trigger (maximum rate of 100 kHz). These data are transmitted by two 32 bits data optical links. The principal function of the ROD is to reconstruct the precise energy and timing of each cell signal from the time samples. In addition, the ROD checks and histograms the data. The treated data are then sent towards the Read Out Buffers (ROB), according to a defined format, where they are stored. A demonstrator system consisting of a mother board and several daughter boards Processing Units (PU), is under development. The goal of the demonstrator is to prove the feasibility of the project and serve as an intermediate step towards the construction of the final ROD module for the ATLAS experiment. The design of the prototypes are presented here. The mother board is a full size 9U VME module able to carry four daughter boards. It allows all the input/output connections with the FEB and ROB, the controls of the board and the VME interface. This board offers maximum modularity and allows the development and testing of different Processing Units (PU). Three PU are being studied. Two are designed with the Texas Instrument TMS320C6202 fixed point DSP, while the other one is designed with the Analog Devices 21160 floating point DSP. These PU present the same overall architecture. The example of the Analog Devices PU will be taken. Each PU treats data from an half FEB (8 ADC). Each ADC digitizes signals from 8 calorimeters cells. Each channel is composed of five 12-bit samples. These FEB data enter an FPGA at the speed of 40 MHz They are parallelized, parity checked and formatted before being buffered into the internal FIFO of the FPGA. This FIFO is connected to the external memory bus of the DSP. Once the DSP finishes the processing of the event, the results are formatted according to the ROB format and then put into a FIFO. This output FIFO is read by the mother board Output Controller. The PU also contains a communication port, through which all the control of the board is done. It uses the DSP link ports to communicate with the mother board VME interface. It is also used to send monitoring or debugging information to the local CPU. All the communications between the DSP and its peripheral are done by Direct Memory Access (DMA), thus being transparent for the DSP core. Results for the different PU will be presented and compared (functioning, performance, DSP algorithm). The first tests have shown that the demonstrator board meets the ATLAS requirements in term of bandwidth and accuracy, although the DSP used are not the next generation of DSP foreseen for the final version of the board.
ATLANTIS - a modular, hybrid FPGA/CPU processor for the ATLAS Readout Systems
Matthias Muellerl, University of Mannheim, Mannheim,Germany
Christian Hinkelbein - Institute of Computer Science V, University of Mannheim, Germany Andreas Kugel - Institute of Computer Science V, University of Mannheim, Germany
Reinhard Maenner - Institute of Computer Science V, University of Mannheim, Germany Matthias Mueller - Institute of Computer Science V, University of Mannheim, Germany
Harald Simmler - Institute of Computer Science V, University of Mannheim, Germany
Holger Singpiel - Institute of Computer Science V, University of Mannheim, Germany
Lorne Levinson - Weizmann Institute of Science, Rehovot, Israel
ATLANTIS realizes a hybrid architecture comprising a standard PC platform plus different FPGA based modules for high performance I/O (AIB) and computing (ACB). CompactPCI provides the basic communication mechanism enhanced by a private bus. The system can be tailored to a specific application by selecting an appropriate combination of modules. Acceleration of computing intensive ATLAS LVL2 trigger tasks has been demonstrated with an ACB based system. The ATLAS RoD and RoB systems profit from the flexible and highly efficient AIB I/O architecture. Various high speed interface modules (S-Link/M-Link) are supported, allowing up to 28 links per CompactPCI crate.
The new ATLAS TRT read-out system
Peter Lichard, CERN, Geneva, Switzerland
The ATLAS TRT detector is very demanding in terms of electronics performance because of the high occupancy of the detector. A new version of the full read-out system, including two new ASICs and the new back-end modules, has been designed and tested successfully at 40 MHz clock rate and high trigger rate on a detector prototype. A description of this system will be given, as well as test results and plan for future scaling.
Off-Detector Electronics for a High-Rate CSC Detector
Kurt Vetter, Brookhaven National Laboratory, Upton, NY, USA
A. Gordeev, V. Gratchev, A. Kandasamy, P. O'Connor, V. Polychronakos, V. Tcherniatine,
K. Vetter
Brookhaven National Laboratory
J. Dailing, N. Drego, D. Hawkins, A. Lankford, Y. Li, S. Pier, M. Schernau, D. Stoker,
B. Toledano
University of California, Irvine
The off-detector electronics system for a high-rate muon Cathode Strip Chamber (CSC) is described. The CSC's are planned for use in the forward region of the ATLAS muon spectrometer. The electronics system provides control logic for switched-capacitor array analog memories on the chambers and accepts a total of nearly 37 Gbyte/s of raw data from 64 chambers. The architecture of the system is described as are some important signal processing algorithms and hardware implementation details.
Design of the Front-End Driver card for CMS Silicon Microstrip Tracker Readout.
John A. Coughlan, CLRC Rutherford Appleton Laboratory, Oxon, UK
S.A. Baird, K.W. Bell, J.A. Coughlan, R. Halsall, W.J. Haynes, I.R. Tomalin
CLRC Rutherford Appleton Laboratory, Oxon, UK.
E. Corrin
Imperial College, London, UK.
The CMS silicon microstrip tracker has the order of 10 million readout channels. The tracking readout system employs several hundred off-detector Front-End Driver (FED) cards to digitise, sparsify and buffer analogue data arriving via optical links from on-detector pipeline chips (APVs). This paper describes the baseline design of the Front-End Driver card which is implemented as a 96 ADC channel (10 bits) 9U VME board. At typical LHC operating conditions the total input data rate per FED after digitisation of over 3 GBytes/s must be substantially reduced. The required digital data processing is highly parallel and heavily pipelined and is carried out in several large FPGAs. The process of FPGA digital design using VHDL and design optimisation with board level simulation together with the tools employed are discussed.
Software developments for the Readout Unit Prototypes for CMS DAQ System
Eric Cano, CERN, Geneva, Switzerland
M.Bellato (INFN Sezione di Padova)
G.Antchev, E.Cano, S. Cittolin, B.Faure, D.Gigi, J.Gutleber, C.Jacobs, F. Meijers, E. Meschi, L.Orsini, L. Pollet, A.Racz,D. Samyn, N. Sinanis,W. Schleifer, P. Sphicas (CERN)
A.Ninane (Université Catholique de Louvain)
In the CMS data acquisition system, the readout unit is a fast buffering device for short term storage of event fragments. It interfaces front end devices and builder data network. The current Readout Unit prototypes are based on two homegrown hardware boards, the Readout Unit Memory (RUM) and the Readout Unit I/O (RUIO). These boards are equipped with an IOP. Several OS environments for this processor are developed. The software running on those boards will have to setup and control the input and output processes. Fast IOP to host communications are experimented. A software test environment is specifically designed for test and validation of the complex memory management of the RUM.
Implementation of a Serial Protocol for the Liquid Argon Atlas Calorimeter (SPAC)
Bertrand Laforge, Laboratoire de Physique Nucléaire et de Hautes Energies, Paris, France
F.Hubaut, B.Laforge, O.Le Dortz, D.Martin, Ph. Schwemling
LPNHE Paris
The Serial Protocol for the Atlas Calorimeter (SPAC) has been designed to provide the loading and reading of all parameters of the front-end boards of the ATLAS Liquid Argon Calorimeter.
This single master / multiple slaves serial protocol is designed to be transmitted optically and electrically, at up to 10 Mbits/s, and enables broadcast or individual transfers from the master to one or a set of slaves.
Some test results about the SPAC performance and its implementation within the ATLAS framework will be presented.
The Detector Control System for the HMPID in ALICE Experiment at LHC
Giacinto De Cataldo INFN, Bari, Italy
for the ALICE collaboration,
The Detector Control System (DCS) of ALICE at LHC will allow a hierarchical consolidation of the participating sub-detectors to obtain a fully integrated detector operation. The High Momentum Particle Identification Detector (HMPID), based on a Ring Imaging Cherenkov, is one of the ALICE sub-detectors. Its DCS has to ensure the detector configuration, operation in standalone mode for maintenance, monitoring, control and integration in the ALICE DCS. In this paper a status report of the HMPID DCS is presented. Costs and merits of its implementation in function of the chosen HV and LV systems will also be reported.
HDMC: An object-oriented approach to hardware diagnostics
Ulrich Pfeiffer, University of Heidelberg, Heidelberg, Germany
V.Schatz, C.Schumacher University of Heidelberg, Heidelberg, Germany
M.P.J.Landon Queen Mary and Westfield College, London, UK
A software package has been developed, which provides direct access to hardware components for testing, diagnostics or monitoring purposes. It provides a library of C++ classes for hardware access and a corresponding graphical user interface. Special care has been taken to make this package convenient to use, flexible and extensible. The software has been successfully used in development of components for the pre-processor system of the ATLAS level-1 calorimeter trigger, but it could be useful for any system requiring direct diagnostic access to VME based hardware.
(cd 22 August 2000)