Danek Kotlinski, Paul Scherrer Institut, Villigen, Switzerland

In the presentation the readout architecture of the CMS pixel detector will be discussed. The data rate and volume expected at the full LHC luminosity and it's implication on the readout chip will be presented. The overall pixel readout system and the integration with the CMS data acquisition system will be emphasized. The first pixel detector layer will be placed at 4cm from the beam in a very high radiation environment. Some aspects of the radiation hardness and its impact on the readout design will be discussed.

Front-End electronics for ATLAS Pixel detector

Laurent Blanquart, Centre de Physique des Particules, Marseille, France

The electronics subgroup of the ATLAS pixel detector has pursued an iterative programme of design development over the last 3 years. The initial phase of this demonstrator programme was aimed at realizing ATLAS specification front-end chips using radiation-soft technologies, the designs of which could then easily be adapted for fabrication at rad-hard foundries. First realistic prototypes were designed in 2 parallel efforts (Europe and US) in 97/98, producing a rad-soft AMS prototype (FE-A/FE-C) and a rad-soft HP prototype (FE-B). Throughout 98/99, more than 60 single chip assemblies and 10 electrically functional modules were produced and have been studied extensively in lab and during 7 testbeam periods at SPS. All of the ATLAS requirement issues (except for the radiation hardness) were addressed in detail such as noise, threshold dispersion, timewalk, digital/analog crosstalk, power supply rejection...with very encouraging results. These measurements on both single chip assembly and module are presented. A unified design approach has been adopted for rad-hard front-end chips, i.e. all working on the same design to be implemented in 2 rad-hard processes. The rad-hard designs, namely FE-D for the DMILL process and FE-H for the Honeywell process, maintain the spirit of the demonstrator programme (i.e. pin compatibility, same pixel pitches...) and combine features of both FE-A/C and FE-B. FE-D has been received in Oct. 99 and FE-H will be submitted during summer 2000.

The ALICE Silicon Pixel Detector Readout System

Michael Burns, CERN, Geneva, Switzerland

Federico ANTINORI ¹, Jaroslav BAN ², Michael BURNS ¹, Michael CAMPBELL ¹, Peter CHOCHULA ^{1, 3}, Fabio FORMENTI ¹, Tullio GRASSI ⁴, Alexander KLUGE ¹, Pierluigi LISCO ⁵, Franco MEDDI ^{1, 6}, Michel MOREL ¹, Giorgio STEFANINI ¹, Kennith WYLLIE ¹

for the ALICE collaboration.

¹ CERN, 1211 Geneva 23, Switzerland

² Institute of Experimental Physics, 04353 Kosice, Slovakia

³ Institute of Experimental Physics, 84215 Bratislava, Slovakia

⁴ Formerly CERN, 1211 Geneva 23, Switzerland

⁵ Universita degli Studi di Bari, I-70126 Bari, Italy

⁶ Universita di Roma La Sapienza, I-00185 Roma, Italy

The ALICE SILICON PIXEL DETECTOR (SPD) is located within the Inner Tracking System (ITS) and is the detector with the highest active channel density and closest to the point of interaction. Approximately 10 million active electronic channels, contained in a volume of 34 litres, have to be read out and controlled. Such a high density in an inaccessible position has imposed a high degree of multiplexing to reduce the amount of cabling to a minimum. This paper will describe the proposed architecture of the readout and control paths.

First results from the ALICE1LHCb pixel chip

Roberto Dinapoli, University and INFN Bari, Italy

K. Wyllie¹, M. Burns¹, M. Campbell¹, E. Cantatore¹, V. Cencelli², P. Chochula¹, R. Dinapoli³,  S. Easo⁴, F. Formenti¹, T. Grassi¹, E. Heijne¹, P. Jarron¹,
K. Kloukinas¹, P. Lamanna³, F. Meddi¹, M. Morel¹, V. O’Shea⁴, V. Quiquempoix¹, D. San Segundo Bello⁵, W. Snoeys¹, L. Van Koningsveld¹

¹ CERN, Geneva, Switzerland

² INFN Rome, Italy

³ University and INFN Bari, Italy

⁴ University of Glasgow, Glasgow, UK

⁵ NIKHEF, Amsterdam, The Netherlands.

ALICE1LHCb is an integrated circuit to read out silicon pixel sensors used for particle tracking in the ALICE Silicon Pixel Detector or for particle identification in the LHCb RICH. It has been fabricated in a commercial 0.25 micron technology, with consideration given to radiation tolerance, testability and system integration. Results from the first laboratory measurements are presented. These include characterisation of the front-end, with measurements of noise and threshold uniformity. The functionality of the digital circuitry is described whilst operating the chip in both ALICE and LHCb modes. The use of the serial JTAG interface is outlined, in terms of configuring the chip and testing connectivity at the system level.

Progress in development of the readout chip for the ATLAS Semiconductor Tracker

Wladyslaw Dabrowski, Faculty of Physics & Nuclear Techniques, UMM, Krakow, Poland

W. Dabrowski, Faculty of Physics and Nuclear Techniques, UMM, Krakow, Poland

F. Anghinolfi, CERN, Geneva, Switzerland

A. Clark, University of Geneva, Switzerland

T. Dubbs, SCIPP, UCSC Santa Cruz, CA, USA

L. Eklund, CERN, Geneva, Switzerland

M. French, Rutherford Appleton Laboratory, Didcot, UK

W. Gannon, Rutherford Appleton Laboratory, Didcot, UK

A. Grillo, SCIPP, UCSC Santa Cruz, CA, USA

P. Jarron, CERN, Geneva, Switzerland

J. Kaplon, CERN, Geneva, Switzerland,

J. Kudlaty, MPI, Munich, Germany

C. Lacasta, IFIC, Valencia, Spain

D. LaMarra, University of Geneva, Switzerland

D. Macina, University of Geneva, Switzerland

I. Mandic, Jezef Stefan Institute, Ljubljana, Slovenia

G. Meddeler, Lawrence Berkeley National Laboratory, Berkeley, CA, USA

H. Niggli, Lawrence Berkeley National Laboratory, Berkeley, CA, USA

P.W. Phillips, Rutherford Appleton Laboratory, Didcot, UK

P. Weilhammer, CERN, Geneva, Switzerland

E. Spencer, SCIPP, UCSC Santa Cruz, CA, USA

R. Szczygiel, CERN, Geneva, Switzerland

A. Zsenei, University of Geneva, Switzerland

The development of the ABCD chip for the binary readout of silicon strip detectors in the ATLAS Semiconductor Tracker has turned into a pre-production phase, following comprehensive evaluation of the ABCD2T prototype chip. The ABCD2T design is one of the two options of the binary readout architecture which have been developed for the ATLAS SCT. It is manufactured in the DMILL process and comprises in a single chip all blocks of the binary readout architecture. In the paper we will present a summary of the ABCD2T performance as well as design issues and performance of the ABCD3T chip which is expected to be the final version for the ATLAS SCT detector.

Analogue Read-Out Chip for Si Strip Detector Modules for LHC Experiments

Jan Kaplon, CERN, Geneva, Switzerland

E. Chesi¹, J. A. Clark², V. Cindro³, W. Dabrowski⁴, D. Ferrere², G. Kramberger³, J. Kaplon¹, C. Lacasta⁵, J. Lozano^1, M. Mikuz³, C. Morone², S. Roe¹,
A. Rudge¹, R. Szczygiel⁶, M.Tadel³, P. Weilhammer¹, A. Zsenei²

¹ CERN, 1211 Geneva 23, Switzerland

² University of Geneva, Switzerland

³ Jozef Stefan Institute, Ljubljana, Slovenia

⁴ Faculty of Physics and Nuclear Techniques, UMM, Krakow, Poland

⁵ IFIC, Valencia, Spain

⁶ Institute of Nuclear Physics, Krakow, Poland

We present a 128-channel analogue front-end chip SCT128A for readout of silicon strip detectors employed in the inner tracking detectors of LHC experiment. The architecture of the chip and critical design issues are discussed. The performance of the chip has been evaluated in detail in the bench test and is presented in the paper. The chip is used to read out prototype analogue modules compatible in size, functionality and performance with the ATLAS SCT base line modules. Several full size detector modules equipped with SCT128A chips has been built and tested successfully in the lab with b particles as well as in the beam test.

Production data base for the ATLAS-SCT front-end ASICs

Carlos Lacasta, Instituto de Física Corpuscular (IFIC), Valencia,Spain

ATLAS SCT will soon enter into the production phase. The large amount of electronics ASICs to be handled requires a well defined procedure both to monitor the performance of the production and to trace the distribution of the components down to the individual module level. That involves not only the development of a testing policy and method for the ASICs, with the corresponding criteria defining the pass/fail tagging of the chips, but also a mechanism to handle the substantial amount of data generated in the process. This paper tries to cover and discuss those aspects of the production and will describe the approach followed by the ATLAS-SCT towards the design of a testing procedure and the development of a production database.

The CMS Tracker APV25 0.25m CMOS readout chip

Geoff Hall, Blackett Laboratory, Imperial College, London, UK

M. J. French, L. L. Jones, Q. Morrissey, A. Neviani, R. Turchetta

Rutherford Appleton Laboratory, Didcot, OXON, OX11 0QX, United Kingdom

J. Fulcher, G. Hall, E. Noah, M. Raymond

Blackett Laboratory, Imperial College, London SW7 2AZ, United Kingdom

K. Kloukinas, P. Moreira

CERN, 1211 Geneva 23, Switzerland

N. Bacchetta, D. Bisello, G. Marseguerra, J. Wyss

University of Padova, Italy

The APV25 is the 128-channel readout chip for silicon microstrips in the CMS tracker. It is the first major chip for a high energy physics experiment to exploit a modern commercial 0.25m CMOS technology. Experimental characterisation of the circuit shows full functionality and excellent performance both in pre- and post-irradiation conditions. The measured noise is significantly reduced compared to earlier APV versions. Automated on-wafer testing of many chips has demonstrated a very high yield. A summary of the design and detailed results from measurements will be presented. Operation of the chip in conjunction with other CMS system components will be described.

APVMUX, An analogue multiplexing chip for the CMS Tracker

Markus French, Rutherford Appleton Laboratory, Didcot, UK

M. French, P. Murray, L. Jone (Rutherford Appleton Laboratory)

M. Raymond (Imperial College)

A chip for multiplexing pairs of APV25 chip outputs onto differential analogue cable has been designed. The chip includes SEU tolerant logic to detect and control the APV signal phasing and termination resistors required by the APV25 chip. The termination impedance and switching phase are programmable by I2C and bond control respectively. The design and implementation is outlined and test results presented.

The CMS Tracker front-end and control electronics in an LHC like beam test

Nancy Marinelli, Blackett Laboratory, Imperial College, London, United Kingdom

W.Beaumont(b), M.Bozzo(f), C.Civinini(e), J.Coughlan(k), F.Drouhin(h), P.Figueiredo(d), L.Fiore(c), A.Giassi(j), K.Gill (d), J.Gutleber(d), G.Hall(g), L.Latronico(f), C.Ljuslin(d), M.Loreti(i), C.Maazouzi(l), S.Marchioro(d), N.Marinelli(g), C. Paillard(d), T.Parthipan(k), P.Siegrist(d), L.Silvestris(c,d), I.Tomalin(k), A.Tsirou(d), P.G.Verdini(j), P.Walsham(g),

B.Wittmer(a), A.Zghiche(l,d), F.Vasey (d)

(a) RWTH, I. Physikalisches Institut, Aachen, Germany,

(b) Universitaire Instelling Antwerpen, Antwerpen, Belgium

(c) INFN, Sezione di Bari, Bari, Italy

(d) CERN, 1211 Geneva 23, Switzerland

(e) INFN, Sezione di Firenze, Firenze, Italy

(f) INFN, Sezione di Genova, Genova, Italy

(g) Blackett Laboratory, Imperial College, London SW7 2AZ, United Kingdom

(h) Universite de l’Haute Alsace, Mulhouse, France

(i) INFN, Sezione di Padova, Padova, Italy

(j) INFN, Sezione di Pisa, Pisa, Italy

(k) Rutherford Appleton Laboratory, Didcot, OXON, OX11 0QX, United Kingdom

(l) Institut de Recherches Subatomiques, IN2PS-CNRS Strasbourg, France

A complete prototype of the CMS tracker read-out and control system has been built using components that are very close to the final design. The system is based on analogue amplifier and pipeline memory chips (APV), analogue optical links transmitting at 40Mbps and a VME digitisation and data handling board (FED), supplemented by a control system which sets and monitors the components of the system. This system has been successfully operated for the first time under LHC like beam conditions, in a 25ns structured beam provided by the SPS at CERN, mainly aiming to test the synchronisation of the system and pile-up effects in a high trigger rate environment. Preliminary results are presented in this paper

Characterisation of the APVD read-out circuit for DC-Coupled Silicon Detectors (Final report)

Ulrich Goerlach, IReS, IN2P3/ULP, Strasbourg, France

J.D. Berst, C. Colledani, Y. Hu, R. Turchetta, LEPSI, IN2P3/ULP, 23 rue du Loess, BP20, F-67037 Strasbourg, France

G. Deptuch, U. Goerlach, C. Hu-Guo, P. Schmitt, IReS, IN2P3/ULP, 23 rue du Loess, BP20, F-67037 Strasbourg, France

M. Dupanloup, S. Gardien, IPNL IN2P3/CNRS, F-69622 Villeurbanne, France

The APVD integrated circuit for the front-end electronics of DC-coupled silicon detectors for CMS has been developed and produced in the radiation-hard process DMILL.The APVD_DC contains, like other members of the APV family 128 identical analog channels, each composed of a low noise preamplifier, a CR-RC shaper, an analog pipeline of 160 cells and a signal processing stage. A current compensation circuit is added in every preamplifier to sink the leakage current coming from the detector. We report on the final test results: the complete circuit has been tested and measured also in the presence of significant leakage currents up to 11 microampere which do not deteriorate the analog performance of the circuit like pulse shape dynamic range and adding about 300 ENC to the noise. Previous APVD circuits suffered from an instability problem in the analog stage of the circuit occurring at nominal bias values. The analog baseline of the new modified circuit is absolutely stable also under extreme operation conditions, like high bias currents demonstrating that the implemented solution stops indeed the oscillation of the circuit as we previously claimed based on extensive simulations of the circuit.

A Mixed Signal ASIC for the Silicon Drift Detectors of the ALICE Experiment in a 0.25 mm CMOS

Angelo Rivetti, CERN, Geneva, Switzerland and INFN, Torino, Italy

A. Rivetti ^1,2, G. Anelli ¹, F. Anghinolfi ¹, G. Mazza ², P. Jarron ¹

¹ CERN, CH-1211 Geneva 23, Switzerland

² INFN, Sezione di Torino, Via Pietro Giuria 1, 10125, Torino, Italy

A mixed signal integrated circuit developed for the read-out of Silicon Drift Detectors (SDDs) is presented. The chip contains 32 channels and 16 ADCs. Each channel is made of an amplifier and an analog pipeline with 256 cells. One ADC is shared by two adjacent channels. The circuit is optimized to match the specifications of the SDDs of the ALICE experiment, where large dynamic range and low power consumption are key issues. The input noise is calculated to be 200 e- rms for an input capacitance of 3pF and a detector dark current of 10nA. The power consumption is 5mW/channel.

Test results of the ALICE SDD electronic readout prototypes

Giovanni Mazza, INFN, Torino, Italy

G. Mazza[INFNTo], G. Alberici[INFNTo], G. Anelli[CERN], G.C Bonazzola[UniTo],

D. Cavagnino[UniTo], P.G. Cerello[INFNTo], P. De Remigis[INFNTo],

D. Falchieri[INFNBo], A. Gabrielli[INFNBo], E. Gandolfi[INFNBo],

P. Giubellino[INFNTo], M. Masetti[INFNBo], L.M. Montano[INFNTo],

D. Nouais[INFNTo], A. Rivetti[CERN][UniTo], F. Tosello[INFNTo],

A. Werbrouck[UniTo], R. Wheadon[INFNTo]

for the ALICE collaboration

Institutes:

[INFNTo]       INFN sezione di Torino, Italy

[INFNBo]       INFN sezione di Bologna, Italy

[UniTo]         Universita` di Torino, Italy

[CERN]         CERN, Geneve, Switzerland

The first prototypes of the front-end electronic of the ALICE silicon drift detectors has been designed and tested. The integrated circuits have been designed using state-of-the-art technologies and, for the analog parts, with radiation-tolerant design techniques. In this paper the test results of the building blocks of the PASCAL chip and the first prototype of the AMBRA chip are presented. The prototypes fully respect the ALICE requirements; owing to the use of deep-submicron technologies together with radiation-tolerant layout techniques, the prototypes have shown a tolerance to a radiation dose much higher than the one foreseen for the ALICE environment.

FEE tracker module developments and production for ALICE and STAR

Jean-Robert Lutz, IReS, Strasbourg, France

L. Arnold, G. Baudot, D. Bonnet, J.P. Coffin, M. Germain, C. Gojak, B. Hippolyte, C. Kuhn, J.-R. Lutz, C. Suire, A. Tarchini

IReS (Institut de Recherches Subatomiques) Strasbourg - France

The front end module - consisting of an AC coupled Double Sided Silicon Strip Detector (DSSSD) and the corresponding Front End Electronics assembly (FFE) with the remote controlled ALICE128C low power, extended range, front end chip and the COSTAR control chip - has been designed, developed and tested to achieve the tracking requirements of the ALICE ITS as well as of the STAR SVT. New TAB interconnection technique is replacing all the front end wiring. Several production samples have been tested on PS and the SPS beams at CERN whereas one assembled test sample has also been irradiated on the Vivitron at IReS. Production and testing data of the components is filling the production database and module assembling and testing is starting.

Design and test of a readout chip for LHCb

Daniel Baumeister, Max-Planck-Institute for Nuclear Physics, Heidelberg, Germany

Niels van Bakel, Jo van den Brand, Hans Verkooijen (Free University of Amsterdam / NIKHEF Amsterdam)

Daniel Baumeister, Werner Hofmann, Karl-Tasso Knoepfle, Sven Loechner, Michael Schmelling, Edgar Sexauer (Max-Planck-Institute for Nuclear Physics, Heidelberg)

Martin Feuerstack-Raible (University of Heidelberg)

Neville Harnew, Nigel Smale (University of Oxford)

For the LHCb experiment a first prototype of a 128 channel analogue pipeline chip, named Beetle, has been developed and submitted in a standard 0.25 um CMOS process. It integrates 128 channels with charge sensitive preamplifiers and shapers, whose outputs are sampled with 40 MHz into an analogue pipeline with a maximum latency of 160 sampling intervals. A comparator behind the shaper provides a binary signal. The 128 channels can be multiplexed on either 4, 2 or 1 outputs. The bias settings are programmable and monitorable via a standard I2C-interface. The architecture of the chip is described as well as simulation and test results are presented.

Implementation of the ASDBLR and DTMROC ASICS in DMILL Technology

Mitch Newcomer, University of Pennsylvania, Philadelphia Pa., USA

C. Alexander, F. Anghinolfi, R. Van Berg, N. Dressnandt, T. Ekenberg, Ph. Farthouat, P. T. Keener, N. Lam, D. Lamarra, J. Mann, F. M. Newcomer, V. Ryjov, M. Soderberg, R. Szczygiel, H.H. Williams

University of Pennsylvania, Philadelphia Pa.

The ASDBLR and DTMROC chipset provide detector mounted signal processing, time digitization, pipelining and level 1 sparsification for the ATLAS TRT tracking and transition radiation detector subsystem. Due to high levels of radiation in the detector environment, the radiation hardened DMILL BiCMOS technology was chosen for fabrication. A multi-institutional effort that included significant analog and digital simulation led to the fabrication of these two highly successful designs in the fall of 1999. Test beam measurements utilizing these ASICS to readout detector prototypes indicate that the chipset is capabable of meeting the design requirements of the TRT.

Digital Implementation of a Tail Cancellation Filter for the Time Projection Chamber of the ALICE Experiment

Bernardo Mota, CERN, Geneva, Switzerland

R.E.Bosch, B. Mota, L. Musa

CERN, Geneva (Switzerland)

FOR THE ALICE COLLABORATION

In the ALICE TPC, the readout chambers are conventional multiwire proportional chambers with cathode pad readout. The pad signal has a rather complex shape, which depends on the details of the chamber and the pad geometry, characterized by a long tail due to the motion of the positive ions. Since the zero suppression has to be done before the data transfer, the high channel occupancy calls for a very precise tail suppression. In order to be compatible with the required dE/dx resolution, a suppression to 0.1% or better of the maximum pulse height, is required. We present a digital implementation of a shortening filter based on the approximation of the tail by the sum of exponential functions. The hardware implementation of the filter is described and the results analyzed.

A data driven high-resolution Time-to-Digital Converter

Jorgen Christiansen, CERN, Geneva, Switzerland

J. Christiansen, A. Marchioro, P. Moreira, M. Mota, V. Ryjov CERN, CH-1211 Geneva, 23 Switzerland

S. Débieux Engineering School of Geneva, Microelectronics Lab, Geneva, Switzerland

A data driven multi-channel Time-to-Digital Converter (TDC) circuit with programmable resolution (25ps - 800ps binning) has been implemented in a 0.24um CMOS technology. An on-chip PLL is used for clock multiplication up to 320MHz from an external 40MHz reference. A 32 element Delay Locked Loop (DLL) performs time interpolation down to 97.5ps. Finally, finer time interpolation is obtained using an on-chip RC delay line. Time measurements are processed and buffered in a data driven architecture based on time tags. This results in a highly flexible triggered or non-triggered TDC which can be used in many different experiments.

A simplified and accurate front-end electronics chain for timing RPCs

Paulo Fonte, LIP and ISEC, Coimbra, Portugal

A. Blanco ¹, N. Carolino ¹, P. Fonte ^1,2, R. Ferreira-Marques ^1,3, A. Gobbi ⁴

(for the ALICE collaboration)

¹ LIP, Coimbra, Portugal.

² ISEC, Quinta da Nora, Coimbra, Portugal.

³ Departamento de Física da Universidade de Coimbra, Coimbra, Portugal.

⁴ GSI, Darmstadt, Germany.

Recent advances in electronics and construction techniques have pushed the timing resolution of Resistive Plate Chambers below 50 ps sigma with detection efficiencies close to 99% for MIPs. In this paper we describe a new front-end electronics chain for accurate time and charge measurement in these devices, having in view a possible application in ALICE's T0 counter. The circuit is built solely from commercially available and inexpensive integrated circuits, featuring a reduced number of components. It includes a fast (2 GHz bandwidth) two-stage amplifier that feeds a fixed threshold discriminator followed by an external TDC. The amplified signal is also buffered into an external ADC for charge digitization. The chain was tested with realistic test signals from an RPC, yielding a timing resolution around 10 ps sigma for signal charges above 100 fC and a charge resolution of 5 fC.

DILOGIC-2 A Sparse Data Scan Readout Processor for the HMPID DETECTOR OF ALICE

Jean-Claude Santiard, CERN, Geneva, Switzerland

H. Witters, IMEC vzw, 3001 Leuven, Belgium (witters@imec.be)

J.C. Santiard, CERN, Geneva, Switzerland (jean-claude.santiard@cern.ch)

Paolo Martinengo, CERN, Geneva, Switzerland (paolo.martinengo@cern.ch)

For the ALICE collaboration

Processing of analog information are always spoiled by additional DC level and noise given by the sensors or their additional readout electronic. The Dilogic-2 ASIC circuit has been developed in a 0.7um n-well CMOS technology to process the data given by Analog to Digital Converters, in order to eliminate the empty channels, to subtract the base line (pedestal) and store locally the true analog information.

Richard Breedon, University of California, Davis CA, USA

R.E. Breedon, B. Holbrook, Winston Ko, D. Mobley, P. Murray, S.M. Tripathi

University of California, Davis, CA 95616 USA

The 16-channel, 96-cell per channel switched capacitor array (SCA) ASIC developed for the cathode readout of the cathode strip chambers (CSC) in the CMS endcap muon system is ready for production. For the final full-sized prototype, the Address Decoder was re-designed and LVDS Receivers were incorporated into the chip package. Under precision testing, the chip exhibits excellent linearity within the 1V design range and very low cell-to-cell pedestal variation. Performance of the SCA during beam tests of a fully-instrumented chamber and results from radiation testing at a 63.3 MeV proton cyclotron will be presented.

The "MAD", a Full Custom ASIC for the CMS Barrel Muon Chambers Front End Boards

Franco Gonella, INFN, Padova, Italy

Franco Gonella and Matteo Pegoraro from INFN - Sez. Padova (Italy)

Front end electronics of CMS barrel muon chambers is built around a full custom ASIC, named MAD, designed and developed by INFN Padova, that provides amplification, discrimination and cable driving circuitry for a quadruplet of drift tubes. The system is organized in compact boards located in the gas volume and includes I2C slow control features for channels enable/disable and temperature monitoring, and a flexible test pulse system for calibration purposes. Attained results confirm the good performances of the system; particularly, big effort was put in radiation tests (neutron, gamma rays and ions) to check behavior and reliability in LHC environment.

Performance and Radiation Tolerance of the ATLAS CSC On-Chamber Electronics

Kurt Vetter, Brookhaven National Laboratory, Upton NY, USA

A. Gordeev, V. Gratchev, A. Kandasamy, P. O'Connor, V. Polychronakos, V. Tcherniatine, K. Vetter

Brookhaven National Laboratory

J. Dailing, N. Drego, D. Hawkins, A. Lankford, Y. Li, S. Pier, M. Schernau, D.Stoker, B. Toledano

University of California, Irvine

The on-detector electronics for the ATLAS Cathode Strip Chamber (CSC) performs amplification, analog buffering, and digitization of the charge signals from individual cathode strips. Working in a high-rate environment (strip hit rate up to several hundred kHz) the system requires a signal-to-noise ratio of 200:1 and a dynamic range of 10 bits. Radiation conditions are: ionizing dose of 4.4 krad/yr and neutron flux of 7x10^12 n/cm^2/yr. The system consists of 320 chamber-mounted ASM boards serving a total of over 61,000 channels. Performance and radiation tolerance of ASM prototypes will be discussed.

Dominique Breton, Laboratoire de l'Accelérateur Linéaire, Orsay, France

E. Delagnes, P. Borgeaud

CEA, DSM/DAPNIA Saclay, 91191 Gif-sur-Yvette, France.

E. Auge, D. Breton, G. Martin-Chassard, V. Tocut

Laboratoire de l'Accelérateur Linéaire, IN2P3-CNRS et Université Paris-Sud, 91405 Orsay Cedex, France.

J. Parsons, W. Sippach

Nevis Laboratories, Columbia University, Irvington, NY 10533, USA

An 12 channel analog memory dedicated to the readout of the Atlas liquid argon calorimeter has been developed. Its main function is to sample, at a 40 Mhz rate, the data coming from a three gain shaper, to store it, waiting for the level-1 trigger decision, and then to send it more slowly (5MHz) towards a 12 bit ADC. For each trigger, the ADC will digitize 5 samples. As the system is supposed to present minimum dead time, the write operations will be unceasing even during the read phases. The chip can thus be seen as a simultaneous double random access analog memory array. The read and write addresses are generated by a separate controller chip and sent together with other control signals to the analog memory using low-voltage swings. In the ATLAS calorimetry, the electronics will have to withstand a total ionising dose higher than 20 krad over a 10 year lifetime. For reliability, the circuit may survive to a total dose of 100krad. Thus the chip has been developed in DMILL technology. The presentation will highlight the amazing level of performance achieved by this circuit whose dynamic range is far in excess of 13 bits even while undergoing simultaneous write and read accesses.

Calibration of the ATLAS Hadronic End-Cap Calorimeter

Pavol Strizenec, Institute of Experimental Physics SAS, Kosice, Slovakia

H. Brettel, W.D. Cwienk, L. Kurchaninov, H. Oberlack, P. Schacht

Max-Plank-Institute for Physics, Munich, Germany

A. Jusko, P. Strizenec

Institute of Experimental Physics SAS, Kosice, Slovakia

On behalf of the ATLAS HEC Collaboration

The calibration chain of the ATLAS HEC is described. A model based on detailed studies of all individual parts is presented. The characteristics of the steering and data taking system for both the test-beam runs and for the acceptance tests of the HEC modules is summarized. The calibration and signal reconstruction procedure is developed and results of the test-beam data are presented.

An electronic calibration for the readout chain of the ECAL-CMS

Jean-Pierre Mendiburu, LAPP, Annecy-le-Vieux, France

Youngwook Baek, Daniel Boget, Pierre Zves Davis, Jean Ditta, Nadia Fouque, Jean Pierre Mendiburu

LAPP Annecy-le-Vieux

A calibration system has been developed in 0.8 m DMILL technology for ECAL-CMS. It consists of several logic and analogic chips that have been funded, and tested in lab and in irradiation beams.

The CMS ECAL APD quality assurance facility

Sacha Singovski, University of Minnesota, Minneapolis, MN, USA

The CMS ECAL APD project is entering the mass production phase. Some 3,500 APD's from Hamamatsu where investigated in detail during the preceding R&D. The summary of results obtained with these devices will be shown together with the detailed description of the tests made and dedicated measurement setups.

Thomas Toifl, CERN, Geneva, Switzerland

Thomas Toifl, Paulo Moreira, Alessandro Marchioro

CERN

The Timing, Trigger and Control Receiver Asic (TTCrx) receives and distributes the clock, the trigger decision, and other synchronisation signals. In this paper the radiation-hard version of the TTCrx, manufactured in DMILL technology, is discussed. First, the architecture of the circuit is described, where we concentrate on the changes to the existing prototype and on the measures taken to increase robustness with respect to single event upsets (SEU). In the second part we will present measurements of the circuit characteristics before and after irradiation with gammas and neutrons. In the last part we will then show measurements of the SEU behavior.

Radiation Test of CMS Endcap Muon Front-end Electronics with 63 MeV Protons

Ta-Yung Ling, The Ohio State University, Columbus, Ohio, U.S.A.

After brief overview of the CMS EMU electronics system, results on Single Event Effects, TID and Displacement Effects due to neutron and ionizing radiation will be reported. These results are obtained by irradiating the front-end electronics boards with 63 MeV protons. During the irradiation, the electronics board was fully under power, all ASICs and COTS on the board were active and the data was readout in the same way as designed for CMS.

Radiation Tolerance Evaluation of the ATLAS RPC Coincidence Matrix Submicron Technology

Riccardo Vari, INFN, Roma, Italy

E. Gennari, E. Petrolo, A. Salamon, R. Vari, S. Veneziano

INFN - Sezione di Roma

P.le Aldo Moro 2 - Rome - Italy

The Coincidence Matrix ASIC is the central part of the ATLAS Level-1 Muon Trigger in the barrel region; it performs the trigger algorithm and data read-out. The ASIC will be mounted on dedicated boards on the Resistive Plate Chamber detectors. The chosen technology has to guarantee complete functionality in the ATLAS RPC radiation environment. Radiation tests have to satisfy the radiation tolerance criteria proposed by the ATLAS Policy on Radiation Tolerant Electronics. The ATLAS standard test methods has to be followed in order to guarantee both total dose and single event effects tolerance. A frequency multiplier ASIC was used for technology evaluation and radiation tests. The chip is a low jitter programmable clock multiplier, realised in 0.25 micron CMOS technology. This frequency multiplier is intended to be used in the Coincidence Matrix ASIC as a macro, to perform the internal clock frequency multiplication. Radiation test results will be presented.

First evaluation of neutron induced Single Event Effects on the CMS barrel muon electronics

Pierluigi Zotto, Politecnico, Milano, Italy and INFN, Padova, Italy

S. Agosteo ¹, L. Castellani ², A. Favalli ¹, I. Lippi ², R. Martinelli ² and P. Zotto ³

¹ Dip. di Ingegneria Nucleare (CESNEF) del Politecnico di Milano, Italy

² Dip. di Fisica dell'Universita and sez. INFN, Padova, Italy

³ Dip. di Fisica del Politecnico di Milano and sez. INFN di Padova, Italy

Neutron irradiation tests of the currently available electronics for the CMS barrel muon detector were performed using thermal neutrons and fast neutrons at E < 11MeV. The Single Events Upset on the Static RAM was measured, while upper limits are derived for devices having experienced no failure. The results are used to guess the upper limits on the mean time between failures in the whole barrel muon detector.

SEU tests of an 80Mbit/s optical receiver

Federico Faccio, CERN, Geneva, Switzerland

F. Faccio, K. Gill, M. Huhtinen, A. Marchioro, P. Moreira, F. Vasey

CERN, CH-1211 Geneva 23, Switzerland

G. Berger

Cyclotron Research Center, UCL, B-1348 Louvain-la-Neuve, Belgium

The sensitivity to SEU is presented for a rad-hard 80Mbit/s receiver developed for the CMS Tracker digital optical link. Bit Error Rate (BER) measurements were made while irradiating with 59MeV protons and 62MeV neutrons, for different angles to the beam and for a wide range of optical power in the link. The photodiode is the most sensitive element to SEU. Direct ionisation can explain the SEU rate for protons incident at high angles of incidence and nuclear interactions explain the SEU rate for incident neutrons, as well as for protons for the low angles of incidence and higher optical power.

Redundancy or GaAs ? Two different approaches to solve the problem of SEU (Single Event Upset) in a digital optical link

Bernard Dinkespiler, Southern Methodist University, Dallas, TX, USA

From SMU: Ryszard Stroynowski, Bernard Dinkespiler, Jingbo Ye, Shouxuan Xie

From CPPM: Frederic Rethore

From ISN: Marie-Laure Andrieux, Laurent Gallin-Martel

From KTH: Mark Pearce, Johan Lundqvist, Stefan Rydstrom

The fast digital optical links for the ATLAS Liquid Argon Calorimeter must survive in a high radiation environment with a total fluence of 2*1013 neutrons/cm2 and 800 Gy. The links based on Agilent Technologies -former HP- Glink chipset show a total dose radiation resistance to neutrons and gammas that would allow for 10 years of operation in the ATLAS detector. We have observed, however, an unacceptable rate of single event upsets (SEU) due to neutrons interacting in the silicon-based serializer. In order to solve this problem, we have developed two link systems. The first one - Dual-Glink-, is based on the principle of redundancy. Data are sent on two independent links. On the reception side, data are analyzed and error recovery is performed without dead time.

The second solution uses a GaAs serializer/deserializer chipset from TriQuint. This technology is intrinsically radiation hard. We expect a minimal number of SEU's and other radiation related problems. High speed of this chipset -2.5 Gb/s- allows for error recovery. The design of the link, its performance in the laboratory environment and the results of the radiation tests will be presented for both systems.

Single Event Upset measurements on the Resistive Plate Chambers Front-End chip for the Compact Muon Solenoid experiment

Antonio Ranieri, Università e INFN, Bari, Italy

M. Abbrescia, A. Colaleo, G. Iaselli, F. Loddo, M. Maggi, B. Marangelli, S. Natali, S. Nuzzo,

G. Pugliese, A. Ranieri, F. Romano

(Dipartimento Interateneo dell'Università di Bari e I.N.F.N. Sezione di Bari)

S. Altieri, G. Belli, G. Bruno, S.P. Ratti, P. Torre, P. Vitulo

(Dipartimento di Fisica Nucleare e Teorica dell'Università di Pavia e I.N.F.N. Sezione di Pavia).

A measurement of irradiation damaging has been made on the analog front-end electronics of the RPC detector in the CMS experiment. The measurements were performed according to the estimated neutron fluence foreseen in the most irradiated area of the apparatus. The test results are shown, considering all the possible irradiation effects on the custom RPC front-end electronics, encouraging us on the use of the 0.8m Bi-CMOS technologies from AMS, chosen for such type of application.

Single Event Upset Studies on the APV25 Readout Chip

Jonathan Fulcher, Imperial College, London, UK

J Fulcher, G Hall, E Noah , M Raymond

Imperial College, London, UK

D Bisello, G. Marseguerra, J Wyss

Padova University, Padova, Italy

M French, L Jones, Q Morrissey, A Neviani

Rutherford Appleton Laboratory, Didcot, UK

The microstrip tracker for the CMS experiment at the LHC will be read out using APV25 chips. During high luminosity running of the LHC the tracker will be exposed to particle fluxes up to 107 cm2 s-1. This high rate of particles introduces a concern that the APV25 could occasionally suffer from Single Event Upset (SEU). In order to evaluate the expected upset rate under these circumstances the APV25 was run under controlled conditions in a heavy ion beam. This enabled the measurement of the SEU upset cross-section, and hence a prediction of the upset rate in CMS. The upset cross-section for a range of particle LETs (Linear Energy Transfer) was measured and the referred threshold energy and saturated cross-section was evaluated. These data are then used to predict the upset rate for the APV25 in the CMS tracker.

Overview of the ATLAS LAr front-end radiation tolerance

Christophe de La Taille, LAL, Orsay, France

The front-end electronics of the ATLAS liquid argon calorimeter must withstand a non-negligible radiation environment (20Gy/yr 5e11N/cm2/yr), in particular when various safety factors (simulation inaccuracies, lots variability or low dose rate effects) are put on top. The design of all the front end elements is now complete and has been tested on module0 on over 2,000 channels. Several key components have been extensively tested to radiation exposure (preamps, shapers, pipelines...) whereas other circuits (mostly digital) are being now migrated into DMILL. The results of these tests will be summarized and the design of the DMILL chips will be presented. The next milestone of the LAr collaboration is to have a final radiation hard complete front-end prototype by mid July.

Overview of the ATLAS Policy on Radiation Tolerant Electronics

Martin Dentan, CERN, Geneva, Switzerland and CEA-DAPNIA, Gif-sur-Yvette, France

Martin Dentan, CERN & CEA-DAPNIA

Philippe Farthouat, CERN

ATLAS Sub-systems will integer a very large quantity and variety of electronics boards which will be submitted to radiations ranging from few krads and few 1E10 n/cm2 to few 10 Mrads and few 1E14 n/cm2, and to energetic particles capable of producing SEE (Single Event Effects). ATLAS Technical Coordination has developed in collaboration with the Sub-systems a new policy on radiation tolerant electronics. It provides guidelines for the pre-selection and for the qualification of all the commercial electronics components that will be used in ATLAS, in order to make sure they will resist to the foreseen radiation constraints. This paper summarises the main guidelines given in the ATLAS Policy on Radiation Tolerant Electronics, and the benefits resulting from this policy.

Instrumentation amplifiers and voltage controlled current sources for LHC cryogenic instrumentation

Juan Agapito, Universidad Complutense, Madrid, Spain

J. A. Agapito³, F. M. Cardeira², J. Casas¹, A. P. Fernandes², F. J. Franco³, P. Gomes¹, I. C. Goncalves², A. Hernandez Cachero³, J. Lozano³, M. A. Martin³,

J. G. Marques², A. Paz³, A. J. G. Ramalho², M. A. Rodriguez Ruiz¹ and J. P. Santos³.

¹ CERN, LHC Division, Geneva, Switzerland.

² Instituto Tecnol&cent;gico e Nuclear (ITN), Sacav‚m, Portugal.

³ Universidad Complutense (UCM), Electronics Dept., Madrid, Spain.

Two different topologies for the basic instrumentation amplifier have been studied. Both amplifier and current source circuits have been designed, constructed and tested under radiation. All radiation campaigns have been carried out in ITN (Portugal) research nuclear reactor. A new facility for neutron beam extraction has been constructed. On line measurements of the offset voltages, offset currents, closed loop gain, and bias currents have been performed on the two structures for two different operational amplifiers, OPA124 & TLE2071. A study of the influence of each individual parameters to the whole has been carried out. Three voltage controlled current sources have been made with every instrumentation amplifier. Three values of current for each set of amplifiers have been fixed, adjusted to the different ranges of measurement of the cold mass temperature sensor. On line measurements of the currents are presented as a function of neutron radiation. And finally on line measurements of commercial voltage references are presented as a function of radiation.

Developments for Radiation Hard Silicon Detectors by Defect Engineering - Results of the CERN RD48 (ROSE) Collaboration

Gunnar Lindstroem, University of Hamburg, Germany

(cospokesman of RD48) on behalf of the RD48 collaboration

The success of the Oxygen enrichment of FZ silicon as a highly powerful defect engineering technique and its optimization with various commercial manufacturers are reported. Major focus is on the changes of the effective doping concentration (depletion voltage). Other aspects (reverse current, charge collection) are covered too. Diode characteristics of test pad- and LHC-strip detectors are compared. The RD48 model for the dependence of radiation effects on fluence, temperature and operational time is verified; projections to operational scenarios for main LHC experiments demonstrate vital benefits. Present microscopic understanding of damage effects including differences caused by charged and neutral hadrons are discussed too.

(cd 21 August 2000)