LEB 2000 - POSTERS SESSION

Development of a 24 ch TDC LSI for the ATLAS Muon Detector

Yasuo Arai, KEK, National High Energy Accelerator Research Organization, Institute of Particle and Nuclear Studies
and
T. Emura, Tokyo University of Agriculture and Technology
 

A TDC LSI for the ATLAS precision muon tracker (MDT) has been developed. A prototype chip (AMT-1) was processed in a 0.3 um CMOS Gate-Array technology. It contains full functionality of the final TDC. To get a high resolution around 300 ps, an asymmetric ring oscillator and a PLL circuit are used. All the I/O signals which are active during measurement has LVDS interfaces. A JTAG interface is used for boundary scan and internal register setup. All the memory and control bits has parity bits so that a SEU can be detected. Radiation tolerance for Gamma-ray and Neutron are also reported.

Implementation of Sorting Schemes in a Programmable Logic

Mikhail Matveev (Rice University, Houston, TX 77005)

Trigger systems of each CMS muon subdetector (Cathode Strip Chambers, Drift Tubes, Resistive Plate Chambers) will have a muon sorter unit in their upper parts. We report on a design and simulation results for the following sorting schemes: "3 objects out of 18", "4 objects out of 8", "4 objects out of 24" and "4 objects out of 36". All designs are targeted to a single chip implementation based on Altera 20KE Programmable Logic Devices (PLD). The PLD internal sorting latency varies between 1 and 3 cycles of 40MHz clock frequency. Proposed schemes can be used for the fast sorting at the CMS Muon subsystems as well as other trigger systems at LHC experiments.

Silicon DAQ based on FPDP and RACEway

Piotr KULINICH  for the PHOBOS collaboration

DAQ for Si-detector of PHOBOS setup (RHIC) with Scalable Power for read out and Zero Suppression is described. Data from VA-HDR chips with analog multiplexor, are digitized by FADC. Digital buffers are multiplexed by DMU modules at speed 100 MBytes/sec and transmitted through FPDP and virtual extender of FPDP to fiber (FFI). At the receiver end (in counting house) data from fiber are distributed between a number of dedicated processors (in RACEway multiprocessor frame) for Zero Suppression. After ZS data are concatenated and transmitted to Event Builder.

Optical Data Transmission from the CMS Cathode Strip Chamber Peripheral Trigger Electronics to Sector Processor Crate

N.Adams, M.Matveev, T.Nussbaum, P.Padley (Rice University)
J.Hauser, V.Sedov (UCLA)

Data representing three muons will be sent from each sector of the CMS Cathode Strip Chambers to the Sector Processor crate residing in the counting room 100 m apart of the detector. We report on the data transmission scheme based on Agilent HDMP-1022/1024 serializer/deserializer chipset and Methode MDX-19 optical transceivers. Six chipsets and six pairs of optical modules are needed in order to transmit 120 bits of data every 25 ns of the main LHC frequency from the peripheral Muon Port Cards to Sector Receiver modules. Results of prototyping, laboratory tests as well as a possible future options for data transmission are discussed.

Custom chips developed for the trigger/readout system of the ATLAS end-cap muon chambers

H.Kano, C.Fukunaga, Tokyo Metropolitan University,
M.Ikeno, O.Sasaki, T.K.Ohska, KEK (National Organization for high energy accelerator physics),
R.Ichimiya, H.Kurashige, Kobe University,
S.Nishida, H.Sakamoto, Kyoto University,
K.Hasuko, Y.Katori, T.Kobayashi, T.Niki, and D.Toya, University of Tokyo

Three custom ASICs are now being developed for the trigger/readout system of the ATLAS end-cap muon chambers. Each chip is the master component in three out of four subparts of the system. Beside the standard circuitry as an ATLAS subsystem, several implementations have been devised in each chip, which are required from various physical and boundary conditions as an electronics system for the end-cap muon chambers. We discuss the implementation of the level-1 muon identification logic as well as these customarily developed data handling technology

Low Noise Amplifier

J.D. Schipper, NIKHEF
R. Kluit,NIKHEF

As a design study for the LHC experiments a 'Low Noise Amplifier Shaper' for capacitive detectors is developed. This amplifier is designed in 0.6 um technology from AMS. The goal was to design an amplifier with a noise contribution of 250 electrons, a 12 electrons per pF contribution from the input capacitor and a relative high gain. A test chip with two versions of the amplifier, a 'radiation tolerant' (gate-around FET's) and a 'normal' version has been fabricated and is now under test. These designs and there characteristics, simulated and measured, will be compared and discussed.

A FAST BINARY FRONT-END IMPLEMENTED IN A 0.25 UM CMOS TECHNOLOGY USING A NOVEL CURRENT-MODE TECHNIQUE

D. Moraes(1), F. Anghinolfi(1), P. Deval(2), P. Jarron(1), A. Rivetti(1).

(1)CERN, CH-1211 Geneva 23, Switzerland.
(2)MEAD Microlectronics S.A., Venoge 7, 1025 St. Sulpice, Switzerland.

A prototype of an IC has been developed with a very fast and low noise preamplifier, using a 0.25micron CMOS technology. The prototype contains a low- and high gain version of the preamplifier. It was designed to have an input impedance below 10 Ohms and an peaking time of 10ns at an input capacitance of 20pF. The low gain version was specially developed to be used on the Cathode Pad Chambers of the LHCb Muon System, where a very low threshold combined with high speed and low noise are required in order to obtain high efficiency and good time resolution.

The nonlinear behaviour of p-i-n diode in high intense radiation fields

P.K.Skorobogatov, A.S.Artamonov, B.A.Ahabaev Specialized electronic systems

The dependence of p-i-n diode ionizing current amplitude vs dose rate is defined using twodimensional software simulation. It is shown that analyzed dependence becomes nonlinear beginning with relatively low dose rates near 107 rad(Si)/s. This effect is connected with the modulation of p-i-n diode intrinsic region by irradiation. As a result the distribution of electric field becomes non-uniform that leads to decrease of excess carriers collection. The ionizing current pulse form becomes more prolonged because of delayed component contribution. It is necessary to take into account when p-i-n diode is used as dose rate dosimeter. The p-i-n diodes are widely used for the measurements of ionizing radiation dose rates. The high electric field in its intrinsic region provides the full and fast excess carriers collection. As a results the ionizing current pulse waveform repeats the ionization pulse with the accuracy of several nanoseconds. To investigate the p-i-n diode possibilities at high dose rates the original software simulator "DIO-DE-2D" [1] was used. The "DIODE-2D" is the fundamental system of equations two-dimensional solver. It takes into account carrier generation, recombination and transport, optical effects, carrier's lifetime and mobility dependencies on excess carriers and doping impurity concentrations. The typical p-i-n diode with 380 micrometers intrinsic region width under 300 V reverse bias was investigated. The simulation of p-i-n diode structure have shown that linear dependence between dose rate and ionizing current is valid only at relatively low dose rates up to 107 rad(Si)/s. In the field of high dose rates this dependence becomes non-linear and ionizing current increases more slowly than dose rate. The reason of non-linearity is connected with the modulation of p-i-n diode intrinsic region by excess carriers. Because of low level of initial carriers concentration the modulation takes place at relatively low dose rates. As a result of modulation the distribution of electric field in the intrinsic region becomes non-uniform that leads to decrease of excess carriers collection. The behavior of p-i-n diode becomes similar to that of ordinary p-n junction with prompt and delayed components of ionizing current. The prompt component repeats the dose rate waveform. The delayed component is connected with the excess carriers collection from regions with low electric fields. As a result the ionizing current pulse form becomes more prolonged and dose not repeat the dose rate waveform. The numerical results were confirmed by experimental measurement of p-i-n diode ionizing reaction in wide range of ionizing radiation dose rates. The non-linear character of behavior and prolonged reaction must be taken into account when p-i-n diode is used as dose rate dosimeter.

References [1]. The "DIODE-2D" Software Simulator Manual Guide, SPELS, 1995.

Use of external resistor to prevent radiation induced latch-up in commercial CMOS IC's

P.K.Skorobogatov, A.Y.Nikiforov, A.A.Demidov Specialized electronic systems

It is shown that in the case of external resistor usage to prevent radiation induced latch-up in commercial CMOS IC's we have the increase of IC recovery time up to tens of microsecond due to deep saturation of parasitic bipolar transistors. Under numerical calculations it was found that there is an optimal value of external resistor that provides the minimal
recovery time of IC.  The usage of commercial CMOS IC's in radiation environment is restricted by the possibility of its latch-up behaviour under irradiation. The external resistor in power supply circuit is a well-known way to prevent latch-up. This method is found on the restriction of IC power supply current to the level lower than latch-up holding current. The experiments were shown however that in this case we unfortunately have the increase of IC recovery time up to tens of microsecond. Under numerical calculations it was found that this effect is connected with deep saturation of parasitic bipolar transistors on the external resistance. It was found that there is an optimal value of external resistor that provides the minimal recovery time of IC. In the case of low resistance the large recovery time is connected with deep level of parasitic transistors saturation. In the case of high resistance value the recovery time is defined by well-substrate p-n junction ionizing current delayed component voltage drop on the external resistance that increases with resistance growth. For CMOS IC's under investigation the optimal value was near 80 Ohm. This effect must be taken into account when commercial CMOS IC's are used in radiation environment.

Fiber Optic based readout for BTeV's Pixel Detector

Gustavo I. E. Cancelo*, Sergio Zimmermann*, Sergio Vergara**, Peter Denes*, Guilherme Cardoso*, Bob Downing*, Jeff
Andresen* * Fermilab, **University of Puebla, Mexico

The current paper describes the design of BTeV's Fiber Optics Pixel Detector readout. The pixel detectors will be located as close as 6mm from the accelerator's beam into the vacuum pipe. The readout electronics will be located at about 6cm from the beam, imposing strong constrains regarding radiation, mass, power dissipation, vacuum and size. This paper includes an analysis of the convenience of using a fiber optic based readout versus alternative solutions. Since the current design will place several components in a high dose proton and gamma radiation environment the fiber optic based readout will need some radiation hardened custom components, which are here specified. Furthermore, test results on optoelectronic devices are provided along with future plans to complete the design.

HIGH-SPEED COMPARATOR IC WITH LOW TIME DISPERSION

E.V.Atkin, Moscow Engineering Physics Institute

The high-speed comparator for fast time reference is represented. It can be used as a leading edge discriminator or as a core for building constant fraction discriminator and can be useful for the development of time-of-flight systems.  It is manufactured with a bipolar process. Its main feature is a small time dispersion of output signal (200 ps) at the presence of a wide dynamic range of input signals (overdrives from 10 mV to 1V). This paper describes the approach to the design of the new version of a low time dispersion comparator. The structure of such a comparator, features of schematics of its separate stages and its parameters are described.

 A BiCMOS discriminator interface for the SPD

A. Diéguez, S. Bota Departament d'Electrònica, Sistemes d'Instrumentació i Comunicacions, Universitat de Barcelona, C/Martí
Franquès, 1, E-08028, Barcelona. Spain

D. Gascón, L. Garrido Departament d'Estructura i Constituents de la Matèria, Universitat de Barcelona, C/Martí i Franques
1, E-08028 Barcelona. Spain.

M. Roselló Departament d'Electrònica, Enginyeria i Arquitectura La salle, Universitat Ramon Llull, Pg. Bonanova 8, E-08022,
Barcelona. Spain.

A prototype chip for the analogue readout of the SPD in the LHCb Calorimeter is presented. The chip has been designed using the 0.8mm-BiCMOS technology of AMS and optimised for minimum size and maximum performance at the required frequency of operation in LHC experiments. It consists of a dual structure formed by two integrators, two track and hold circuits, two substractors, two comparators and a multiplexer. The die size occupied by one discriminator circuit is approximately 1720mm x 330 mm.

The Muon Pretrigger System of the HERA-B Experiment

M.Adams (Universitaet Dortmund), P.Bechtle (Universitaet Dortmund), P.Buchholz (Universitaet Dortmund), C.Cruse
(Universitaet Dortmund), U.Husemann (Universitaet Dortmund), E.Klaus (Universitaet Dortmund), N.Koch (Universitaet
Dortmund), M.Kolander (Universitaet Dortmund), I.Kolotaev (ITEP Moscow and Universitaet Dortmund), H.Riege (Universitaet
Hamburg), J.Schuett (Universitaet Hamburg), B.Schwenninger (Universitaet Dortmund), R.van Staa (Universitaet Hamburg),
D.Wegener (Universitaet Dortmund)

The muon pretrigger system of the HERA-B experiment is used to find muon track candidates as one of the inputs of the first level trigger. Due to the interaction rate of 40 MHz required to achieve an accuracy of 0.17 on sin(2beta) the total input of the muon pretrigger system is about 10 GBytes/s. The latency to define muon track candidates should not exceed 1 microsecond. Therefore the muon pretrigger is implemented as about 100 large size VME modules in a highly parallelized architecture.
We will present the system as well as performance studies and first physics results.

First Level Trigger for H1, using the latest FPGA generation

M. Urban, A. Rausch, U. Straumann Physikalisches Institut Universitaet Heidelberg

To cope with the higher luminosities after the HERA upgrade, H1 builds a set of new MWPCs, which provide information to distinguish between beam background and true ep interactions. The first level trigger uses the latest 20K400 APEX FPGAs with 500 user IO pins to find tracks in 10000 digital pad signals. It allows to reconstruct the vertex and cut on its position. The system works deadtime free in a pipelined manner using 40 MHz clock frequency. The pipelines needed for data acquisition are also programmed into the same FPGAs. Test results including timing stability will be shown.

Possibility of SR8000 Supercomputer for ATLAS DAQ Event Building and Event Filtering

ANRAKU, Kazuaki (ICEPP, Univ. of Tokyo), IMORI, Masatosi (ICEPP, Univ. of Tokyo)

We are investigating the possiblity of adapting the SR8000 supercomputer system by Hitachi for ATLAS DAQ event building and event filtering. The SR8000 system is comprised of a number (up to 128) of nodes, each of which has RISC microprocessors sharing a main memory, and of high speed "multi-dimensional" inter-node network. The maximum total processing power amounts to 1024 GFLOPS and a bidirectional transfer rate of the inter-node network is 2 Gbyte/s. An arbitrary number of nodes can have I/O adapters of HIPPI, ATM, Ethernet, and Fast Ethernet. These features seem to be suitable to both the ATLAS DAQ event builder and event filter.

Design of a comparator in a 0.25µm CMOS technology

Niels van Bakel, Jo van den Brand (Free University of Amsterdam / NIKHEF Amsterdam), Hans Verkooijen (NIKHEF Amsterdam),
Daniel Baumeister, Werner Hofmann, Karl-Tasso Knoepfle, Sven Loechner, Michael Schmelling, Edgar Sexauer
(Max-Planck-Institute for Nuclear Physics, Heidelberg) Martin Feuerstack-Raible (University of Heidelberg), Neville Harnew,
Nigel Smale (University of Oxford)

A comparator for the LHC-B vertex detector front-end chip, the Beetle, has been designed in a 0.25µm CMOS technology and is sent for fabrication. To improve threshold uniformity, each comparator has a 3 bits DAC. The comparator can handle positive and negative inputsignals. A polarity signal changes the polarity of the threshold voltage and makes the outputsignal always positive when active. The outputsignal is latched by a 40MHz clock and is selectable between time-over-threshold (in 25ns bins) or active for one clockcycle. Simulation- and measurement results will be discussed.

Comparative study of current-mode versus voltage-mode analog memory in a 0.25um CMOS technology

F.VAUTRIN, J.MICHEL, F.BRAUN
LEPSI Strasbourg

The aim of this work is the study of switched-current and voltage-mode memory cells in order to develop a model including non-ideal effects such as charge injections,non-linear capacitance and readout system influence. These models will allow non-linearity control regard to surface, speed and power criteria in digital dedicated submicronic technology. Such models lead to a memory cell optimization in order to include it in an analog memory for LHC experiments.

A Novel Monolithic Active Pixel Sensor for Charged Particle Tracking and Imaging using Standard VLSI CMOS Technology

J.D. Berst, B.Casadei, G.Claus, C.Colledani, W.Dulinski, Y.Hu, D.Husson,
J.P.Le Normand, R.Turchetta, J.L.Riester LEPSI, IN2P3/ULP,
23 rue du Loess, BP20, F-67037 Strasbourg, France

G.Deptuch, U.Goerlach, S.Higueret, G.Orazi, M.Winter IReS, IN2P3/ULP,
23 rue du Loess, BP20, F-67037 Strasbourg, France

A novel Monolithic Active Pixel Sensor (MAPS) for charged particle tracking made in a standard CMOS technology is proposed. The sensor is a photodiode with a special structure, which allows the high detection efficiency required for tracking applications. The partially depleted thin epitaxial silicon layer is used as a sensitive detector volume. A first prototype has been designed and fabricated using a standard sub-micron 0.6 um CMOS process. It is made of four arrays each containing 64 times 64 pixels, with a readout pitch of 20 um in both directions. Extensive tests made with soft X-ray source ( 55 Fe) and minimum ionising particles (15 GeV/c pions) fully demonstrate the predicted performances, with the individual pixel noise below 20 electrons(ENC) and the Signal-to-Noise ratio of the order of 40, both for 5.9 keV X-rays and Minimum Ionising Particles (MIP). A new version of the circuit has been submitted to the 0.35 um Alcatel-Mietec process. This novel device opens new perspectives in high precision vertex detectors as well as in other applications.

Radiation hardness studies for CMS HF quartz fiber calorimeter

G. Dajkó, A. Fenyvesi, K. Makónyi, J. Molnár
Atomki, Debrecen, Hungary

P. Raics
University of Debrecen, Debrecen, Hungary

I.Dumanoglu
Cukurowa University, Adana, Turkey

J. P. Merlo
University of Iowa, Iowa City, USA

A Kerek, D. Novák
Kungl Tekniska Högskolan, Stockholm, Sweden

A project has been in progress to provide information on radiation hardness properties of Hamamatsu photomultiplier tubes and quartz-fibers to be used in the construction of CMS Very Forward Calorimeter. Neutron activation studies as well as neutron, gamma and electron radiation tolerance tests have been carried out, using 3.7 MeV average energy neutrons, 500MeV energy electrons and Co-60 gamma radiation. The test setups, the irradiation conditions as well as the experimental results are described.

Compact Bidirectional 2.5 Gbit/s Optical Transceiver for the H1-Experiment

S. Lueders, R. Baldinger, R. Eichler, C. Grab, B. Meier, S. Streuli, K. Szeker
Institute for Particle Physics, ETH Zuerich, 5232 Villigen PSI, Switzerland

For triggering purposes, 9600 channels have to be read out within 96 ns, i.e. with a rate of 100 Gbit/s, using 40 identical very compact optical transceiver units --- each measuring 130 mm x 45 mm x 9 mm. Taking advance of VCSEL diodes and 90 degree fiber bending, 4x 850 Mbit/s of digitized trigger information as well as two channels with analog monitoring information are transferred to the receiver electronics 40 m away. From there two channels of 10 MHz clock information are received for timing adjustments.

Mono-phase cooling system for front-end electronics on the example of the ATLAS TRT detector

Magnus Andersson - Luleå University of Technology Sweden
Pierre Bonneau - CERN
Michel Bosteels - CERN
Jan Godlewski - INP Krakow Poland, CERN

The work presents the results of cooling tests performed for the ATLAS TRT electronics. The test installation and control equipment are described.
A model of a standard cooling unit designed for all ATLAS detectors is also presented together with its modifications corresponding to various limitations connected with experimental zone, magnetic field, limited access and localization of various detectors.

Total Dose irradiation of a 0.25µm process

M. J. French
Rutherford Appleton Laboratory, Didcot, OXON, OX11 0QX, United Kingdom

I. Dindoyal, G. Hall, E. Noah, M. Raymond
Blackett Laboratory, Imperial College, London SW7 2AZ, United Kingdom

D. Bisello
University of Padova, Italy

A commercial 0.25µm process will be used for various electronic components of the CMS tracker, one of these being the APV25 readout chip for silicon microstrips. Irradiating and measuring individual transistors is important in assessing the radiation tolerance of the chip. Transistors from two different foundries owned by the same company were irradiated up to doses of 50Mrad(SiO2) with a 10keV X-ray source. Threshold voltage shifts of up to 140mV were observed whilst noise measurements showed very little degradation in the white noise region after irradiation and annealing. Detailed results of both static characteristics and noise will be presented.

Design and Characterization of a DAC for the Slow Control of the Pixel Chip

F. Corsi (*), R. Dinapoli (*)(#), P. Lamanna(*), C. Marzocca(*)
* Dipartimento di Elettrotecnica ed Elettronica - Poltecnico di Bari
# INFN - Sezione di Bari

A digital to analog converter for slow control of pixel front end chip has been designed in a 0.35 um standard CMOS technology to prove the effectiveness of the chosen circuit structures for this application. The DAC provides a total output current variation of about 15uA with an accuracy of 8 bits (LSB=60nA).  The DAC is based on a PMOS current bank (an NMOS of a reasonable size would operate in the weak inversion region for these current levels and would hence be unsuitable for accurate current sources). The bit value determines whether the current corresponding to these bit is switched to the output or not.  The occupied area is about 300um x 300um and total power dissipation is 85uW.  The results of the test measurements performed on the 36 fabricated prototypes show that statistical fluctuations of the output current due to mismatch are negligible compared to the desired accuracy for all the input configurations.

 Readout Unit Prototype for CMS DAQ System

G. Antchev, E. Cano, S. Cittolin, S. Erhan,
B. Faure, D.Gigi, J. Gutleber , C.Jacobs, F. Meijers,
E. Meschi, A. Ninane, L.Orsini, L. Pollet, A.Racz,
D. Samyn, N. Sinanis, W. Schleifer, P. Sphicas

CERN Div.EP/CMD, Switzerland

In the CMS data acquisition system, the Readout Unit (RU) is a major element of the Readout Column and it is placed between Front-end Devices (FED) and Builder Data Network (BDN). The RU is intelligent fast buffer for intermediate storage of data before transferring between the levels of the DAQ system. Readout Unit prototype is developed to achieve the CMS DAQ requirement for data input bandwidth of 400MB/sec and data output bandwidth of 400 MB/sec. The new RU prototype based on reconfigurable hardware structure and high-speed standard busses is presented in this paper.

A 400 MB/sec data link based on GE componants and reconfigurable hardware platforms

Attila Racz, Lucien Pollet
CERN Div.EP/CMD, Switzerland

In the context of large data acquisition systems for LHC experiments, simple and robust data links are required to transfer data from the  underground counting rooms up to the surface buildings where complex processing is performed on the data. In the case of CMS, ~500 of these links are needed with an individual throughput of 400MB/sec over a distance of 200m. A prototype based on standard Gigabit Ethernet components and a versatile hardware platform is presented in this article.

Minimizing crosstalk in a high-speed cable-connector assembly

B.J. Evans
E. Calvo Giraldo
T. Motos Lopez

CERN, IT/CE

This paper presents the detailed signal-integrity analysis results of a connector-cable assembly linking the ALICE Time Projection Chamber (TPC) to its Front-End Electronics.
The goal was to minimize the crosstalk (electromagnetic coupling) between signal lines for a given line to ground capacitance. Both mechanical (cable flexibility and strength) and electrical (fast signal rise-times) design constraints were considered.  The design was analysed using Finite Element Method software tools to extract equivalent circuit models for the connector and cable. We will show how these programs helped us to quickly investigate different cable configurations. The resulting PSpice simulations will be presented.

Single Event Upset Studies for the ATLAS SCT and Pixel Optical Links

D.G.Charlton, J.D.Dowell, R.J.Homer, P.Jovanovic, G.Mahout, H.R.Shaylor, J.A.Wilson

School of Physics and Astronomy, University of Birmingham,UK

R.L. Wastie, A.R. Weidberg

Physics Department, Oxford University, U.K.

J.K. Troska, D.J. White

Rutherford Appleton Laboratory, U.K.

I-M Gregor

Physics Department, Wuppertal University, Germany.

The readout of the ATLAS SCT and Pixel detectors will use optical links. The radiation hardness of all the components has been extensively studied but this paper discusses the operation of these links in simulated LHC radiation environments. Nuclear interactions can deposit large amounts of energy in electronic components which can cause Single Event Upsets (SEU). The SEU rates have been measured with MIPS from a beta source, low energy neutrons, pions and protons at PSI. The dominant source of SEU effects is from energy deposition in the active region of the PIN diodes.

cd 28 August 2000